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* Remove -fexceptions from llvmc tests.Mikhail Glushenkov2010-08-1317-17/+17
| | | | llvm-svn: 110999
* llvmc: fix two tests, remove XFAILs.Mikhail Glushenkov2010-08-132-6/+1
| | | | | | | Tested on Linux and Darwin; please add platform-specific XFAILs/mail me a bug report if this still fails. llvm-svn: 110998
* Reapply this transformation now that it is passing the external test which ↵Nate Begeman2010-08-131-0/+29
| | | | | | it previously failed. llvm-svn: 110987
* fix PR7876: If ipsccp decides that a function's address is takenChris Lattner2010-08-121-0/+28
| | | | | | before it rewrites the code, we need to use that in the post-rewrite pass. llvm-svn: 110962
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+6
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* - Teach SSEDomainFix to switch between different levels of AVX instructions. ↵Bruno Cardoso Lopes2010-08-121-0/+12
| | | | | | | | | | Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. - Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too. - Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX. - Add a testcase for a simple 128-bit zero vector creation. llvm-svn: 110946
* Add a test for llvm-gcc svn 110632.Bob Wilson2010-08-121-0/+16
| | | | llvm-svn: 110935
* Temporarily revert 110737 and 110734, they were causing failuresEric Christopher2010-08-121-29/+0
| | | | | | in an external testsuite. llvm-svn: 110905
* Begin to support some vector operations for AVX 256-bit intructions. The longBruno Cardoso Lopes2010-08-121-0/+15
| | | | | | | | | term goal here is to be able to match enough of vector_shuffle and build_vector so all avx intrinsics which aren't mapped to their own built-ins but to shufflevector calls can be codegen'd. This is the first (baby) step, support building zeroed vectors. llvm-svn: 110897
* The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen2010-08-121-0/+2
| | | | | | | | | | entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
* MC/X86/AsmParser: Give an explicit error message when we reject an instructionDaniel Dunbar2010-08-121-0/+5
| | | | | | because it could have an ambiguous suffix. llvm-svn: 110890
* This is x86 only test.Devang Patel2010-08-121-1/+1
| | | | llvm-svn: 110887
* Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen2010-08-111-0/+6
| | | | | | Added two test cases to arm-tests.txt. llvm-svn: 110880
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-0/+4
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Add testcases for all AVX 256-bit intrinsics added in the last couple daysBruno Cardoso Lopes2010-08-111-0/+751
| | | | llvm-svn: 110854
* Reapply r109881 using a more strict command line for llc.Bruno Cardoso Lopes2010-08-112-0/+2006
| | | | llvm-svn: 110833
* fix silly typoJim Grosbach2010-08-111-2/+2
| | | | llvm-svn: 110831
* Add a target triple, as the runtime library invocation varies a bit byJim Grosbach2010-08-111-3/+3
| | | | | | | | | platform. It's apparently "bl __muldf3" on linux, for example. Since that's not what we're checking here, it's more robust to just force a triple. We just wwant to check that the inline FP instructions are only generated on cpus that have them." llvm-svn: 110830
* Fix test and re-enable it.Evan Cheng2010-08-111-4/+4
| | | | llvm-svn: 110829
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | properly investigated. llvm-svn: 110825
* cortex m4 has floating point support, but only single precision.Jim Grosbach2010-08-111-0/+24
| | | | llvm-svn: 110810
* Temporarily disable some failing tests, until they can beDan Gohman2010-08-111-2/+2
| | | | | | properly investigated. llvm-svn: 110808
* Consider this code snippet:Bill Wendling2010-08-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 llvm-svn: 110799
* Report error if codegen tries to instantiate a ARM target when the cpu does ↵Evan Cheng2010-08-112-11/+1
| | | | | | support it. e.g. cortex-m* processors. llvm-svn: 110798
* Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)Evan Cheng2010-08-111-6/+6
| | | | llvm-svn: 110795
* MC/ARM: Add basic support for handling predication by parsing it out of the ↵Daniel Dunbar2010-08-111-0/+8
| | | | | | mnemonic into a separate operand form. llvm-svn: 110794
* Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bitEvan Cheng2010-08-111-5/+12
| | | | | | instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
* - Add subtarget feature -mattr=+db which determine whether an ARM cpu has theEvan Cheng2010-08-112-0/+34
| | | | | | | | | memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
* Update test to match output of optimize compares for ARM.Bill Wendling2010-08-111-4/+2
| | | | llvm-svn: 110765
* When analyzing loop exit conditions combined with and and or, don'tDan Gohman2010-08-111-2/+40
| | | | | | | make any assumptions about when the two conditions will agree on when to permit the loop to exit. This fixes PR7845. llvm-svn: 110758
* The optimize comparisons pass removes the "cmp" instruction this is checking ↵Bill Wendling2010-08-101-1/+0
| | | | | | for. llvm-svn: 110739
* Add test for recent instcombine vector shuffle enhancementNate Begeman2010-08-101-0/+29
| | | | llvm-svn: 110737
* tests: Don't error out if HOME isn't present in t the environment.Daniel Dunbar2010-08-101-1/+2
| | | | llvm-svn: 110711
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-102-7/+75
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-22/+7
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* MC/AsmParser: Fix a bug in macro argument parsing, which was droppingDaniel Dunbar2010-08-101-0/+7
| | | | | | parentheses from argument lists. llvm-svn: 110692
* Fix test for more architectures. Patch by Tobias Grosser.Jakob Stoklund Olesen2010-08-101-1/+1
| | | | llvm-svn: 110685
* RegionInfo: Do not assert if a BB is not part of the dominance tree.Tobias Grosser2010-08-101-0/+20
| | | | llvm-svn: 110665
* Fix failing testcase.Tobias Grosser2010-08-101-1/+1
| | | | | | Those look like typos to me. llvm-svn: 110664
* Handle TAG_constant for integers.Devang Patel2010-08-101-0/+25
| | | | llvm-svn: 110656
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-7/+22
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* PR7853: fix a silly mistake introduced in r101899, and add a test to make sureEli Friedman2010-08-091-12/+22
| | | | | | it doesn't regress again. llvm-svn: 110597
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-092-3/+15
| | | | llvm-svn: 110576
* XFAIL for mingw that has no plugins.Rafael Espindola2010-08-092-0/+2
| | | | llvm-svn: 110574
* Reject unrepresentable pointer types in intrinsics. Fixes PR7316.Nick Lewycky2010-08-081-0/+21
| | | | llvm-svn: 110541
* Use %shlibext instead of .soRafael Espindola2010-08-082-2/+2
| | | | llvm-svn: 110529
* Move the bugpoint test passes to a plugin in preparation for having bugpointRafael Espindola2010-08-072-2/+4
| | | | | | use opt. llvm-svn: 110520
* Use sdmem and sse_load_f64 (etc.) for the vectorDale Johannesen2010-08-071-0/+27
| | | | | | | | form of CMPSD (etc.) Matching a 128-bit memory operand is wrong, the instruction uses only 64 bits (same as ADDSD etc.) 8193553. llvm-svn: 110491
* Test case for r110459. Radar 8264751. Test case by Fariborz Jahanian!Stuart Hastings2010-08-061-0/+16
| | | | llvm-svn: 110467
* Implement a proper getModRefInfo for va_arg.Dan Gohman2010-08-061-0/+11
| | | | llvm-svn: 110458
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