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* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-2618-65/+65
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* [MC] Don't crash when trying to emit a relocation against .bss.Davide Italiano2016-07-261-0/+9
| | | | | | Turn that into an error instead. llvm-svn: 276783
* [InstSimplify] Cast folding can be made more genericDavid Majnemer2016-07-261-2/+1
| | | | | | Use isEliminableCastPair to determine if a pair of casts are foldable. llvm-svn: 276777
* GlobalISel: add correct operand type to G_FRAME_INDEX instrs.Tim Northover2016-07-261-3/+3
| | | | | | Frame indices should use "addFrameIndex", not "addImm". llvm-svn: 276775
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-0/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-265-52/+52
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* Re-committing r275284: add support to inline __builtin_mempcpyAndrew Kaylor2016-07-262-0/+6
| | | | | | | | Patch by Sunita Marathe Differential Revision: http://reviews.llvm.org/D21920 llvm-svn: 276771
* AMDGPU: Add missing tests for xnack option for HSAMatt Arsenault2016-07-261-5/+21
| | | | llvm-svn: 276765
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-262-0/+96
| | | | | | | This could use some additional optimization work to use mad/mac legacy. llvm-svn: 276764
* [ARM] Improve error messages for .arch_extension directiveOliver Stannard2016-07-261-0/+25
| | | | | | | | | | | | - More informative message when extension name is not an identifier token. - Stop parsing directive if extension is unknown (avoid duplicate error messages). - Report unsupported extensions with a source location, rather than report_fatal_error. Differential Revision: https://reviews.llvm.org/D22806 llvm-svn: 276748
* [ARM] Implement -mimplicit-it assembler optionOliver Stannard2016-07-262-0/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 llvm-svn: 276747
* [X86][SSE] Added extra memory folding tests for cvtsd2ss intrinsicSimon Pilgrim2016-07-261-0/+36
| | | | | | SSE only fold partial reg update instructions when optsize is enabled llvm-svn: 276743
* [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsicsSimon Pilgrim2016-07-262-0/+56
| | | | | | | | Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding. This was only unearthed when rL276102 started using the intrinsic again..... llvm-svn: 276740
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-263-6/+289
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis2016-07-2617-0/+142
| | | | | | | | | | | Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
* Reapply: [InstSimplify] Add support for bitcasts"David Majnemer2016-07-263-4/+29
| | | | | | | This reverts commit r276700 and reapplies r276698. The relevant clang tests have been updated. llvm-svn: 276727
* GVN-hoist: use a DFS numbering of instructions (PR28670)Sebastian Pop2016-07-261-11/+12
| | | | | | | | | | | Instead of DFS numbering basic blocks we now DFS number instructions that avoids the costly operation of which instruction comes first in a basic block. Patch mostly written by Daniel Berlin. Differential Revision: https://reviews.llvm.org/D22777 llvm-svn: 276714
* [safestack] Fix stack guard live range.Evgeniy Stepanov2016-07-261-0/+34
| | | | | | Stack guard slot is live throughout the function. llvm-svn: 276712
* [lit] Don't match tool names within new PM's <> markersAdam Nemet2016-07-251-1/+1
| | | | | | For example, stop expanding 'opt' in -passes='require<opt-remark-emit>'. llvm-svn: 276707
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-254-11/+39
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* Revert "[InstSimplify] Add support for bitcasts"David Majnemer2016-07-252-28/+3
| | | | | | | This reverts commit r276698. Clang has tests which rely on the optimizer :( llvm-svn: 276700
* [InstSimplify] Add support for bitcastsDavid Majnemer2016-07-252-3/+28
| | | | | | | BitCasts of BitCasts can be folded away as can BitCasts which don't change the type of the operand. llvm-svn: 276698
* [X86] Regenerate v2i256 shift legalization testsSimon Pilgrim2016-07-251-26/+116
| | | | llvm-svn: 276692
* [X86] Regenerate i64 shift legalization testsSimon Pilgrim2016-07-251-38/+160
| | | | llvm-svn: 276691
* GlobalISel: add generic casts to IRTranslatorTim Northover2016-07-251-9/+51
| | | | | | | | | This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
* GlobalISel[AArch64]: support pointer types in argument lowering.Tim Northover2016-07-251-0/+52
| | | | | | | | They're basically i64 for AArch64, but we'll leave them intact for stranger targets. Also add some tests for the (very few) other cases we can handle right now. llvm-svn: 276689
* [PM] Port SymbolRewriter to the new PMMichael Kuperstein2016-07-251-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D22703 llvm-svn: 276687
* Next step along the way to getting good error messages for bad archives.Kevin Enderby2016-07-253-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | I consulted with Lang Hames on this work, and the goal was to add a bit of "where" in the archive the error occurred along with what the error was. So this step changes ArchiveMemberHeader into a class with a pointer to the archive header and the parent archive. Which allows the methods in the ArchiveMemberHeader to determine which member the header is for to include that information in the error message. For this first step the "where" is just the offset to the member in the archive. The next step will be a new method on ArchiveMemberHeader to get the full name, if possible, to be use in the error message. Which will now be possible as ArchiveMemberHeader contains a pointer to the Archive with its string table and its size, etc. so the full name can be determined from the header if it is valid. Also this change adds the missing checks the archive header is actually contained in the buffer and is not truncated, as well as if the terminating characters are correct in the header. And changes one error message in Archive::Child::getNext() where the name or offset to member is now added. llvm-svn: 276686
* AMDGPU: Remove read_workdim intrinsicJan Vesely2016-07-254-115/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22732 llvm-svn: 276682
* Scalarizer: Support scalarizing intrinsicsMatt Arsenault2016-07-251-0/+85
| | | | llvm-svn: 276681
* AMDGPU: Fix missing verify-machineinstrs in control flow testMatt Arsenault2016-07-251-1/+1
| | | | llvm-svn: 276679
* Fix invalid iterator use in safestack coloring.Evgeniy Stepanov2016-07-251-0/+84
| | | | llvm-svn: 276676
* [PGO] Fix profile mismatch in COMDAT function with pre-inlinerRong Xu2016-07-254-11/+70
| | | | | | | | | | | | | | | | | | Pre-instrumentation inline (pre-inliner) greatly improves the IR instrumentation code performance, among other benefits. One issue of the pre-inliner is it can introduce CFG-mismatch for COMDAT functions. This is due to the fact that the same COMDAT function may have different early inline decisions across different modules -- that means different copies of COMDAT functions will have different CFG checksum. In this patch, we propose a partially renaming the COMDAT group and its member function/variable so we have different profile counter for each version. We will post-fix the COMDAT function and the group name with its FunctionHash. Differential Revision: http://reviews.llvm.org/D22600 llvm-svn: 276673
* [X86][SSE] Added 2048-bit vector comparison testsSimon Pilgrim2016-07-251-0/+1757
| | | | | | Upper limit of what can be held in a <32 x i8> result llvm-svn: 276666
* AVX-512: Fixed [US]INT_TO_FP selection for i1 vectors.Elena Demikhovsky2016-07-251-0/+347
| | | | | | | | It failed with assertion before this patch. Differential Revision: https://reviews.llvm.org/D22735 llvm-svn: 276648
* Remove useless pass from the pipeline in ↵Wei Mi2016-07-251-2/+2
| | | | | | test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll. llvm-svn: 276644
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-0/+73
| | | | llvm-svn: 276638
* [ARM] Improve longMAC codegen testSam Parker2016-07-251-34/+85
| | | | | | | | Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
* [mips] Optimize materialization of i64 constantsSimon Dardis2016-07-259-80/+85
| | | | | | | | | | | | | | | | | Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit integer. This allows us to generate the same instructions for the materialization of the same constants regardless the width of their type. Patch by: Vasileios Kalintiris Contributions by: Simon Dardis Reviewers: Daniel Sanders Differential Review: https://reviews.llvm.org/D21689 llvm-svn: 276628
* [ARM] Enable ISel of SMMLS for ARM and Thumb2Sam Parker2016-07-251-2/+34
| | | | | | | | Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
* [AVX512] Add load folding support for the unmasked forms of the FMA ↵Craig Topper2016-07-252-8/+4
| | | | | | instructions. llvm-svn: 276615
* [AVX512] Add some additional patterns so that we can fold broadcast loads in ↵Craig Topper2016-07-251-4/+2
| | | | | | the first argument of an FMADD/FMSUB/FNMADD/FNMSUB/FMADDSUB/FMSUBADD node. Also add patterns to support all combinations of the broadcast input and the preserved input for masked versions. llvm-svn: 276614
* [AVX512] Cleanup FMA operand order in patterns to match the VEX versions and ↵Craig Topper2016-07-253-243/+266
| | | | | | to really be 213, 231, and 132. llvm-svn: 276613
* Fix : Partial Inliner requires AssumptionCacheTrackerSean Silva2016-07-251-0/+20
| | | | | | | | | | | The public InlineFunction utility assumes that the passed in InlineFunctionInfo has a valid AssumptionCacheTracker. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22706 llvm-svn: 276609
* [GVNHoist] Merge metadata on hoisted instructions less conservativelyDavid Majnemer2016-07-251-0/+25
| | | | | | | We can combine metadata from multiple instructions intelligently for certain metadata nodes. llvm-svn: 276602
* [GVNHoist] Properly merge alignments when hoistingDavid Majnemer2016-07-251-0/+21
| | | | | | | | | If we two loads of two different alignments, we must use the minimum of the two alignments when hoisting. Same deal for stores. For allocas, use the maximum of the two allocas. llvm-svn: 276601
* [X86][SSE] Added PR27854 tests Simon Pilgrim2016-07-241-0/+48
| | | | llvm-svn: 276571
* [X86] Add shift double tests for PR14593Simon Pilgrim2016-07-241-0/+74
| | | | llvm-svn: 276570
* [X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'Simon Pilgrim2016-07-241-0/+2
| | | | | | As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing. llvm-svn: 276569
* [X86] Add SHRD shift combine testsSimon Pilgrim2016-07-241-0/+36
| | | | llvm-svn: 276568
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