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* This reverts commit r239529 and r239514.Rafael Espindola2015-06-111-197/+0
| | | | | | | | | Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions." Revert "Fixing MSVC 2013 build error." The test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X. llvm-svn: 239544
* Revert "Fix merges of non-zero vector stores"Reid Kleckner2015-06-112-11/+2
| | | | | | | | This reverts commit r239539. It was causing SDAG assertions while building freetype. llvm-svn: 239543
* SLSR: Pass address space to isLegalAddressingModeMatt Arsenault2015-06-112-0/+109
| | | | | | | | | This only updates one of the uses. The other is used in cases that may never touch memory, so I'm not sure why this is even calling it. Perhaps there should be a new, similar hook for such cases or pass -1 for unknown address space. llvm-svn: 239540
* Fix merges of non-zero vector storesMatt Arsenault2015-06-112-2/+11
| | | | | | | | | | Now actually stores the non-zero constant instead of 0. I somehow forgot to include this part of r238108. The test change was just an independent instruction order swap, so just add another check line to satisfy CHECK-NEXT. llvm-svn: 239539
* R600/SI: Add -mcpu=bonaire to a test that uses flat address spaceTom Stellard2015-06-111-1/+1
| | | | | | | Flat instructions don't exist on SI, but there is a bug in the backend that allows them to be selected. llvm-svn: 239533
* Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate ↵Toma Tabacu2015-06-114-0/+158
| | | | | | | | | operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
* [mips][microMIPS] Implement ERET and ERETNC instructionsZoran Jovanovic2015-06-112-10/+11
| | | | | | http://reviews.llvm.org/D10091 llvm-svn: 239522
* [mips] Change existing uimm10 operand to restrict the accepted immediatesZoran Jovanovic2015-06-113-0/+13
| | | | | | http://reviews.llvm.org/D10312 llvm-svn: 239520
* [mips][microMIPSr6] Change disassembler tests to one line formatZoran Jovanovic2015-06-112-672/+336
| | | | llvm-svn: 239519
* [AArch64] Match interleaved memory accesses into ldN/stN instructions.Hao Liu2015-06-111-0/+197
| | | | | | | | | | | | | | | | | | | | | | | Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true" E.g. Transform an interleaved load (Factor = 2): %wide.vec = load <8 x i32>, <8 x i32>* %ptr %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements Into: %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr) %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0 %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1 E.g. Transform an interleaved store (Factor = 2): %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7> ; Interleaved vec store <8 x i32> %i.vec, <8 x i32>* %ptr Into: %v0 = shuffle %i.vec, undef, <0, 1, 2, 3> %v1 = shuffle %i.vec, undef, <4, 5, 6, 7> call void aarch64.neon.st2(%v0, %v1, %ptr) llvm-svn: 239514
* [X86][SSE] Vectorized i8 and i16 shift operatorsSimon Pilgrim2015-06-116-1343/+532
| | | | | | | | | | | | | | | | This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements: 1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node. 2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper). 3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial. The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however. Tested on SSE2, SSE41 and AVX machines. Differential Revision: http://reviews.llvm.org/D9474 llvm-svn: 239509
* LLVM support for vector quad bit permute and gather instructions through ↵Nemanja Ivanovic2015-06-113-0/+103
| | | | | | | | | | | | | | builtins This patch corresponds to review: http://reviews.llvm.org/D10096 This is the back end portion of the patch related to D10095. The patch adds the instructions and back end intrinsics for: vbpermq vgbbd llvm-svn: 239505
* Revert "Move dllimport name mangling to IR mangler."Reid Kleckner2015-06-111-17/+0
| | | | | | | | | This reverts commit r239437. This broke clang-cl self-hosts. We'd end up calling the __imp_ symbol directly instead of using it to do an indirect function call. llvm-svn: 239502
* ArgumentPromotion: Drop sret attribute on functions that are only called ↵Peter Collingbourne2015-06-101-0/+28
| | | | | | | | | | | | | | | | | | | directly. If the first argument to a function is a 'this' argument and the second has the sret attribute, the ArgumentPromotion pass may promote the 'this' argument to more than one argument, violating the IR constraint that 'sret' may only be applied to the first or second argument. Although this IR constraint is arguably unnecessary, it highlighted the fact that ArgPromotion does not need to preserve this attribute. Dropping the attribute reduces register pressure in the backend by avoiding the register copy required by sret. Because sret implies noalias, we also replace the former with the latter. Differential Revision: http://reviews.llvm.org/D10353 llvm-svn: 239488
* [x86] Add a reassociation optimization to increase ILP via the ↵Sanjay Patel2015-06-101-0/+78
| | | | | | | | | | | | | | | | | | MachineCombiner pass This is a reimplementation of D9780 at the machine instruction level rather than the DAG. Use the MachineCombiner pass to reassociate scalar single-precision AVX additions (just a starting point; see the TODO comments) to increase ILP when it's safe to do so. The code is closely based on the existing MachineCombiner optimization that is implemented for AArch64. This patch should not cause the kind of spilling tragedy that led to the reversion of r236031. Differential Revision: http://reviews.llvm.org/D10321 llvm-svn: 239486
* [WinEH] _except_handlerN uses 0 instead of 1 to indicate catch-allReid Kleckner2015-06-102-3/+3
| | | | | | Our usage of 1 was a holdover from __C_specific_handler. llvm-svn: 239482
* [GVN] Set proper debug locations for some instructions created by GVN.Alexey Samsonov2015-06-101-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Determining proper debug locations for instructions created in PHITransAddr is tricky. We use a simple approach here and simply copy debug locations from instructions computing load address to "corresponding" instructions re-creating the address computation in predecessor basic blocks. This may not always be correct, given all the rearrangement and simplification going on, and debug locations may jump around a lot, as the basic blocks we copy locations between may be very far from each other. Still, this would work good in most simple cases (e.g. when chain of address computing instruction is short, or our mapping turns out to be 1-to-1), and we desire to have *some* reasonable debug locations associated with newly inserted instructions. See http://reviews.llvm.org/D10351 review thread for more details. Test Plan: regression test suite Reviewers: spatel, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10351 llvm-svn: 239479
* [Hexagon] Adding decoders for signed operands and ensuring all signed ↵Colin LeMahieu2015-06-102-1/+100
| | | | | | operand types disassemble correctly. llvm-svn: 239477
* [Statepoints] Add test case to check that statepoint is marked with ↵Igor Laevsky2015-06-101-0/+24
| | | | | | | | Throwable attribute. Differential Revision: http://reviews.llvm.org/D10215 llvm-svn: 239473
* [StatepointLowering] Reuse stack slots across basic blocksIgor Laevsky2015-06-101-1/+45
| | | | | | | | | | | During statepoint lowering we can sometimes avoid spilling of the value if we know that it was already spilled for previous statepoint. We were doing this by checking if incoming statepoint value was lowered into load from stack slot. This was working only in boundaries of one basic block. But instead of looking at the lowered node we can look directly at the llvm-ir value and if it was gc.relocate (or some simple modification of it) look up stack slot for it's derived pointer and reuse stack slot from it. This allows us to look across basic block boundaries. Differential Revision: http://reviews.llvm.org/D10251 llvm-svn: 239472
* AVX-512: Fixed a bug in comparison of i1 vectors.Elena Demikhovsky2015-06-101-2/+2
| | | | | | | | | cmp eq should give kxnor instruction cmp neq should give kxor https://llvm.org/bugs/show_bug.cgi?id=23631 llvm-svn: 239460
* [WinEH] Call llvm.stackrestore in __except blocksReid Kleckner2015-06-101-0/+4
| | | | | | | We have to do this manually, the runtime only sets up ebp. Fixes a crash when returning after catching an exception. llvm-svn: 239451
* [WinEH] Emit .safeseh directives for all 32-bit exception handlersReid Kleckner2015-06-102-0/+6
| | | | | | | | | | Use a "safeseh" string attribute to do this. You would think we chould just accumulate the set of personalities like we do on dwarf, but this fails to account for the LSDA-loading thunks we use for __CxxFrameHandler3. Each of those needs to make it into .sxdata as well. The string attribute seemed like the most straightforward approach. llvm-svn: 239448
* Add explicit -mtriple=arm-unknown to ↵NAKAMURA Takumi2015-06-091-3/+3
| | | | | | llvm/test/CodeGen/ARM/disable-tail-calls.ll, to satisfy *-win32. llvm-svn: 239442
* [BasicBlockUtils] Set debug locations for instructions created in ↵Alexey Samsonov2015-06-091-0/+90
| | | | | | | | | | | | | | SplitBlockPredecessors. Test Plan: regression test suite Reviewers: eugenis, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10343 llvm-svn: 239438
* Move dllimport name mangling to IR mangler.Peter Collingbourne2015-06-091-0/+17
| | | | | | | | This ensures that LTO clients see the correct external symbol name. Differential Revision: http://reviews.llvm.org/D10318 llvm-svn: 239437
* [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpacesJingyue Wu2015-06-091-0/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: We used to assume V->RAUW only modifies the operand list of V's user. However, if V and V's user are Constants, RAUW may replace and invalidate V's user entirely. This patch fixes the above issue by letting the caller replace the operand instead of calling RAUW on Constants. Test Plan: @nested_const_expr and @rauw in access-non-generic.ll Reviewers: broune, jholewinski Reviewed By: broune, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10345 llvm-svn: 239435
* LibDriver, llvm-lib: introduce.Peter Collingbourne2015-06-093-0/+11
| | | | | | | | | | llvm-lib is intended to be a lib.exe compatible utility that also understands bitcode. The implementation lives in a library so that lld can use it to implement /lib. Differential Revision: http://reviews.llvm.org/D10297 llvm-svn: 239434
* [WinEH] Add 32-bit SEH state table emission prototypeReid Kleckner2015-06-093-14/+225
| | | | | | | | | | | | This gets all the handler info through to the asm printer and we can look at the .xdata tables now. I've convinced one small catch-all test case to work, but other than that, it would be a stretch to say this is functional. The state numbering algorithm avoids doing any scope reconstruction as we do for C++ to simplify the implementation. llvm-svn: 239433
* [AArch64] Remove an overly conservative check when generating store pairs.Chad Rosier2015-06-091-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Store instructions do not modify register values and therefore it's safe to form a store pair even if the source register has been read in between the two store instructions. Previously, the read of w1 (see below) prevented the formation of a stp. str w0, [x2] ldr w8, [x2, #8] add w0, w8, w1 str w1, [x2, #4] ret We now generate the following code. stp w0, w1, [x2] ldr w8, [x2, #8] add w0, w8, w1 ret All correctness tests with -Ofast on A57 with Spec200x and EEMBC pass. Performance results for SPEC2K were within noise. llvm-svn: 239432
* Remove DisableTailCalls from TargetOptions and the code in resetTargetOptionsAkira Hatanaka2015-06-092-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | that was resetting it. Remove the uses of DisableTailCalls in subclasses of TargetLowering and use the value of function attribute "disable-tail-calls" instead. Also, unconditionally add pass TailCallElim to the pipeline and check the function attribute at the start of runOnFunction to disable the pass on a per-function basis. This is part of the work to remove TargetMachine::resetTargetOptions, and since DisableTailCalls was the last non-fast-math option that was being reset in that function, we should be able to remove the function entirely after the work to propagate IR-level fast-math flags to DAG nodes is completed. Out-of-tree users should remove the uses of DisableTailCalls and make changes to attach attribute "disable-tail-calls"="true" or "false" to the functions in the IR. rdar://problem/13752163 Differential Revision: http://reviews.llvm.org/D10099 llvm-svn: 239427
* MergeFunctions: Don't replace a weak function use by another equivalent weak ↵Arnold Schwaighofer2015-06-091-9/+39
| | | | | | | | | | function We don't know whether the weak functions definition is the definitive definition. rdar://21303727 llvm-svn: 239422
* Revert "[DWARF] Fix a few corner cases in expression emission"David Blaikie2015-06-091-110/+0
| | | | | | | This reverts commit r239380 due to apparently GDB regressions: http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/22562 llvm-svn: 239420
* The constant initialization for globals in NVPTX is generated as an Samuel Antao2015-06-091-0/+23
| | | | | | | | | | array of bytes. The generation of this byte arrays was expecting the host to be little endian, which prevents big endian hosts to be used in the generation of the PTX code. This patch fixes the problem by changing the way the bytes are extracted so that it works for either little and big endian. llvm-svn: 239412
* Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-092-0/+26
| | | | | | | Specified the llvm namespace for the 2 calls to make_unique() which caused compilation errors in Visual Studio 2013. llvm-svn: 239405
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+38
| | | | | | Added encoding tests. llvm-svn: 239403
* Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." ↵Toma Tabacu2015-06-094-158/+0
| | | | | | | | (r239396). It was breaking buildbots. llvm-svn: 239397
* [mips] [IAS] Add support for BNE and BEQ with an immediate operand.Toma Tabacu2015-06-094-0/+158
| | | | | | | | | | | | | | | | Summary: For some branches, GAS accepts an immediate instead of the 2nd register operand. We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9666 llvm-svn: 239396
* llvm/test/DebugInfo/X86/expressions.ll: %llc_dwarf shouldn't be used with ↵NAKAMURA Takumi2015-06-091-2/+2
| | | | | | | | -mtriple, since %llc_dwarf implies the triple. In this case, use plain "llc". llvm-svn: 239390
* Move X86-only test case to appropriate directoryKeno Fischer2015-06-091-0/+0
| | | | llvm-svn: 239384
* [DWARF] Fix a few corner cases in expression emissionKeno Fischer2015-06-091-0/+110
| | | | | | | | | | | | | | | | | | | Summary: I noticed an object file with `DW_OP_reg4 DW_OP_breg4 0` as a DWARF expression, which I traced to a missing break (and `++I`) in this code snippet. While I was at it, I also added support for a few other corner cases along the same lines that I could think of. Test Plan: Hand-crafted test case to exercises these cases is included. Reviewers: echristo, dblaikie, aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10302 llvm-svn: 239380
* [asan] Prevent __attribute__((annotate)) triggering errors on DarwinAnna Zaks2015-06-091-0/+12
| | | | | | | | | | | | | | | | | The following code triggers a fatal error in the compiler instrumentation of ASan on Darwin because we place the attribute into llvm.metadata section, which does not have the proper MachO section name. void foo() __attribute__((annotate("custom"))); void foo() {;} This commit reorders the checks so that we skip everything in llvm.metadata first. It also removes the hard failure in case the section name does not parse. That check will be done lower in the compilation pipeline anyway. (Reviewed in http://reviews.llvm.org/D9093.) llvm-svn: 239379
* Implement computeKnownBits for min/max nodesMatt Arsenault2015-06-093-4/+103
| | | | llvm-svn: 239378
* [NVPTX] run SROA after NVPTXFavorNonGenericAddrSpacesJingyue Wu2015-06-091-2/+3
| | | | | | | | | | | | | | | | | | Summary: This cleans up most allocas NVPTXLowerKernelArgs emits for byval parameters. Test Plan: makes bug21465.ll more stronger to verify no redundant local load/store. Reviewers: eliben, jholewinski Reviewed By: eliben, jholewinski Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10322 llvm-svn: 239368
* MergeFunctions: Impose a total order on the replacement of functionsArnold Schwaighofer2015-06-092-4/+34
| | | | | | | | | | | | | We don't want to replace function A by Function B in one module and Function B by Function A in another module. If these functions are marked with linkonce_odr we would end up with a function stub calling B in one module and a function stub calling A in another module. If the linker decides to pick these two we will have two stubs calling each other. rdar://21265586 llvm-svn: 239367
* [AArch64] AsmParser should be case insensitive about accepting vector ↵Ranjeet Singh2015-06-081-0/+8
| | | | | | | | register names. Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
* Fix a regression in .pop_section.Rafael Espindola2015-06-081-0/+21
| | | | | | | It was calling ChangeSection with the wrong current section, eventually leading to a crash. llvm-svn: 239335
* [X86][SSE] Added lzcnt vector tests.Simon Pilgrim2015-06-082-0/+3010
| | | | llvm-svn: 239333
* [ARM] Pass a callback to FunctionPass constructors to enable skipping executionAkira Hatanaka2015-06-081-0/+22
| | | | | | | | | | | | | | | | on a per-function basis. Previously some of the passes were conditionally added to ARM's pass pipeline based on the target machine's subtarget. This patch makes changes to add those passes unconditionally and execute them conditonally based on the predicate functor passed to the pass constructors. This enables running different sets of passes for different functions in the module. rdar://problem/20542263 Differential Revision: http://reviews.llvm.org/D8717 llvm-svn: 239325
* X86: Reject register operands with obvious type mismatches.Matthias Braun2015-06-081-0/+10
| | | | | | | | | | | | | While we have some code to transform specification like {ax} into {eax}/{rax} if the operand type isn't 16bit, we should reject cases where there is no sane way to do this, like the i128 type in the example. Related to rdar://21042280 Differential Revision: http://reviews.llvm.org/D10260 llvm-svn: 239309
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