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* Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"Daniel Jasper2017-02-071-6/+7
| | | | | | | | | | | | | This reverts commit r294186. On an internal test, this triggers an out-of-memory error on PPC, presumably because there is another dagcombine that does the exact opposite triggering and endless loop consuming more and more memory. Chandler has started at creating a reduced test case and we'll attach it as soon as possible. llvm-svn: 294288
* [AVX-512] Add masked and unmasked shift by immediate instructions to load ↵Craig Topper2017-02-071-0/+102
| | | | | | folding tables. llvm-svn: 294287
* [AVX-512] Add masked shift instructions to load folding tables.Craig Topper2017-02-071-0/+42
| | | | | | This adds the masked versions of everything, but the shift by immediate instructions. llvm-svn: 294286
* [AVX-512] Add some of the shift instructions to the load folding tables.Craig Topper2017-02-072-0/+486
| | | | | | | | This includes unmasked forms of variable shift and shifting by the lower element of a register. Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms. llvm-svn: 294285
* [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including ↵Craig Topper2017-02-071-14/+28
| | | | | | YMM16-31. llvm-svn: 294277
* [AVX-512] Put the integer stack folding tests in alphabetical order.Craig Topper2017-02-072-1253/+1237
| | | | llvm-svn: 294276
* RegisterCoalescer: Fix joinReservedPhysReg()Matthias Braun2017-02-071-20/+75
| | | | | | | | | | | joinReservedPhysReg() can only deal with a liverange in a single basic block when copying from a vreg into a physreg. See also rdar://30306405 Differential Revision: https://reviews.llvm.org/D29436 llvm-svn: 294268
* [AMDGPU] Lower null pointers in static variable initializerYaxun Liu2017-02-071-0/+113
| | | | | | | | | | | | For amdgcn target Clang generates addrspacecast to represent null pointers in private and local address spaces. In LLVM codegen, the static variable initializer is lowered by virtual function AsmPrinter::lowerConstant which is target generic. Since addrspacecast is target specific, AsmPrinter::lowerConst This patch overrides AsmPrinter::lowerConstant with AMDGPUAsmPrinter::lowerConstant, which is able to lower the target-specific addrspacecast in the null pointer representation so that -1 is co Differential Revision: https://reviews.llvm.org/D29284 llvm-svn: 294265
* [x86] add tests to show current codegen for vblendv*; NFCSanjay Patel2017-02-071-0/+319
| | | | | | | As noted in the comments, we should be able to eliminate cmp ops in several cases. llvm-svn: 294263
* GlobalISel: legalize narrow G_SELECTS on AArch64.Tim Northover2017-02-061-5/+15
| | | | | | Otherwise there aren't any patterns to select them. llvm-svn: 294261
* Fix the samplepgo indirect call promotion bug: we should not promote a ↵Dehao Chen2017-02-062-0/+18
| | | | | | | | | | | | | | | | direct call. Summary: Checking CS.getCalledFunction() == nullptr does not necessary indicate indirect call. We also need to check if CS.getCalledValue() is not a constant. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29570 llvm-svn: 294260
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-0616-39/+678
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [X86][SSE] Tests showing the lowering of float/double complex ↵Simon Pilgrim2017-02-061-0/+215
| | | | | | multiplications with fastmath (PR31866) llvm-svn: 294254
* Merge DebugLoc on combined stores; in this case, when combining storesPaul Robinson2017-02-062-2/+74
| | | | | | | | from the end of two blocks, merge instead of arbitrarily picking one. Differential Revision: http://reviews.llvm.org/D29504 llvm-svn: 294251
* [GVNHoist] Merge DebugLoc metadata on hoisted instructionsTaewook Oh2017-02-061-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When instructions are hoisted, current implementation keeps DebugLoc metadata of the instruction that chosen as Repl (and its GEP operand if Repl is a load or a store). However, DebugLoc metadata should be updated to the 'merged' location across all hoisted instructions. See the following example code: ``` 1: typedef struct { 2: int a[10]; 3: } S1; 4: 5: extern S1 *s1[10]; 6: 7: void foo(int x, int y, int i) { 8: if (y) 9: s1[i]->a[i] = x + y; 10: else 11: s1[i]->a[i] = x; 12: } ``` Below is LLVM IR representation of the program before gvn-hoist: ``` %struct.S1 = type { [10 x i32] } @s1 = external local_unnamed_addr global [10 x %struct.S1*], align 16 define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 br i1 %tobool, label %if.then, label %if.else, !dbg !10 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !11 %idxprom = sext i32 %i to i64, !dbg !12 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !12 %0 = load %struct.S1*, %struct.S1** %arrayidx, align 8, !dbg !12, !tbaa !13 %a = getelementptr inbounds %struct.S1, %struct.S1* %0, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !12 if.else: ; preds = %entry %idxprom3 = sext i32 %i to i64, !dbg !18 %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom3, !dbg !18 %1 = load %struct.S1*, %struct.S1** %arrayidx4, align 8, !dbg !18, !tbaa !13 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %idxprom6 = sext i32 %i to i64 %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom6 store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` where ``` !11 = !DILocation(line: 9, column: 18, scope: !9) !12 = !DILocation(line: 9, column: 5, scope: !9) !18 = !DILocation(line: 11, column: 5, scope: !9) !19 = !DILocation(line: 11, column: 9, scope: !9) ``` . And below is after gvn-hoist: ``` define void @foo(i32 %x, i32 %y, i32 %i) !dbg !4 { entry: %tobool = icmp ne i32 %y, 0, !dbg !8 %idxprom = sext i32 %i to i64, !dbg !10 %0 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %1 = load %struct.S1*, %struct.S1** %0, align 8, !dbg !10, !tbaa !11 br i1 %tobool, label %if.then, label %if.else, !dbg !15 if.then: ; preds = %entry %add = add nsw i32 %x, %y, !dbg !16 %arrayidx = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !10 %a = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !17 br label %if.end, !dbg !10 if.else: ; preds = %entry %arrayidx4 = getelementptr inbounds [10 x %struct.S1*], [10 x %struct.S1*]* @s1, i64 0, i64 %idxprom, !dbg !18 %a5 = getelementptr inbounds %struct.S1, %struct.S1* %1, i32 0, i32 0, !dbg !19 br label %if.end if.end: ; preds = %if.else, %if.then %a5.sink = phi [10 x i32]* [ %a5, %if.else ], [ %a, %if.then ] %.sink = phi i32 [ %x, %if.else ], [ %add, %if.then ] %arrayidx7 = getelementptr inbounds [10 x i32], [10 x i32]* %a5.sink, i64 0, i64 %idxprom store i32 %.sink, i32* %arrayidx7, align 4, !tbaa !20 ret void, !dbg !22 } ``` As you see, loads and their GEPs have been hosited from if.then/if.else block to entry block. However, DebugLoc metadata of these new instructions are still same as the instructions in if.then block, as they are moved/cloned from if.then block. This may result incorrect stepping and imprecise sample profile result. Reviewers: majnemer, pcc, sebpop Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29377 llvm-svn: 294250
* GlobalISel: fall back gracefully when we can't map an operand's size.Tim Northover2017-02-061-0/+8
| | | | | | | | AArch64 was asserting when it was asked to provide a register-bank of a size it couldn't deal with (in this case an s128 IMPLICIT_DEF). But we want a robust fallback path so this isn't allowed. llvm-svn: 294248
* GlobalISel: legalize G_INSERT instructionsTim Northover2017-02-062-2/+102
| | | | | | | We don't handle all cases yet (see arm64-fallback.ll for an example), but this is enough to cover most common C++ code so it's a good place to start. llvm-svn: 294247
* [SLP] Revert "Allow using of extra values in horizontal reductions."Michael Kuperstein2017-02-061-114/+134
| | | | | | | | This breaks when one of the extra values is also a scalar that participates in the same vectorization tree which we'll end up reducing. llvm-svn: 294245
* IR: Consider two DISubprograms to be odr-equal if they have the same ↵Peter Collingbourne2017-02-061-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | template parameters. In ValueMapper we create new operands for MDNodes and rely on MDNode::replaceWithUniqued to create a new MDNode with the specified operands. However this doesn't always actually happen correctly for DISubprograms because when we uniquify the new node, we only odr-compare it with existing nodes (MDNodeSubsetEqualImpl<DISubprogram>::isDeclarationOfODRMember). Although the TemplateParameters field can refer to a distinct DICompileUnit via DITemplateTypeParameter::type -> DICompositeType::scope -> DISubprogram::unit, it is not currently included in the odr comparison. As a result, we can end up getting our original DISubprogram back, which means we will have a cloned module referring to the DICompileUnit in the original module, which causes a verification error. The fix I implemented was to consider TemplateParameters to be one of the odr-equal properties. But I'm a little uncomfortable with this. In general it seems unsound to rely on distinct MDNodes never being reachable from nodes which we only check odr-equality of. My only long term suggestion would be to separate odr-uniquing from full uniquing. Differential Revision: https://reviews.llvm.org/D29240 llvm-svn: 294240
* Fix a bug in llvm-obdump(1) with the -macho and -info-plist optionsKevin Enderby2017-02-061-0/+10
| | | | | | | | | which caused it to print more than the (__TEXT,__info_plist) if that section did not end with a null. rdar://27378808 llvm-svn: 294236
* Get function start line number from DWARF infoDavid Blaikie2017-02-061-0/+3
| | | | | | | | | | | | | | | DWARF info contains info about the line number at which a function starts (DW_AT_decl_line). This patch creates a function to look up the start line number for a function, and returns it in DILineInfo when looking up debug info for a particular address. Patch by Simon Que! Reviewed By: dblaikie Differential Revision: https://reviews.llvm.org/D27962 llvm-svn: 294231
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-0613-10/+164
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [X86][SSE] Add tests showing missed opportunities to simplify integer ↵Simon Pilgrim2017-02-061-0/+79
| | | | | | absolute instructions llvm-svn: 294216
* Fix a bug in llvm-obdump(1) with the -macho and -disassemble optionsKevin Enderby2017-02-062-0/+8
| | | | | | | | | | which caused it to not disassemble the bytes a the start of the section if the section had symbols and the first symbol was not at the start of the section. rdar://30143243 llvm-svn: 294212
* [ValueTracking] emit a remark when we detect a conflicting assumption (PR31809)Sanjay Patel2017-02-061-5/+28
| | | | | | | | | | | | This is a follow-up to D29395 where we try to be good citizens and let the user know that we've probably gone off the rails. This should allow us to resolve: https://llvm.org/bugs/show_bug.cgi?id=31809 Differential Revision: https://reviews.llvm.org/D29404 llvm-svn: 294208
* Fix the bug of samplepgo indirect call promption when type casting of the ↵Dehao Chen2017-02-061-7/+9
| | | | | | | | | | | | | | | | return value is needed. Summary: When type casting of the return value is needed, promoteIndirectCall will return the type casting instruction instead of the direct call. This patch changed to return the direct call instruction instead. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29569 llvm-svn: 294205
* [AArch64] Fix incorrect MachinePointerInfo in splitStoreSplatJohn Brawn2017-02-062-0/+131
| | | | | | | | | | | When splitting up one store into several in splitStoreSplat we have to make sure we get the MachinePointerInfo right, otherwise alias analysis thinks they all store to the same location. This can then cause invalid scheduling later on. Differential Revision: https://reviews.llvm.org/D29446 llvm-svn: 294203
* [DAGCombiner] Support bswap as a part of load combine patternsArtur Pilipenko2017-02-065-0/+145
| | | | | | | | Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D29397 llvm-svn: 294201
* Commit full codegen for mul-i256.ll . NFCAmaury Sechet2017-02-061-19/+277
| | | | | | The full codegen is committed for larger multiply, so that won't make the test suite more fragile. However, it'll allow to expose the effects fo various DAG combine. llvm-svn: 294196
* RuntimeDyldELF/AArch64: Implement basic GOT supportEugene Leviant2017-02-061-0/+46
| | | | | | | | | This patch implements two GOT relocations: R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC Differential revision: https://reviews.llvm.org/D28571 llvm-svn: 294191
* Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.Amaury Sechet2017-02-061-4/+2
| | | | | | | | | | | | Summary: As per title. Reviewers: bkramer, sunfish, lattner, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29521 llvm-svn: 294188
* [DAGCombiner] Make DAGCombiner smarter about overflowAmaury Sechet2017-02-061-2/+1
| | | | | | | | | | | | Summary: Leverage it to transform addc into add. Reviewers: mkuper, spatel, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29524 llvm-svn: 294187
* [DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)Amaury Sechet2017-02-061-7/+6
| | | | | | | | | | | | Summary: This is extracted from D29443 . Reviewers: mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29564 llvm-svn: 294186
* Add DAGCombiner load combine tests with non-zero offsetArtur Pilipenko2017-02-065-3/+805
| | | | | | This is separated from https://reviews.llvm.org/D29394 review. llvm-svn: 294185
* [X86] Add add/addc known-bits tests (D29521)Simon Pilgrim2017-02-061-0/+66
| | | | llvm-svn: 294184
* [X86][SSE] Combine shuffle nodes with multiple uses if all the users are ↵Simon Pilgrim2017-02-064-43/+8
| | | | | | | | | | | | | | being combined. Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines. We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree. This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list. Differential Revision: https://reviews.llvm.org/D29399 llvm-svn: 294183
* [mips] dla expansion without the at registerSimon Dardis2017-02-061-0/+48
| | | | | | | | | | | | | | | | | Previously only the superscalar scheduled expansion of the dla macro for MIPS64 was implemented. If assembler temporary register is not available and the optional source register is not the destination register, synthesize the address using the naive solution of adds and shifts. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: slthakur, seanbruno Differential Revision: https://reviews.llvm.org/D29328 llvm-svn: 294182
* [ArgPromote] Replace all the grep-based testing with precise FileCheckChandler Carruth2017-02-065-63/+117
| | | | | | | | | | tests. This also removes the use of instcombine as we can max the patterns produced by argument promotion directly with the more powerful tools in FileCheck. llvm-svn: 294174
* [X86][GlobalISel] Add limited ret lowering support to the IRTranslator.Igor Breger2017-02-062-38/+181
| | | | | | | | | | | | | | | | Summary: Support return lowering for i8/i16/i32/i64/float/double, vector type supported for 64bit platform only. Support argument lowering for float/double types. Reviewers: t.p.northover, zvi, ab, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, delena, llvm-commits Differential Revision: https://reviews.llvm.org/D29261 llvm-svn: 294173
* [AVX-512] Add VPSLLDQ/VPSRLDQ to load folding tables.Craig Topper2017-02-062-0/+48
| | | | llvm-svn: 294170
* [AVX-512] Add VPABSB/D/Q/W to load folding tables.Craig Topper2017-02-062-0/+172
| | | | llvm-svn: 294169
* [AVX-512] Add VSHUFPS/PD to load folding tables.Craig Topper2017-02-061-0/+39
| | | | llvm-svn: 294168
* [AVX-512] Add all masked and unmasked versions of VPMULDQ and VPMULUDQ to ↵Craig Topper2017-02-051-0/+59
| | | | | | load folding tables. llvm-svn: 294163
* [X86][SSE] Replace insert_vector_elt(vec, -1, idx) with shuffleSimon Pilgrim2017-02-051-22/+12
| | | | | | Similar to what we already do for zero elt insertion, we can quickly rematerialize 'allbits' vectors so to avoid a unnecessary gpr value and insertion into a vector llvm-svn: 294162
* [AVX-512] Add scalar masked max/min intrinsic instructions to the load ↵Craig Topper2017-02-051-0/+62
| | | | | | folding tables. llvm-svn: 294153
* [AVX-512] Add scalar masked add/sub/mul/div intrinsic instructions to the ↵Craig Topper2017-02-051-0/+62
| | | | | | load folding tables. llvm-svn: 294152
* [AVX-512] Add masked scalar FMA intrinsics to ↵Craig Topper2017-02-051-8/+4
| | | | | | isNonFoldablePartialRegisterLoad to improve load folding of scalar loads. llvm-svn: 294151
* [AVX-512] Add test cases that show failure to fold scalar loads into masked ↵Craig Topper2017-02-051-0/+108
| | | | | | scalar FMA intrinsics. llvm-svn: 294150
* [AVX-512] Move 128/256-bit intrinsic tests from avx512bwvl test file to ↵Craig Topper2017-02-052-1111/+1112
| | | | | | avx512vl test file. llvm-svn: 294149
* [X86][AVX] Add 8i32 -> 8f32 sitofp tests with constant insertionSimon Pilgrim2017-02-051-0/+158
| | | | | | Some elements are constant inserted into the source integer vector before conversion. llvm-svn: 294147
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