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* Add llvm.codeview.annotation to implement MSVC __annotationReid Kleckner2017-09-052-0/+108
| | | | | | | | | | | | | | | | | | Summary: This intrinsic represents a label with a list of associated metadata strings. It is modelled as reading and writing inaccessible memory so that it won't be removed as dead code. I think the intention is that the annotation strings should appear at most once in the debug info, so I marked it noduplicate. We are allowed to inline code with annotations as long as we strip the annotation, but that can be done later. Reviewers: majnemer Subscribers: eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D36904 llvm-svn: 312569
* [X86] Remove unnecessary (v4f32 (X86vzmovl (v4f32 (scalar_to_vector ↵Craig Topper2017-09-051-4/+4
| | | | | | | | | | | | | | | | | | FR32X)))) patterns We had already disabled the pattern for SSE4.1 and SSE4.2. But it got re-enabled for AVX and AVX512. With SSE41 we rely on a separate (v4f32 (X86vzmovl VR128)) pattern to select blendps with a xorps to create zeroess. And a separate (v4f32 (scalar_to_vector FR32X)) to select a COPY_TO_REG_CLASS to move FR32 to VR128 The same thing can happen for AVX with vblendps and those separate patterns already exist. For AVX512, (v4f32 (X86vzmov VR128)) will select a VMOVSS instruction instead of VBLENDPS due to their not being a EVEX VBLENDPS. This is what we were getting out of the larger pattern anyway. So the larger pattern is unneeded for AVX512 too. For SSE1-SSSE3 we can rely on (v4f32 (X86vzmov VR128)) selecting a MOVSS similar to AVX512. Again this is what the larger pattern did too. So the only real change here is that AVX1/2 now properly outputs a VBLENDPS during isel instead of a VMOVSS to match SSE41. Most tests didn't notice because the two address instruction pass knows how to turn VMOVSS into VBLENDPS to get an independent destination register. llvm-svn: 312564
* AMDGPU: Fix not accounting for tail call resource usageMatt Arsenault2017-09-051-0/+31
| | | | | | | | If the only call in a function is a tail call, the function isn't considered to have a call since it's a type of return. llvm-svn: 312561
* X86 Tests: Adding missing AVX512 fptoui coverage tests. NFC.Zvi Rackover2017-09-051-0/+231
| | | | | | Some of the cases show missing pattern i intend to fix shortly. llvm-svn: 312560
* Split opt-remark YAML and opt output testing on this testAdam Nemet2017-09-051-2/+5
| | | | | | This prepares for https://reviews.llvm.org/D33514 llvm-svn: 312544
* [AVX512] Remove patterns for (v8f32 (X86vzmovl (insert_subvector undef, ↵Craig Topper2017-09-051-0/+1
| | | | | | | | (v4f32 (scalar_to_vector FR32X:)), (iPTR 0)))) and the same for v4f64. We don't have this same pattern for AVX2 so I don't believe we should have it for AVX512. We also didn't have it for v16f32. llvm-svn: 312543
* [AMDGPU] Added extra test checks to make D19325 diff clearerSimon Pilgrim2017-09-051-5/+11
| | | | llvm-svn: 312537
* [X86] Limit store merge size when implicitfloat is enabled (PR34421)Simon Pilgrim2017-09-051-0/+40
| | | | | | | | As suggested by @niravd : https://bugs.llvm.org/show_bug.cgi?id=34421#c2 Differential Revision: https://reviews.llvm.org/D37464 llvm-svn: 312534
* [X86] Regenerate scalar rotation testsSimon Pilgrim2017-09-052-69/+207
| | | | llvm-svn: 312530
* [X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift testsSimon Pilgrim2017-09-059-38/+76
| | | | llvm-svn: 312529
* [X86][AVX512] Use AVX512 attributes instead of -mcpuSimon Pilgrim2017-09-053-8/+18
| | | | llvm-svn: 312528
* Fix test/DebugInfo/dwarfdump-decompression-invalid-size.testJonas Devlieghere2017-09-051-0/+2
| | | | llvm-svn: 312527
* [Decompression] Fail gracefully when out of memoryJonas Devlieghere2017-09-052-0/+13
| | | | | | | | | | | | This patch adds failing gracefully when running out of memory when allocating a buffer for decompression. This provides a work-around for: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3224 Differential revision: https://reviews.llvm.org/D37447 llvm-svn: 312526
* [ARM] GlobalISel: Support global variables for RWPIDiana Picus2017-09-053-12/+72
| | | | | | | | | In RWPI code, globals that are not read-only are accessed relative to the SB register (R9). This is achieved by explicitly generating an ADD instruction between SB and an offset that we either load from a constant pool or movw + movt into a register. llvm-svn: 312521
* [InstCombine] Add test cases for folding (select (icmp ne/eq (and X, C1), ↵Craig Topper2017-09-051-1/+800
| | | | | | | | | | (bitwiseop Y, C2), Y -> (bitwiseop Y, (shl/shr (and X, C1), C3)) or similar. This is possible if C1 and C2 are both powers of 2. Or if binop is 'and' then ~C2 needs to be a power of 2. We already support this for 'or', but we should be able to support 'and' and 'xor'. This will be enhanced by D37274. llvm-svn: 312519
* [PowerPC] eliminate redundant compare instructionHiroshi Inoue2017-09-051-0/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If multiple conditional branches are executed based on the same comparison, we can execute multiple conditional branches based on the result of one comparison on PPC. For example, if (a == 0) { ... } else if (a < 0) { ... } can be executed by one compare and two conditional branches instead of two pairs of a compare and a conditional branch. This patch identifies a code sequence of the two pairs of a compare and a conditional branch and merge the compares if possible. To maximize the opportunity, we do canonicalization of code sequence before merging compares. For the above example, the input for this pass looks like: cmplwi r3, 0 beq 0, .LBB0_3 cmpwi r3, -1 bgt 0, .LBB0_4 So, before merging two compares, we canonicalize it as cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq beq 0, .LBB0_3 cmpwi r3, 0 ; greather than -1 means greater or equal to 0 bge 0, .LBB0_4 The generated code should be cmpwi r3, 0 beq 0, .LBB0_3 bge 0, .LBB0_4 Differential Revision: https://reviews.llvm.org/D37211 llvm-svn: 312514
* NewGVN: Fix PR 34430 - we need to look through predicateinfo copies to ↵Daniel Berlin2017-09-051-0/+48
| | | | | | detect self-cycles of phi nodes. We also need to not ignore certain types of arguments when testing whether the phi has a backedge or was originally constant. llvm-svn: 312510
* NewGVN: Fix PR 34452 by passing instruction all the way down when we do ↵Daniel Berlin2017-09-051-0/+49
| | | | | | aggregate value simplification llvm-svn: 312509
* [x86] add tests for vector store merge opportunity; NFCSanjay Patel2017-09-041-0/+139
| | | | llvm-svn: 312504
* [x86] auto-generate complete checks; NFCSanjay Patel2017-09-041-7/+21
| | | | llvm-svn: 312503
* [x86] add/regenerate complete checks; NFCSanjay Patel2017-09-043-78/+146
| | | | llvm-svn: 312502
* [x86] add test for unnecessary cmp + masked store; NFCSanjay Patel2017-09-041-0/+28
| | | | | | | | | As noted in PR11210: https://bugs.llvm.org/show_bug.cgi?id=11210 ...fixing this should allow us to eliminate x86-specific masked store intrinsics in IR. (Although more testing will be needed to confirm that.) llvm-svn: 312496
* Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source ↵Sam McCall2017-09-0473-303/+320
| | | | | | | | | | forwarding"" This crashes on boringSSL on PPC (will send reduced testcase) This reverts commit r312328. llvm-svn: 312490
* Fix test/Transforms/GlobalOpt/integer-bool-dwarfStrahinja Petrovic2017-09-041-11/+2
| | | | | | | | | This patch fixes regression related with integer-bool-dwarf test. Patch by Nikola Prica. llvm-svn: 312489
* Update test for testing avx512Michael Zuckerman2017-09-041-26/+26
| | | | llvm-svn: 312487
* [X86][AVX512] Add support for VPERMILPS v16f32 shuffle lowering (PR34382)Simon Pilgrim2017-09-042-42/+31
| | | | | | Avoid use of VPERMPS where we don't need it by instead using the variable mask version of VPERMILPS for unary shuffles. llvm-svn: 312486
* Added shuffle test case from PR34382Simon Pilgrim2017-09-041-0/+11
| | | | llvm-svn: 312485
* Added shuffle test case from PR34369Simon Pilgrim2017-09-041-0/+37
| | | | llvm-svn: 312481
* [DebugInfo] - Fix for lld DWARF parsing of base address selection entries in ↵George Rimar2017-09-043-0/+95
| | | | | | | | | | | | | range lists. It solves issue of wrong section index evaluating for ranges when base address is used. Based on David Blaikie's patch D36097. Differential revision: https://reviews.llvm.org/D37214 llvm-svn: 312477
* [X86] Replace -mcpu option with -mattr in LIT tests added in ↵Ayman Musa2017-09-0413-952/+953
| | | | | | https://reviews.llvm.org/rL312442 llvm-svn: 312474
* [GlobalISel][X86] G_PHI support.Igor Breger2017-09-044-1/+1321
| | | | llvm-svn: 312473
* LoopVectorize: MaxVF should not be larger than the loop trip countZvi Rackover2017-09-041-0/+35
| | | | | | | | | | | | | | | | | | | | | | | Summary: Improve how MaxVF is computed while taking into account that MaxVF should not be larger than the loop's trip count. Other than saving on compile-time by pruning the possible MaxVF candidates, this patch fixes pr34438 which exposed the following flow: 1. Short trip count identified -> Don't bail out, set OptForSize:=True to avoid tail-loop and runtime checks. 2. Compute MaxVF returned 16 on a target supporting AVX512. 3. OptForSize -> choose VF:=MaxVF. 4. Bail out because TripCount = 8, VF = 16, TripCount % VF !=0 means we need a tail loop. With this patch step 2. will choose MaxVF=8 based on TripCount. Reviewers: Ayal, dorit, mkuper, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D37425 llvm-svn: 312472
* [LoopUnroll][DebugInfo] Don't add metadata to unrolled remainder loopSam Parker2017-09-042-2/+108
| | | | | | | | | | | | | | | Debug information can be, and was, corrupted when the runtime remainder loop was fully unrolled. This is because a !null node can be created instead of a unique one describing the loop. In this case, the original node gets incorrectly updated with the NewLoopID metadata. In the case when the remainder loop is going to be quickly fully unrolled, there isn't the need to add loop metadata for it anyway. Differential Revision: https://reviews.llvm.org/D37338 llvm-svn: 312471
* [XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic ↵Dean Michael Berris2017-09-0411-85/+73
| | | | | | | | | | | | | | | | | references in .text Summary: This is a re-roll of D36615 which uses PLT relocations in the back-end to the call to __xray_CustomEvent() when building in -fPIC and -fxray-instrument mode. Reviewers: pcc, djasper, bkramer Subscribers: sdardis, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D37373 llvm-svn: 312466
* [X86] Add a combine to recognize when we have two insert subvectors that ↵Craig Topper2017-09-042-3/+0
| | | | | | | | together write the whole vector, but the starting vector isn't undef. In this case we should replace the starting vector with undef. llvm-svn: 312462
* [X86] Add a combine to turn (insert_subvector zero, (insert_subvector zero, ↵Craig Topper2017-09-032-6/+0
| | | | | | X, Idx), Idx) into an insert of X into the larger zero vector. llvm-svn: 312460
* [X86] Add more patterns to use moves to zero the upper portions of a vector ↵Craig Topper2017-09-032-30/+15
| | | | | | register that I missed in r312450. llvm-svn: 312459
* [X86] Combine inserting a vector of zeros into a vector of zeros just the ↵Craig Topper2017-09-031-14/+4
| | | | | | larger vector. llvm-svn: 312458
* [X86] Add patterns to turn an insert into lower subvector of a zero vector ↵Craig Topper2017-09-038-186/+97
| | | | | | | | into a move instruction which will implicitly zero the upper elements. Ideally we'd be able to emit the SUBREG_TO_REG without the explicit register->register move, but we'd need to be sure the producing operation would select something that guaranteed the upper bits were already zeroed. llvm-svn: 312450
* [X86] Add VBLENDPS/VPBLENDD to the execution domain fixing tables.Craig Topper2017-09-0326-276/+205
| | | | llvm-svn: 312449
* [X86] Canonicalize (concat_vectors X, zero) -> (insert_subvector zero, X, 0).Craig Topper2017-09-036-121/+93
| | | | | | In a future patch, I plan to teach isel to use a small vector move with implicit zeroing of the upper elements when it sees the (insert_subvector zero, X, 0) pattern. llvm-svn: 312448
* [InstCombine] add tests for fcmp ord/uno canonicalization; NFCSanjay Patel2017-09-033-0/+171
| | | | | | Currently, we canonicalize some cases to use 0.0, but we miss others. llvm-svn: 312445
* [X86] Add -mtriple option to LIT tests added in ↵Ayman Musa2017-09-0313-13/+13
| | | | | | https://reviews.llvm.org/rL312442 llvm-svn: 312443
* [X86][AVX512] Add simple tests for all AVX512 shuffle instructions.Ayman Musa2017-09-0313-0/+26357
| | | | | | | | | | | | | | | | Throughout an effort to strongly check the behavior of CodeGen with the IR shufflevector instruction we generated many tests while predicting the best X86 sequence that may be generated. This is a subset of the generated tests that we think may add value to our X86 set of tests. Some of the checks are not optimal and will be changed after fixing: 1. PR34394 2. PR34382 3. PR34380 4. PR34359 Differential Revision: https://reviews.llvm.org/D37329 llvm-svn: 312442
* [X86] Add RUN line for LIT test committed in "rL312438: [X86] Fix crash on ↵Ayman Musa2017-09-031-1/+3
| | | | | | assert of non-simple type after type-legalization.". llvm-svn: 312439
* [X86] Fix crash on assert of non-simple type after type-legalizationAyman Musa2017-09-031-0/+22
| | | | | | | | | | The function combineShuffleToVectorExtend in DAGCombine might generate an illegal typed node after "legalize types" phase, causing assertion on non-simple type to fail afterwards. Adding a type check in case the combine is running after the type legalize pass. Differential Revision: https://reviews.llvm.org/D37330 llvm-svn: 312438
* Add llvm-isel-fuzzer to test/CMakeLists.txtHal Finkel2017-09-031-0/+1
| | | | | | | Tests were added that depend on llvm-isel-fuzzer in r312427, so the tests should depend on the tool. llvm-svn: 312433
* Revert "[XRay][tools] Function call stack based analysis tooling for XRay ↵Keith Wyss2017-09-034-137/+0
| | | | | | | | | | traces" This reverts commit 204a65e0702847a1880336372ad7abd1df414b44. Double ref qualifier failed bots. llvm-svn: 312428
* llvm-isel-fuzzer: Add some basic testsJustin Bogner2017-09-036-0/+29
| | | | llvm-svn: 312427
* [XRay][tools] Function call stack based analysis tooling for XRay tracesKeith Wyss2017-09-034-0/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a subcommand to the llvm-xray tool called "stacks" which allows for analysing XRay traces provided as inputs and accounting time to stacks instead of just individual functions. This gives us a more precise view of where in a program the latency is actually attributed. The tool uses a trie data structure to keep track of the caller-callee relationships as we process the XRay traces. In particular, we keep track of the function call stack as we enter functions. While we're doing this we're adding nodes in a trie and indicating a "calls" relatinship between the caller (current top of the stack) and the callee (the new top of the stack). When we push function ids onto the stack, we keep track of the timestamp (TSC) for the enter event. When exiting functions, we are able to account the duration by getting the difference between the timestamp of the exit event and the corresponding entry event in the stack. This works even if we somehow miss the exit events for intermediary functions (i.e. if the exit event is not cleanly associated with the enter event at the top of the stack). The output of the tool currently provides just the top N leaf functions that contribute the most latency, and the top N stacks that have the most frequency. In the future we can provide more sophisticated query mechanisms and potentially an export to database feature to make offline analysis of the stack traces possible with existing tools. llvm-svn: 312426
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