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* If a function needs a frame pointer, but r11 (aka fp) has not been used,Joerg Sonnenberger2014-05-065-36/+38
| | | | | | | | remove it from the list of unspilled registers. Otherwise the following attempt to keep the stack aligned by picking an extra GPR register to spill will not work as it picks up r11. llvm-svn: 208129
* Do not make -pass-remarks additive.Diego Novillo2014-05-061-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When I initially introduced -pass-remarks, I thought it would be a neat idea to make it additive. So, if one used it as: $ llc -pass-remarks=inliner --pass-remarks=loop.* the compiler would build the regular expression '(inliner)|(loop.*)'. The more I think about it, the more I regret it. This is not how other flags work. The standard semantics are right-to-left overrides. This is how clang interprets -Rpass. And I think the two should be compatible in this respect. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3614 llvm-svn: 208122
* TTI: Estimate @llvm.fmuladd cost as fmul + fadd when FMA's aren't legal on ↵Benjamin Kramer2014-05-061-0/+28
| | | | | | the target. llvm-svn: 208115
* [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 ↵Andrea Di Biagio2014-05-062-2/+83
| | | | | | | | | | | | | | | | | | | | (and vice versa). Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. llvm-svn: 208107
* Implememting named register intrinsicsRenato Golin2014-05-0612-0/+204
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* Special case aliases in GlobalValue::getAlignment.Rafael Espindola2014-05-061-0/+14
| | | | | | | | | An alias has the address of what it points to, so it also has the same alignment. This allows a few optimizations to see past aliases for free. llvm-svn: 208103
* AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover2014-05-061-0/+1
| | | | llvm-svn: 208091
* AArch64/ARM64: add two more MC tests to ARM64 set.Tim Northover2014-05-062-0/+4
| | | | llvm-svn: 208085
* AArch64/ARM64: enable MC-level diagnostic tests for NEON insts.Tim Northover2014-05-062-392/+663
| | | | | | | | | Obviously we can't expect the two backends to produce identical diagnostics, since what's possible depends quite a bit on how the .td files are structured. I think the ARM64 diagnostics are basically of the same quality in all the changed cases, so I've split the CHECK lines. llvm-svn: 208084
* AArch64/ARM64: make NEON vector list parsing a bit more robustTim Northover2014-05-061-1/+1
| | | | | | | It doesn't change the results, but it seems silly not to diagnose obvious problems early on. llvm-svn: 208083
* AArch64/ARM64: produce more informative diagnostic assembling some immediatesTim Northover2014-05-062-18/+18
| | | | | | | No tests here, they'll be added when the entire neon-diagnostics.s test from AArch64 is enabled. llvm-svn: 208079
* ARM: For thumb fixups store halfwords high first and low secondChristian Pirker2014-05-061-0/+12
| | | | llvm-svn: 208076
* [ARM64] Enable alignment control option in front-end for ARM64.Kevin Qin2014-05-061-0/+1
| | | | | | This is the modification in llvm part. llvm-svn: 208074
* Fix i128 div/mod on mingw64Reid Kleckner2014-05-061-0/+26
| | | | | | | | | | The Win64 docs are very clear that anything larger than 8 bytes is passed by reference, and GCC MinGW64 honors that for __modti3 and friends. Patch by Jameson Nash! llvm-svn: 208029
* Improve 'tail' call marking in TRE. A bootstrap of clang goes from 375k ↵Nick Lewycky2014-05-051-0/+23
| | | | | | | | | | calls marked tail in the IR to 470k, however this improvement does not carry into an improvement of the call/jmp ratio on x86. The most common pattern is a tail call + br to a block with nothing but a 'ret'. The number of tail call to loop conversions remains the same (1618 by my count). The new algorithm does a local scan over the use-def chains to identify local "alloca-derived" values, as well as points where the alloca could escape. Then, a visit over the CFG marks blocks as being before or after the allocas have escaped, and annotates the calls accordingly. llvm-svn: 208017
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-18/+37
| | | | llvm-svn: 208005
* Revert "Optimize shufflevector that copies an i64/f64 and zeros the rest."Filipe Cabecinhas2014-05-052-16/+0
| | | | | | This reverts commit 207992. I misread the phab number on the LGTM. llvm-svn: 207993
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-052-0/+16
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 207992
* Move test from r207969 to another folder and rename it.Michael Zolotukhin2014-05-051-0/+0
| | | | llvm-svn: 207984
* Always set alignment of vectorized LD/ST in SLP-Vectorizer. ↵Yi Jiang2014-05-051-0/+27
| | | | | | <rdar://problem/16812145> llvm-svn: 207983
* Fix spelling.Joerg Sonnenberger2014-05-051-0/+0
| | | | llvm-svn: 207982
* LTO: -internalize sets visibility to defaultDuncan P. N. Exon Smith2014-05-051-0/+25
| | | | | | | | | Visibility is meaningless when the linkage is local. Change `-internalize` to reset the visibility to `default`. <rdar://problem/16141113> llvm-svn: 207979
* Remove the -disable-cfi option.Rafael Espindola2014-05-051-34/+0
| | | | | | | This also add a release note about it. If this stays I will cleanup MC next week. llvm-svn: 207977
* [Test] Remove substitution for clangAdam Nemet2014-05-051-1/+0
| | | | | | | | | clang should not be used in the llvm tests. The topic was discussed in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html llvm-svn: 207976
* Modify test to not use -disable-cfi.Rafael Espindola2014-05-052-34/+27
| | | | llvm-svn: 207974
* Move test to the ARM64 directory.Rafael Espindola2014-05-051-0/+0
| | | | llvm-svn: 207972
* Convert a CodeGen test into a MC test.Rafael Espindola2014-05-052-161/+208
| | | | llvm-svn: 207971
* Fix test from r207966 and add a comment there.Michael Zolotukhin2014-05-051-2/+4
| | | | llvm-svn: 207969
* Add regression test for r207692.Michael Zolotukhin2014-05-051-0/+23
| | | | llvm-svn: 207966
* CodeGen: correct memset emittance for WoASaleem Abdulrasool2014-05-041-0/+18
| | | | | | | | Windows on ARM does not conform to AEABI. However, memset would be emitted using the AEABI signature, resulting in inverted parameters. Handle this special case appropriately. llvm-svn: 207943
* CodeGen: strengthen WoA AEABI avoidance testsSaleem Abdulrasool2014-05-041-0/+22
| | | | | | Add additional test cases for WoA AEABI avoidance checking. llvm-svn: 207942
* MC: support FK_SecRel_4 for Windows on ARMSaleem Abdulrasool2014-05-041-0/+41
| | | | | | | | | Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. llvm-svn: 207941
* LoopUnroll: If we're doing partial unrolling, use the PartialThreshold to ↵Benjamin Kramer2014-05-041-0/+47
| | | | | | | | | | | limit unrolling. Otherwise we use the same threshold as for complete unrolling, which is way too high. This made us unroll any loop smaller than 150 instructions by 8 times, but only if someone specified -march=core2 or better, which happens to be the default on darwin. llvm-svn: 207940
* SLPVectorizer: Bring back the insertelement patch (r205965) with fixesArnold Schwaighofer2014-05-042-0/+140
| | | | | | | | | | | | | | | | When can't assume a vectorized tree is rooted in an instruction. The IRBuilder could have constant folded it. When we rebuild the build_vector (the series of InsertElement instructions) use the last original InsertElement instruction. The vectorized tree root is guaranteed to be before it. Also, we can't assume that the n-th InsertElement inserts the n-th element into a vector. This reverts r207746 which reverted the revert of the revert of r205018 or so. Fixes the test case in PR19621. llvm-svn: 207939
* AVX-512: minor change in rndscale intrinsicElena Demikhovsky2014-05-041-2/+2
| | | | llvm-svn: 207937
* X86: repair export compatibility with MinGW/cygwinSaleem Abdulrasool2014-05-041-36/+41
| | | | | | | | | | | | | | Both MinGW and cygwin (i686) construct export directives without the global leader prefix. This is mostly due to the fact that they use GNU ld which does not correctly handle the export directive. This apparently has been been broken for a while. However, this was recently reported as being broken by mingwandroid and diorcety of the msys2 project. Remove the global leader prefix if targeting MinGW or cygwin, otherwise, retain the global leader prefix. Add an explicit test for cygwin's behaviour of export directives. llvm-svn: 207926
* Fix pr19645.Rafael Espindola2014-05-032-1/+5
| | | | | | | | | | | | | | | | The fix itself is fairly simple: move getAccessVariant to MCValue so that we replace the old weak expression evaluation with the far more general EvaluateAsRelocatable. This then requires that EvaluateAsRelocatable stop when it finds a non trivial reference kind. And that in turn requires the ELF writer to look harder for weak references. Last but not least, this found a case where we were being bug by bug compatible with gas and accepting an invalid input. I reported pr19647 to track it. llvm-svn: 207920
* [ARM64] Correctly select ANDWri in FastISel.Joey Gouly2014-05-031-1/+1
| | | | | | http://reviews.llvm.org/D3598 llvm-svn: 207917
* Vectorize intrinsic math function calls in SLPVectorizer.Karthik Bhat2014-05-031-0/+128
| | | | | | | This patch adds support to recognize and vectorize intrinsic math functions in SLPVectorizer. Review: http://reviews.llvm.org/D3560 and http://reviews.llvm.org/D3559 llvm-svn: 207901
* [LSR] Add llc testcase for r207271/r207569.Adam Nemet2014-05-021-0/+70
| | | | | | | See PR19608 for the details but to summarize it was easy to modify the .ll file to get the desired def-use ordering. llvm-svn: 207887
* [sanitizers] Propagate the sanitizer options through to the lit context.Chandler Carruth2014-05-021-0/+5
| | | | | | | | This makes it *really* easy to debug leaks FYI: ASAN_OPTIONS=detect_leaks=1 ./bin/llvm-lit -v <path to test> llvm-svn: 207874
* llvm-cov: Fix handling of line zero appearing in a line tableJustin Bogner2014-05-024-1/+30
| | | | | | | | | | | | | Reading line tables in llvm-cov was pretty broken, but would happen to work as long as no line in the table was 0. It's not clear to me whether a line of zero *should* show up in these tables, but deciding to read a string in the middle of the line table is certainly the wrong thing to do if it does. I've also added some comments, as trying to figure out what this block of code was doing was fairly unpleasant. llvm-svn: 207866
* [tablegen] !strconcat accepts more than two arguments but this wasn't ↵Daniel Sanders2014-05-021-1/+13
| | | | | | | | | | | | | | | | | | | | documented or tested. Summary: * Updated the documentation * Added a test for >2 arguments * Added a check for the lexical concatenation * Made the existing test a bit stricter. Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: http://reviews.llvm.org/D3485 llvm-svn: 207865
* Teach GlobalDCE how to remove empty global_ctor entries.Nico Weber2014-05-022-0/+59
| | | | | | | | | | | | | | | | | This moves most of GlobalOpt's constructor optimization code out of GlobalOpt into Transforms/Utils/CDtorUtils.{h,cpp}. The public interface is a single function OptimizeGlobalCtorsList() that takes a predicate returning which constructors to remove. GlobalOpt calls this with a function that statically evaluates all constructors, just like it did before. This part of the change is behavior-preserving. Also add a call to this from GlobalDCE with a filter that removes global constructors that contain a "ret" instruction and nothing else – this fixes PR19590. llvm-svn: 207856
* [GVN] Pass the phi-translated address of a load instead of the untranslatedAkira Hatanaka2014-05-021-0/+87
| | | | | | | | | address to AnalyzeLoadFromClobberingLoad. This fixes a bug in load-PRE where PRE is applied to a load that is not partially redundant. <rdar://problem/16638765>. llvm-svn: 207853
* MC: place .file records into the correct sectionSaleem Abdulrasool2014-05-022-0/+60
| | | | | | | | | .file records are supposed to have a section identifier of 65534 (IMAGE_SCN_DEBUG) rather than 0. This is spelt out clearly within the PE/COFF specification. Fix this minor oversight with the implementation for support for .file records. llvm-svn: 207851
* DAGCombine: prevent formation of illegal ConstantFP nodes.Tim Northover2014-05-021-0/+14
| | | | llvm-svn: 207850
* R600: Expand vector sin and cos.Tom Stellard2014-05-022-22/+65
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+40
| | | | llvm-svn: 207844
* AArch64/ARM64: add patterns for post-indexed ST1 ops.Tim Northover2014-05-021-0/+211
| | | | llvm-svn: 207840
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