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* [InstCombine] add tests to show type limitations of InsertRangeTest and callersSanjay Patel2016-08-303-3/+56
| | | | llvm-svn: 280175
* Add a test file, macho-invalid-dysymtab-extreloff-nextrel,Kevin Enderby2016-08-301-0/+0
| | | | | | I forgot to do an svn add on. llvm-svn: 280167
* Next set of additional error checks for invalid Mach-O files for bad ↵Kevin Enderby2016-08-3015-0/+45
| | | | | | | | LC_DYSYMTAB’s. This contains the missing checks for LC_DYSYMTAB load command fields. llvm-svn: 280161
* GlobalISel: combine extracts & sequences created for legalizationTim Northover2016-08-302-10/+108
| | | | | | | | Legalization ends up creating many G_SEQUENCE/G_EXTRACT pairs which leads to inefficient codegen (even for -O0), so add a quick pass over the function to remove them again. llvm-svn: 280155
* AMDGPU: Relax SGPR asm constraint register classMatt Arsenault2016-08-301-0/+10
| | | | | | | s should be SReg_32 to be as general as possible. This can avoid a copy from m0. llvm-svn: 280154
* Revert "ELFDumper: Unversioned symbols must not have trailing @"Hemant Kulkarni2016-08-302-13/+13
| | | | | | | | This reverts commit 8df7a877949e8782a3a28e3ecdb0770c1e444056. Fixing other repositories and adding changes together. llvm-svn: 280152
* [LoopVectorizer] Predicate instructions in blocks with several incoming edgesMichael Kuperstein2016-08-302-4/+62
| | | | | | | | | | We don't need to limit predication to blocks that have a single incoming edge, we just need to use the right mask. This fixes PR30172. Differential Revision: https://reviews.llvm.org/D24009 llvm-svn: 280148
* IntrArgMemOnly is only defined (and current AA machinery only sanely ↵Daniel Berlin2016-08-301-0/+42
| | | | | | supports) pointer arguments, and these intrinsics have vector of pointer arguments. Remove ArgMemOnly until we either have the machinery, define a new attribute, or something similar llvm-svn: 280143
* ELFDumper: Unversioned symbols must not have trailing @Hemant Kulkarni2016-08-302-13/+13
| | | | llvm-svn: 280140
* GlobalISel: forbid physical registers on generic MIs.Tim Northover2016-08-308-72/+160
| | | | | | | | | | We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
* llvm-readobj: add support for printing GNU NotesSaleem Abdulrasool2016-08-301-0/+76
| | | | | | | | | Add support for printing the GNU Notes. This allows an easy way to view the build id for a binary built with the build id. Currently, this only handles the GNU notes, though it would be easy to extend for other note types (default, FreeBSD, NetBSD, etc). Only the GNU style is supported currently. llvm-svn: 280131
* [InstCombine] replace divide-by-constant checks with asserts; NFCSanjay Patel2016-08-301-1/+16
| | | | | | | These folds already have tests for scalar and vector types, except for the vector div-by-0 case, so I'm adding tests for that. llvm-svn: 280115
* [SimplifyCFG] Properly CSE metadata in SinkThenElseCodeToEndJames Molloy2016-08-301-0/+37
| | | | | | This was missing, meaning the metadata in sunk instructions was potentially bogus and could cause miscompiles. llvm-svn: 280072
* [llvm-cov] Use the native path in the coverage report.Ying Yi2016-08-303-0/+23
| | | | | | | | | | | The coverage reports contain the source or binary file paths. On Windows, the file path might contain the seperators of both '/' and '\'. This patch uses the native path in the coverage reports. For example, on Windows, all '/' are converted to '\'. Differential Revision: https://reviews.llvm.org/D23922 llvm-svn: 280061
* [PowerPC] Force entry alignment in .got2Hal Finkel2016-08-301-0/+1
| | | | | | | | | Implement Bill's suggested fix for 32-bit targets for PR22711 (for the alignment of each entry). As pointed out in the bug report, we could just force the section alignment, since we only add pointer-sized things currently, but this fix is somewhat more future-proof. llvm-svn: 280049
* [sanitizer-coverage] add two more modes of instrumentation: trace-div and ↵Kostya Serebryany2016-08-304-4/+73
| | | | | | trace-gep, mostly usaful for value-profile-based fuzzing; llvm part llvm-svn: 280043
* [PowerPC] Add support for -mlongcallHal Finkel2016-08-301-0/+26
| | | | | | | | | | | The "long call" option forces the use of the indirect calling sequence for all calls (even those that don't really need it). GCC provides this option; This is helpful, under certain circumstances, for building very-large binaries, and some other specialized use cases. Fixes PR19098. llvm-svn: 280040
* [PowerPC] Add triple to test/CodeGen/PowerPC/atomic-2.ll for ppc64leHal Finkel2016-08-301-1/+1
| | | | | | Otherwise, running the test on Darwin systems will not work. llvm-svn: 280034
* [ThinLTO] Indirect call promotion fixes for promoted local functionsTeresa Johnson2016-08-292-3/+19
| | | | | | | | | | | | | | | | | | | Summary: Fix a couple issues limiting the application of indirect call promotion in ThinLTO mode: - Invoke indirect call promotion before globalopt, since it may eliminate imported functions which appear unreferenced. - Invoke indirect call promotion with InLTO=true so that the PGOFuncName metadata is used to get the name for locals which would have been renamed during promotion. Reviewers: davidxl, mehdi_amini Subscribers: Prazek, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D24004 llvm-svn: 280024
* [PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomicsHal Finkel2016-08-291-1/+14
| | | | | | | | | | | | | | For little-Endian PowerPC, we generally target only P8 and later by default. However, generic (older) 64-bit configurations are still an option, and in that case, partword atomics are not available (e.g. stbcx.). To lower i8/i16 atomics without true i8/i16 atomic operations, we emulate using i32 atomics in combination with a bunch of shifting and masking, etc. The amount by which to shift in little-Endian mode is different from the amount in big-Endian mode (it is inverted -- meaning we can leave off the xor when computing the amount). Fixes PR22923. llvm-svn: 280022
* ExecutionEngine: fix a bug in the movt/movw relocatorSaleem Abdulrasool2016-08-291-1/+17
| | | | | | | | | | According to the arm arm specifications, 4 bytes are needed for a shift instead of 8, this was causing the movt instruction to write to a different register sometimes. Patch by Walter Erquinigo! llvm-svn: 280005
* [LV] Move insertelement sequence after scalar definitionsMatthew Simpson2016-08-292-16/+58
| | | | | | | | | | | | | | After r279649 when getting a vector value from VectorLoopValueMap, we create an insertelement sequence on-demand if the value has been scalarized instead of vectorized. We previously inserted this insertelement sequence before the value's first vector user. However, this insert location is problematic if that user is the phi node of a first-order recurrence. With this patch, we move the insertelement sequence after the last scalar instruction we created when scalarizing the value. Thus, the value's vector definition in the new loop will immediately follow its scalar definitions. This should fix PR30183. Reference: https://llvm.org/bugs/show_bug.cgi?id=30183 llvm-svn: 280001
* Propagate TBAA info in SelectionDAG::getIndexedLoadKrzysztof Parzyszek2016-08-291-0/+37
| | | | | | Patch by Pranav Bhandarkar. llvm-svn: 279998
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-2923-62/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCNSchedStrategy re-uses most of GenericScheduler, it's just uses a different method to compute the excess and critical register pressure limits. It's not enabled by default, to enable it you need to pass -misched=gcn to llc. Shader DB stats: 32464 shaders in 17874 tests Totals: SGPRS: 1542846 -> 1643125 (6.50 %) VGPRS: 1005595 -> 904653 (-10.04 %) Spilled SGPRs: 29929 -> 27745 (-7.30 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 36688188 -> 37034900 (0.95 %) bytes LDS: 1913 -> 1913 (0.00 %) blocks Max Waves: 254101 -> 265125 (4.34 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 1338220 -> 1438499 (7.49 %) VGPRS: 886221 -> 785279 (-11.39 %) Spilled SGPRs: 29869 -> 27685 (-7.31 %) Spilled VGPRs: 334 -> 352 (5.39 %) Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread Code Size: 34315716 -> 34662428 (1.01 %) bytes LDS: 1551 -> 1551 (0.00 %) blocks Max Waves: 188127 -> 199151 (5.86 %) Wait states: 0 -> 0 (0.00 %) Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23688 llvm-svn: 279995
* [asan] Enable new stack poisoning with store instruction by defaultVitaly Buka2016-08-294-59/+106
| | | | | | | | | | Reviewers: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23968 llvm-svn: 279993
* AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the schedulerTom Stellard2016-08-2910-39/+61
| | | | | | | | | | | | | | | | | | | | Summary: The SILoadStoreOptimizer can now look ahead more then one instruction when looking for instructions to merge, which greatly improves the number of loads/stores that we are able to merge. Moving the pass before scheduling avoids increasing register pressure after the scheduler, so that the scheduler's register pressure estimates will be more accurate. It also gives more consistent results, since it is no longer affected by minor scheduling changes. Reviewers: arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: https://reviews.llvm.org/D23814 llvm-svn: 279991
* GlobalISel: legalize frem to a libcall on AArch64.Tim Northover2016-08-291-0/+14
| | | | llvm-svn: 279988
* AMDGPU/R600: Fix fixups used for constant arraysMatt Arsenault2016-08-291-0/+28
| | | | | | Fixes bug 29289 llvm-svn: 279986
* IfConversion: Fix branch predication bug.Kyle Butt2016-08-291-0/+37
| | | | | | | | | | | | This bug shows up with diamonds that share unpredicable, unanalyzable branches. There's an included test case from Hexagon. What was happening was that we were attempting to predicate the branch instruction despite the fact that it was checked to be the same. Now for unanalyzable branches we skip over the branch instructions when predicating the block. Differential Revision: https://reviews.llvm.org/D23939 llvm-svn: 279985
* Use store operation to poison allocas for lifetime analysis.Vitaly Buka2016-08-292-35/+624
| | | | | | | | | | | | | | | | | | Summary: Calling __asan_poison_stack_memory and __asan_unpoison_stack_memory for small variables is too expensive. Code is disabled by default and can be enabled by -asan-experimental-poisoning. PR27453 Reviewers: eugenis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23947 llvm-svn: 279984
* [SimplifyCFG] Hoisting invalidates metadataDavid Majnemer2016-08-291-0/+31
| | | | | | | | | We forgot to remove optimization metadata when performing hosting during FoldTwoEntryPHINode. This fixes PR29163. llvm-svn: 279980
* Make vec_fabs.ll pass with MSVC 2013Reid Kleckner2016-08-291-4/+7
| | | | | | We should revert this change once we drop support for MSVC 2013. llvm-svn: 279979
* [gold] Fix test accidentally regressed for newer goldTeresa Johnson2016-08-293-1/+18
| | | | | | | | | | | | With r279911 I accidentally regressed the gold/X86/start-lib-common.ll test for newer golds (v1.12+) that honor the --start-lib/--end-lib. Remove the alignment which should not be there to make this work with both old and new gold linkers. Additionally, now that we have a subdirectory for v1.12+ gold tests, copy this test there and check specifically for the v1.12+ behavior. llvm-svn: 279977
* [StatepointsForGC] Rematerialize in the presence of PHIsAnna Thomas2016-08-291-0/+37
| | | | | | | | | | | | | | | | Summary: While walking the use chain for identifying rematerializable values in RS4GC, add the case where the current value and base value are the same PHI nodes. This will aid rematerialization of geps and casts instead of relocating. Reviewers: sanjoy, reames, igor Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23920 llvm-svn: 279975
* [Constant] remove fdiv and frem from canTrap()Sanjay Patel2016-08-291-6/+3
| | | | | | | | | | | Assuming the default FP env, we should not treat fdiv and frem any differently in terms of trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env. This matches how we treat the fdiv/frem in IR with isSafeToSpeculativelyExecute() and in the backend after: https://reviews.llvm.org/rL279970 llvm-svn: 279973
* [SimplifyCFG] rename test file, regenerate checks, and add testSanjay Patel2016-08-292-41/+70
| | | | | | | The fdiv test shows a problem similar to: https://reviews.llvm.org/rL279970 llvm-svn: 279972
* [Coroutines] Part 9: Add cleanup subfunction.Gor Nishanov2016-08-299-39/+160
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: [Coroutines] Part 9: Add cleanup subfunction. This patch completes coroutine heap allocation elision. Now, the heap elision example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex3.ll) Intrinsic Changes: * coro.free gets a token parameter tying it to coro.id to allow reliably discovering all coro.frees associated with a particular coroutine. * coro.id gets an extra parameter that points back to a coroutine function. This allows to check whether a coro.id describes the enclosing function or it belongs to a different function that was later inlined. CoroSplit now creates three subfunctions: # f$resume - resume logic # f$destroy - cleanup logic, followed by a deallocation code # f$cleanup - just the cleanup code CoroElide pass during devirtualization replaces coro.destroy with either f$destroy or f$cleanup depending whether heap elision is performed or not. Other fixes, improvements: * Fixed buglet in Shape::buildFrame that was not creating coro.save properly if coroutine has more than one suspend point. * Switched to using variable width suspend index field (no longer limited to 32 bit index field can be as little as i1 or as large as i<whatever-size_t-is>) Reviewers: majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23844 llvm-svn: 279971
* [TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)Sanjay Patel2016-08-291-10/+2
| | | | | | | | | | | | | | | | | Assuming the default FP env, we should not treat fdiv and frem any differently in terms of trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env. This matches how we treat these ops in IR with isSafeToSpeculativelyExecute(). There's a similar bug in Constant::canTrap(). This bug manifests in PR29114: https://llvm.org/bugs/show_bug.cgi?id=29114 ...as a sequence of scalar divisions instead of a vector division on x86 for a <3 x float> type. Differential Revision: https://reviews.llvm.org/D23974 llvm-svn: 279970
* Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole registerKrzysztof Parzyszek2016-08-291-0/+48
| | | | | | | | | | | | | MRI::getMaxLaneMaskForVReg does not always cover the whole register. For example, on X86 the upper 16 bits of EAX cannot be accessed via any subregister. Consequently, there is no lane mask that only covers that part of EAX. The getMaxLaneMaskForVReg will return the union of the lane masks for all subregisters, and in case of EAX, that union will not cover the upper 16 bits. This fixes https://llvm.org/bugs/show_bug.cgi?id=29132 llvm-svn: 279969
* AMDGPU/SI: Improve register allocation hints for sopk instructionsTom Stellard2016-08-291-2/+2
| | | | | | | | | | | | | | | | | | | Summary: For shrinking SOPK instructions, we were creating a hint to tell the register allocator to use the register allocated for src0 for the dst operand as well. However, this seems to not work sometimes depending on the order virtual registers are assigned physical registers. To fix this, I've added a second allocation hint which does the reverse, asks that the register allocated for dst is used for src0. Reviewers: arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D23862 llvm-svn: 279968
* Use the correct ctor/dtor section for dynamic-no-pic.Rafael Espindola2016-08-291-0/+4
| | | | llvm-svn: 279967
* Mark test as XFAIL instead of disabling it everywhere.Benjamin Kramer2016-08-291-2/+2
| | | | | | | There is no lit feature 'X86' so this test is just disabled completely. Make it XFAIL until a solution is found. llvm-svn: 279966
* Fixed a bug in type legalizer for masked gather.Igor Breger2016-08-291-0/+33
| | | | | | | | | The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist. In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain). Differential Revision: http://reviews.llvm.org/D23756 llvm-svn: 279961
* [AVX512] In some cases KORTEST instruction may be used instead of ZEXT + ↵Igor Breger2016-08-295-723/+273
| | | | | | | | TEST sequence. Differential Revision: http://reviews.llvm.org/D23490 llvm-svn: 279960
* [X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just ↵Craig Topper2016-08-297-73/+188
| | | | | | | | create a ConstantFPSDNode and let that be lowered. This allows broadcast loads to used when available. llvm-svn: 279958
* [AVX-512] Add 512-bit fabs tests with and without AVX512DQ.Craig Topper2016-08-291-4/+84
| | | | llvm-svn: 279956
* [AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.Craig Topper2016-08-281-8/+2
| | | | llvm-svn: 279951
* [AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. ↵Craig Topper2016-08-281-5/+155
| | | | | | Will be fixed in a future commit. llvm-svn: 279949
* [x86] add tests for <3 x N> vector types (PR29114)Sanjay Patel2016-08-281-0/+40
| | | | llvm-svn: 279939
* [InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat ↵Sanjay Patel2016-08-284-18/+8
| | | | | | constant vectors llvm-svn: 279937
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