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* [SCEV] Make isLoopEntryGuardedByCond a bit smarterMax Kazantsev2018-02-074-7/+121
| | | | | | | | | | | Sometimes `isLoopEntryGuardedByCond` cannot prove predicate `a > b` directly. But it is a common situation when `a >= b` is known from ranges and `a != b` is known from a dominating condition. Thia patch teaches SCEV to sum these facts together and prove strict comparison via non-strict one. Differential Revision: https://reviews.llvm.org/D42835 llvm-svn: 324453
* The xfailed test from r324448 passed on one of the bots: remove it entirely ↵Michael Zolotukhin2018-02-071-69/+0
| | | | | | for now. llvm-svn: 324451
* [x86/retpoline] Make the external thunk names exactly match the namesChandler Carruth2018-02-071-24/+24
| | | | | | | | | | | | | | | | | | | that happened to end up in GCC. This is really unfortunate, as the names don't have much rhyme or reason to them. Originally in the discussions it seemed fine to rely on aliases to map different names to whatever external thunk code developers wished to use but there are practical problems with that in the kernel it turns out. And since we're discovering this practical problems late and since GCC has already shipped a release with one set of names, we are forced, yet again, to blindly match what is there. Somewhat rushing this patch out for the Linux kernel folks to test and so we can get it patched into our releases. Differential Revision: https://reviews.llvm.org/D42998 llvm-svn: 324449
* Xfail the test added in r324445 until the underlying issue in LoopSink is fixed.Michael Zolotukhin2018-02-072-61/+69
| | | | llvm-svn: 324448
* [LegalizeDAG] Truncate condition operand of ISD::SELECTEugene Leviant2018-02-071-0/+61
| | | | | | Differential revision: https://reviews.llvm.org/D42737 llvm-svn: 324447
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOUI as legalTom Stellard2018-02-071-0/+22
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D42152 llvm-svn: 324446
* Follow-up for r324429: "[LCSSAVerification] Run verification only when ↵Michael Zolotukhin2018-02-071-0/+61
| | | | | | | | | | | | | asserts are enabled." Before r324429 we essentially didn't have a verification of LCSSA, so no wonder that it has been broken: currently loop-sink breaks it (the attached test illustrates the failure). It was detected during a stage2 RA build, so to unbreak it I'm disabling the check for now. llvm-svn: 324445
* [ThinLTO] Serialize WithGlobalValueDeadStripping index flag for distributed ↵Teresa Johnson2018-02-079-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | backends Summary: A recent fix to drop dead symbols (r323633) did not work for ThinLTO distributed backends because we lose the WithGlobalValueDeadStripping set on the index during the thin link. This patch adds a new flags record to the bitcode format for the index, and serializes this flag for the combined index (it would always be 0 for the per-module index generated by the compile step, so no need to serialize the new flags record there until/unless we add another flag that applies to the per-module indexes). Generally this flag should always be set for the distributed backends, which are necessarily performed after the thin link. However, if we were to simply set this flag on the index applied to the distributed backends (invoked via clang), we would lose the ability to disable dead stripping via -compute-dead=false for debugging purposes. Reviewers: grimar, pcc Subscribers: mehdi_amini, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D42799 llvm-svn: 324444
* GlobalISel: Always check operand types when executing match tableVolkan Keles2018-02-071-0/+36
| | | | | | | | | | | | | | | | | | Summary: Some of the commands tries to get the register without checking if the specified operands is a register and causing crash. All commands should check the type of the operand first and reject if the type is not expected. Reviewers: dsanders, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42984 llvm-svn: 324442
* [AMDGPU] Suppress redundant waitcnt instrs.Mark Searles2018-02-071-0/+24
| | | | | | | | | | | | 1. Run the memory legalizer prior to the waitcnt pass; keep the policy that the waitcnt pass does not remove any waitcnts within the incoming IR. 2. The waitcnt pass doesn't (yet) track waitcnts that exist prior to the waitcnt pass (it just skips over them); because the waitcnt pass is ignorant of them, it may insert a redundant waitcnt. To avoid this, check the prev instr. If it and the to-be-inserted waitcnt are the same, suppress the insertion. We keep the existing waitcnt under the assumption that whomever, e.g., the memory legalizer, inserted it knows what they were doing. 3. Follow-on work: teach the waitcnt pass to record the pre-existing waitcnts for better waitcnt production. Differential Revision: https://reviews.llvm.org/D42854 llvm-svn: 324440
* [Mips][AMDGPU] Update test cases to not use vector lt/gt compares that can ↵Craig Topper2018-02-073-92/+98
| | | | | | | | | | be simplified to an equality/inequality or to always true/false. For example 'ugt X, 0' can be simplified to 'ne X, 0'. Or 'uge X, 0' is always true. We already simplify this for scalars in SimplifySetCC, but we don't currently for vectors in SimplifySetCC. D42948 proposes to change that. llvm-svn: 324436
* AMDGPU: Select BFI patterns with 64-bit intsMatt Arsenault2018-02-071-12/+146
| | | | llvm-svn: 324431
* [DAGCombiner][AMDGPU][X86] Turn cttz/ctlz into ↵Craig Topper2018-02-061-1/+2
| | | | | | | | | | | | cttz_zero_undef/ctlz_zero_undef if we can prove the input is never zero X86 currently has a late DAG combine after cttz/ctlz are turned into BSR+BSF+CMOV to detect this and remove the CMOV. But we should be able to do this much earlier and avoid creating the cmov all together. For the changed AMDGPU test case it appears that previously the i8 cttz was type legalized to i16 which introduced an OR with 256 in order to limit the result to 8 on the widened type. At this point the result is known to never be zero, but nothing checked that. Then operation legalization is told to promote all i16 cttz to i32. This introduces an extend and a truncate and another OR with 65536 to limit the result to 16. With the DAG combiner change we are able to prevent the creation of the second OR since the opcode will have been changed to cttz_zero_undef after the first OR. I the lack of the OR caused the instruction to change to v_ffbl_b32_sdwa Differential Revision: https://reviews.llvm.org/D42985 llvm-svn: 324427
* Add DWARF for discriminated unionsAdrian Prantl2018-02-064-2/+162
| | | | | | | | | | | | | | | | | | | | | | | | | n Rust, an enum that carries data in the variants is, essentially, a discriminated union. Furthermore, the Rust compiler will perform space optimizations on such enums in some situations. Previously, DWARF for these constructs was emitted using a hack (a magic field name); but this approach stopped working when more space optimizations were added in https://github.com/rust-lang/rust/pull/45225. This patch changes LLVM to allow discriminated unions to be represented in DWARF. It adds createDiscriminatedUnionType and createDiscriminatedMemberType to DIBuilder and then arranges for this to be emitted using DWARF's DW_TAG_variant_part and DW_TAG_variant. Note that DWARF requires that a discriminated union be represented as a structure with a variant part. However, as Rust only needs to emit pure discriminated unions, this is what I chose to expose on DIBuilder. Patch by Tom Tromey! Differential Revision: https://reviews.llvm.org/D42082 llvm-svn: 324426
* Place undefined globals in .bss instead of .dataEli Friedman2018-02-062-2/+16
| | | | | | | | | | | | | | | | | | | | | | Following up on the discussion from http://lists.llvm.org/pipermail/llvm-dev/2017-April/112305.html, undef values are now placed in the .bss as well as null values. This prevents undef global values taking up potentially huge amounts of space in the .data section. The following two lines now both generate equivalent .bss data: @vals1 = internal unnamed_addr global [20000000 x i32] zeroinitializer, align 4 @vals2 = internal unnamed_addr global [20000000 x i32] undef, align 4 ; previously unaccounted for This is primarily motivated by the corresponding issue in the Rust compiler (https://github.com/rust-lang/rust/issues/41315). Differential Revision: https://reviews.llvm.org/D41705 Patch by varkor! llvm-svn: 324424
* [LivePhysRegs] Fix handling of return instructions.Eli Friedman2018-02-062-1/+47
| | | | | | | | | | | | | | | | | See D42509 for the original version of this. Basically, there are two significant changes to behavior here: - addLiveOuts always adds all pristine registers (even if a block has no successors). - addLiveOuts and addLiveOutsNoPristines always add all callee-saved registers for return blocks (including conditional return blocks). I cleaned up the functions a bit to make it clear these properties hold. Differential Revision: https://reviews.llvm.org/D42655 llvm-svn: 324422
* Fix a crash when emitting DIEs for variable-length arraysAdrian Prantl2018-02-061-0/+99
| | | | | | | | | | | | | VLAs may refer to a previous DIE to express the DW_AT_count of their type. Clang generates an artificial "vla_expr" variable for this. If this DIE hasn't been created yet LLVM asserts. This patch fixes this by sorting the local variables so that dependencies come before they are needed. It also replaces the linear scan in DWARFFile with a std::map, which can be faster. Differential Revision: https://reviews.llvm.org/D42940 llvm-svn: 324412
* [X86] Add test cases that exercise the BSR/BSF optimization combineCMov.Craig Topper2018-02-061-0/+121
| | | | | | | | | | | | combineCmov tries to remove compares against BSR/BSF if we can prove the input to the BSR/BSF are never zero. As far as I can tell most of the time codegenprepare despeculates ctlz/cttz and gives us a cttz_zero_undef/ctlz_zero_undef which don't use a cmov. So the only way I found to trigger this code is to show codegenprepare an illegal type which it won't despeculate. I think we should be turning ctlz/cttz into ctlz_zero_undef/cttz_zero_undef for these cases before we ever get to operation legalization where the cmov is created. But wanted to add these tests so we don't regress. llvm-svn: 324409
* [x86] add tests to show demanded bits shortcoming; NFCSanjay Patel2018-02-061-0/+42
| | | | llvm-svn: 324408
* [AArch64] add test to show sub-optimal isel; NFCSanjay Patel2018-02-061-0/+17
| | | | llvm-svn: 324404
* [x86] add test to show missed BMI isel; NFCSanjay Patel2018-02-061-0/+15
| | | | llvm-svn: 324403
* [DWARFv5] Emit .debug_line_str (in a non-DWO file).Paul Robinson2018-02-061-6/+13
| | | | | | | | This should enable the linker to do string-pooling of path names. Differential Revision: https://reviews.llvm.org/D42707 llvm-svn: 324393
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-061-0/+35
| | | | llvm-svn: 324391
* [SLP] Update test checks, NFC.Alexey Bataev2018-02-063-64/+1127
| | | | llvm-svn: 324387
* [Hexagon] Don't form new-value jumps from floating-point instructionsKrzysztof Parzyszek2018-02-061-0/+19
| | | | | | | Additionally, verify that the register defined by the producer is a 32-bit register. llvm-svn: 324381
* [InstCombine][ValueTracking] Match non-uniform constant power-of-two vectorsSimon Pilgrim2018-02-061-1/+1
| | | | | | | | Generalize existing constant matching to work with non-uniform constant vectors as well. Differential Revision: https://reviews.llvm.org/D42818 llvm-svn: 324369
* [X86] Auto-generate checks. NFCCraig Topper2018-02-061-102/+121
| | | | llvm-svn: 324367
* [ARM] f16 conversionsSjoerd Meijer2018-02-061-0/+45
| | | | | | | | | This is a follow up of r324321, adding f16 <-> f32 and f16 <-> f64 conversion match patterns. Differential Revision: https://reviews.llvm.org/D42954 llvm-svn: 324360
* [DAG, X86] Improve Dependency analysis when doing multi-nodeNirav Dave2018-02-0615-738/+496
| | | | | | | | | | | | | | | | | | | | Instruction Selection Cleanup cycle/validity checks in ISel (IsLegalToFold, HandleMergeInputChains) and X86 (isFusableLoadOpStore). Now do a full search for cycles / dependencies pruning the search when topological property of NodeId allows. As part of this propogate the NodeId-based cutoffs to narrow hasPreprocessorHelper searches. Reviewers: craig.topper, bogner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41293 llvm-svn: 324359
* Regenerate vector-urem test. NFCI.Simon Pilgrim2018-02-061-2/+2
| | | | llvm-svn: 324357
* AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALUMarek Olsak2018-02-061-0/+34
| | | | | | | | Author: Bas Nieuwenhuizen https://reviews.llvm.org/D42881 llvm-svn: 324353
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-063-0/+77
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-062-60/+30
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [X86][SSE] Add PACKUS support for truncation of clamped valuesSimon Pilgrim2018-02-061-48/+7
| | | | | | Followup to D42544 that matches PACKUSWB cases for non-AVX512, SSE and PACKUSDW cases will have to wait until we can add support for general SMIN/SMAX matching. llvm-svn: 324347
* [AMDGPU] do not generate .AMDGPU.config for amdpal os typeTim Renouf2018-02-061-2/+2
| | | | | | | | | | | | | | | Summary: Now we generate PAL metadata for the amdpal os type, there is no need to generate the .AMDGPU.config section. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D37760 Change-Id: I303c5fad66656ce97293da60621afac6595b4c18 llvm-svn: 324346
* [AArch64][SVE] Asm: Add AND_ZI instructions and aliasesSander de Smalen2018-02-062-0/+108
| | | | | | | | | | | | | | Summary: Adds support for the SVE AND instruction with vector and logical-immediate operands, and their corresponding aliases. Reviewers: fhahn, rengolin, samparker, echristo, aadg, kristof.beyls Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, llvm-commits Differential Revision: https://reviews.llvm.org/D42295 llvm-svn: 324343
* [MergeICmps] Handle chains with several complex BCE basic blocks.Clement Courbet2018-02-061-0/+58
| | | | | | | | | | - Fix condition for detecting that a complex basic block was the first in the chain. - Add tests. This was caught by buildbots when submitting rL324319. llvm-svn: 324341
* [X86][SSE] Add PACKSS support for truncation of clamped valuesSimon Pilgrim2018-02-061-47/+7
| | | | | | Followup to D42544 that matches PACKSSWB cases for non-AVX512, SSE and PACKSSDW cases will have to wait until we can add support for general SMIN/SMAX matching. llvm-svn: 324339
* [AArch64] Fix spelling of ICH_ELRSR_EL2 system registerOliver Stannard2018-02-062-3/+3
| | | | | | | This register was mis-spelled as ICH_ELSR_EL2, but has the correct encoding for ICH_ELRSR_EL2. llvm-svn: 324325
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-066-0/+30
| | | | | | | | | | | | | | | This adds the CSDB instruction, which is a new barrier instruction described by the whitepaper at [1]. This is in encoding space which was previously executed as a NOP, so it is available for all targets that have the relevant NOP encoding space. This matches the binutils behaviour for these instructions [2][3]. [1] https://developer.arm.com/support/security-update [2] https://sourceware.org/ml/binutils/2018-01/msg00116.html [3] https://sourceware.org/ml/binutils/2018-01/msg00120.html llvm-svn: 324324
* [ARM] Armv8.2-A FP16 code generation (part 3/3)Sjoerd Meijer2018-02-061-8/+566
| | | | | | | | | | | | | | | This adds most of the FP16 codegen support, but these areas need further work: - FP16 literals and immediates are not properly supported yet (e.g. literal pool needs work), - Instructions that are generated from intrinsics (e.g. vabs) haven't been added. This will be addressed in follow-up patches. Differential Revision: https://reviews.llvm.org/D42849 llvm-svn: 324321
* Revert "[MergeICmps] Enable the MergeICmps Pass by default."Clement Courbet2018-02-063-16/+41
| | | | | | | | Breaks clang-ppc64be-linux-multistage buildbot. This reverts commit 515bab711f308c2e8299c49dd8c84ea6a2e0b60e. llvm-svn: 324319
* [MergeICmps] Enable the MergeICmps Pass by default.Clement Courbet2018-02-063-41/+16
| | | | | | | | | | | | Summary: Now that PR33325 is fixed, this should always improve the generated code. Reviewers: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42793 llvm-svn: 324317
* [ThinLTO] fix test failure without x86 backendHiroshi Inoue2018-02-062-0/+3
| | | | | | This patch moves ThinLTOBitcodeWriter/module-asm.ll test case into x86 directory to avoid a test failure when x86 backend is not enabled. llvm-svn: 324316
* [X86] Modify a few tests to not use icmps that are provably false.Craig Topper2018-02-063-17/+15
| | | | | | | | These used things like unsigned less than zero, which is always false because there is no unsigned number less than zero. I plan to teach DAG combine to optimize these so need to stop using them. llvm-svn: 324315
* AMDGPU/MemoryModel: Fix monotonic atomic loadsKonstantin Zhuravlyov2018-02-061-2/+2
| | | | | | Those should have glc bit set for system and agent synchronization scopes llvm-svn: 324314
* ThinLTOBitcodeWriter: Do not include module-level inline asm in the merged ↵Peter Collingbourne2018-02-061-0/+12
| | | | | | | | | | | module. If the inline asm provides the definition of a symbol, this can result in duplicate symbol errors. Differential Revision: https://reviews.llvm.org/D42944 llvm-svn: 324313
* [WebAssembly] Fix test expectations after r324274Derek Schuff2018-02-062-80/+33
| | | | | | | Wasm uses the expand action for several FP compare ops, and that behavior changed. llvm-svn: 324305
* Update test expectations after reverting PLT changeReid Kleckner2018-02-062-15/+15
| | | | llvm-svn: 324304
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-062-0/+29
| | | | llvm-svn: 324303
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