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* [llvm-rc] Add support for parsing memory flagsMartin Storsjo2018-05-154-0/+401
| | | | | | | | | | | | | | | | | | | | | | | | Most of the handling is pretty straightforward; fetch the default memory flags for the specific resource type before parsing the flags and apply them on top of that, except that some flags imply others and some flags clear more than one flag. For icons and cursors, the flags set get passed on to all individual single icon/cursor resources, while only some flags affect the icon/cursor group resource. For stringtables, the behaviour is pretty simple; the first stringtable resource of a bundle sets the flags for the whole bundle. The output of these tests match rc.exe byte for byte. The actual use of these memory flags is deprecated and they have no effect since Win16, but some resource script files may still happen to have them in place. Differential Revision: https://reviews.llvm.org/D46818 llvm-svn: 332329
* [llvm-rc] Read the Planes/BitCount fields from BITMAPINFOHEADER for iconsMartin Storsjo2018-05-151-1/+1
| | | | | | | | | | | | | | | | Previously these fields were only read from this header for cursors, while Planes was hardcoded to 1 for icons (with a comment that it was unknown why this was needed) and BitCount was left at the value read originally in the RESDIRENTRY. This fixes the single byte that was differing for the icon/cursor test compared to rc.exe. This is based on research/testing by Nico Weber. Differential Revision: https://reviews.llvm.org/D46816 llvm-svn: 332328
* [X86] Add fast isel tests for some of the avx512 truncate intrinsics to ↵Craig Topper2018-05-154-0/+451
| | | | | | match current clang codegen. llvm-svn: 332326
* [Debugify] Add -debugify-each for testing each pass in a pipelineVedant Kumar2018-05-153-11/+35
| | | | | | | | | | | | | | | | This adds a -debugify-each mode to opt which, when enabled, wraps each {Module,Function}Pass in a pipeline with logic to add, check, and strip synthetic debug info for testing purposes. This mode can be used to test complex pipelines for debug info bugs, or to collect statistics about the number of debug values & locations lost throughout various stages of a pipeline. Patch by Son Tuan Vu! Differential Revision: https://reviews.llvm.org/D46525 llvm-svn: 332312
* [InstCombine] fix crash due to ignored addrspacecastKeno Fischer2018-05-141-0/+19
| | | | | | | | | | | | | | | | | | Summary: Part of the InstCombine code for simplifying GEPs looks through addrspacecasts. However, this was done by updating a variable also used by the next transformation, for marking GEPs as inbounds. This led to replacing a GEP with a similar instruction in a different addrspace, which caused an assertion failure in RAUW. This caused julia issue https://github.com/JuliaLang/julia/issues/27055 Patch by Jeff Bezanson <jeff@juliacomputing.com> Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D46722 llvm-svn: 332302
* [AArch64] enhance test to show FMF loss; NFCSanjay Patel2018-05-141-1/+2
| | | | llvm-svn: 332301
* [ARM] Back up R4 and LR if calling the stack probe functionMartin Storsjo2018-05-141-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D46777 llvm-svn: 332298
* [llvm-rc] Add missing inputs for tag-icon-cursor.test.Martin Storsjo2018-05-147-28/+2
| | | | | | | | | | | | | | This adds the missing input files used for this test, except for the separate input files for specific error cases; matching test input files were provided by Nico Weber. The extra copying of files into the %t directory doesn't seem to be necessary since that directory only ever is used for output here, not for inputs. Differential Revision: https://reviews.llvm.org/D46813 llvm-svn: 332297
* [CodeView] Improve debugging of virtual base class member variablesBrock Wyma2018-05-141-91/+156
| | | | | | | | Initial support for passing the virtual base pointer offset to CodeViewDebug. https://reviews.llvm.org/D46271 llvm-svn: 332296
* [PowerPC] add more tests for FMF propagation; NFCSanjay Patel2018-05-141-2/+84
| | | | llvm-svn: 332295
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-0/+23
| | | | llvm-svn: 332285
* Hexagon: Put relocations after instructions not packets.Sid Manning2018-05-143-3/+18
| | | | | | | | | | | | | Change relocation output so that relocation information follows individual instructions rather than clustering them at the end of packets. This change required shifting block of code but the actual change is in HexagonPrettyPrinter's PrintInst. Differential Revision: https://reviews.llvm.org/D46728 llvm-svn: 332283
* [X86] Remove and autoupgrade avx512.vbroadcast.ss/avx512.vbroadcast.sd ↵Craig Topper2018-05-142-20/+20
| | | | | | intrinsics. llvm-svn: 332271
* [llvm-mca][X86] Add missing SSE4A test fileSimon Pilgrim2018-05-141-0/+55
| | | | llvm-svn: 332270
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-144-4/+4
| | | | | | MMX was missing and YMM was tagged as a fp nt store llvm-svn: 332269
* [BranchFolding] Allow hoisting to block with a single conditional branch.Geoff Berry2018-05-141-0/+29
| | | | | | | | | | | | | | | | | | | | | Summary: The BranchFolding pass is currently missing opportunities to hoist common code if the hoisted-to block contains a single conditional branch that has register uses. This occurs somewhat frequently on AArch64 with CBZ/TBZ opcodes. This change also eliminates some code differences when debug info is present since the presence of e.g. DBG_VALUE instructions in the hoisted-to block can enable hoisting that wouldn't have occurred without them. Reviewers: MatzeB, rnk, kparzysz, twoh, aprantl, javed.absar Subscribers: kristof.beyls, JDevlieghere, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46324 llvm-svn: 332265
* [llvm-mca][x86] Add scalar nt-store instruction testsSimon Pilgrim2018-05-149-9/+72
| | | | llvm-svn: 332262
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-143-7/+7
| | | | llvm-svn: 332260
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-1417-72/+223
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [llvm-mca][x86] Add and/not/or/xor instruction testsSimon Pilgrim2018-05-149-9/+2772
| | | | llvm-svn: 332257
* [AArch64] Improve single vector lane storesEvandro Menezes2018-05-144-2/+357
| | | | | | | | When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead. Differential revision: https://reviews.llvm.org/D46655 llvm-svn: 332251
* [CodeGen/AccelTable]: Handle -dwarf-linkage-names=Abstract correctlyPavel Labath2018-05-142-1/+89
| | | | | | | | | | | | | | | | | | | | Summary: If we are not emitting a linkage name in the .debug_info sections, we should not add it into the index either. This makes sure our index is consistent with the actual debug info. I am also explicitly setting the --dwarf-linkage-names=All in the name-collsions test as that one would now fail on targets where this defaults to "Abstract" (in fact, it would have failed already if there wasn't a bug in the DWARF verifier, which I fix as well). Reviewers: probinson, aprantl, JDevlieghere Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46748 llvm-svn: 332246
* [AggressiveInstCombine] avoid crashing on unsimplified code (PR37446)Sanjay Patel2018-05-141-0/+16
| | | | | | | | | This bug: https://bugs.llvm.org/show_bug.cgi?id=37446 ...raises another question: why do we run aggressive-instcombine before regular instcombine? llvm-svn: 332243
* [mips] Add missing test case from r332227Simon Dardis2018-05-141-0/+26
| | | | | | I did not commit this test from D46689. llvm-svn: 332241
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-143-6/+4
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* [LLVM-C] Add Bindings For Module FlagsRobert Widmann2018-05-141-0/+4
| | | | | | | | | | | | | | | | | | | Summary: The first foray into merging debug info into the echo tests. - Add bindings to Module::getModuleFlagsMetadata() in the form of LLVMCopyModuleFlagsMetadata - Add the opaque type LLVMModuleFlagEntry to represent Module::ModuleFlagEntry - Add accessors for LLVMModuleFlagEntry's behavior, key, and metadata node. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: aprantl, JDevlieghere, llvm-commits, harlanhaskins Differential Revision: https://reviews.llvm.org/D46792 llvm-svn: 332219
* Correct compatibility with the GNU Assembler's handling of comparison opsBill Wendling2018-05-143-11/+21
| | | | | | | | GAS returns -1 for a comparison operator if the result is true and 0 if false. https://www.sourceware.org/binutils/docs-2.12/as.info/Infix-Ops.html#Infix%20Ops llvm-svn: 332215
* [X86] Add fast isel test cases for the clang output for 512-bit cvtps2pd ↵Craig Topper2018-05-141-0/+92
| | | | | | related intrinsics. llvm-svn: 332214
* [X86] Remove and autoupgrade the cvtusi2sd intrinsic. Use ↵Craig Topper2018-05-142-11/+11
| | | | | | uitofp+insertelement instead. llvm-svn: 332206
* [X86] Add patterns for combining movss+uint_to_fp into the intrinsic ↵Craig Topper2018-05-131-12/+6
| | | | | | | | instructions under AVX512. This matches what we do for sint_to_fp. llvm-svn: 332205
* [X86] Add fast-isel test cases for _mm_cvtu32_sd, _mm_cvtu64_sd, ↵Craig Topper2018-05-131-0/+98
| | | | | | _mm_cvtu32_ss, and _mm_cvtu64_ss. llvm-svn: 332204
* [X86] Extend instcombine folds for pclmuldq intrinsics to the 256 and 512 ↵Craig Topper2018-05-131-0/+186
| | | | | | bit version. llvm-svn: 332202
* [X86] Add missing test for the InstCombines of pclmulqdq.Craig Topper2018-05-131-0/+80
| | | | | | Apparently this test was lost when r293151 was committed. It was present in the review, but not the commit. llvm-svn: 332199
* [X86] Remove and autoupgrade masked vpermd/vpermps intrinsics.Craig Topper2018-05-132-40/+40
| | | | llvm-svn: 332198
* Follow-up to rL332176 by adding a test case for PR37264.Dimitry Andric2018-05-131-0/+12
| | | | | | Noticed by Simon Pilgrim. llvm-svn: 332197
* AMDGPU: Make undef legal for v2i16/v2f16Matt Arsenault2018-05-131-4/+1
| | | | | | | This is apparently necessary to stop undef from being turned into a build_vector of 0s. llvm-svn: 332195
* [NFC] MIR-Canon: switching to a stable string sorting of instructions.Puyan Lotfi2018-05-131-3/+4
| | | | llvm-svn: 332191
* [X86] Add some load folding patterns for cvtsi2ss/sd into intrinsic ↵Craig Topper2018-05-131-1/+1
| | | | | | instructions. llvm-svn: 332189
* [X86] Remove some unused CHECK lines from tests.Craig Topper2018-05-132-12/+0
| | | | llvm-svn: 332188
* [X86] Remove an autoupgrade legacy cvtss2sd intrinsics.Craig Topper2018-05-133-85/+55
| | | | llvm-svn: 332187
* [X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what ↵Craig Topper2018-05-1211-149/+118
| | | | | | clang has used for a very long time. llvm-svn: 332186
* [X86] Remove some unused masked conversion intrinsics that can be replaced ↵Craig Topper2018-05-122-144/+144
| | | | | | | | with an older intrinsic and a select. This is what clang already uses. llvm-svn: 332170
* [AMDGPU] Fix amdgpu-waves-per-eu accounting in schedulerStanislav Mekhanoshin2018-05-121-0/+591
| | | | | | | | | | We cannot query this attribute from a subtarget given a machine function. At this point attribute itself is already unavailable and can only be obtained through MFI. Differential Revision: https://reviews.llvm.org/D46781 llvm-svn: 332166
* AMDGPU/GlobalISel: Implement select() for >32-bit G_STORETom Stellard2018-05-111-4/+19
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D46153 llvm-svn: 332154
* [CodeExtractor] Allow extracting blocks with exception handlingSergey Dmitriev2018-05-112-0/+108
| | | | | | | | | | | | | | | | | This is a CodeExtractor improvement which adds support for extracting blocks which have exception handling constructs if that is legal to do. CodeExtractor performs validation checks to ensure that extraction is legal when it finds invoke instructions or EH pads (landingpad, catchswitch, or cleanuppad) in blocks to be extracted. I have also added an option to allow extraction of blocks with alloca instructions, but no validation is done for allocas. CodeExtractor caller has to validate it himself before allowing alloca instructions to be extracted. By default allocas are still not allowed in extraction blocks. Differential Revision: https://reviews.llvm.org/D45904 llvm-svn: 332151
* AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.Changpeng Fang2018-05-111-0/+27
| | | | | | | | | | | | | Summary: We have no logic to promote alloca to vector for an AddrSpaceCast instruction. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D45993 llvm-svn: 332147
* [X86] Remove and autoupgrade a bunch of FMA instrinsics that are no longer ↵Craig Topper2018-05-113-257/+12
| | | | | | used by clang. llvm-svn: 332146
* [Split GEP] handle trunc() in separate-const-offset-from-gep pass.Artem Belevich2018-05-112-14/+35
| | | | | | | | | | | Let separate-const-offset-from-gep pass handle trunc() when it calculates constant offset relative to base. The pass itself may insert trunc() instructions when it canonicalises array indices to pointer-size integers and needs to handle trunc() in order to evaluate the offset. Differential Revision: https://reviews.llvm.org/D46732 llvm-svn: 332142
* [AMDGPU] Fix compilation failure when IR contains comdatYaxun Liu2018-05-111-0/+19
| | | | | | | | | | | | | | | | | Remove a useless SwitchSection which also causes compilation failure when IR contains comdat. The SwitchSection is useless because the current section is already correct text section for the function therefore no need to switch. It causes compilation failure for comdat because functions with comdat has specific text section, not the default .text section. Since HIP uses comdat, this bug caused failures for HIP. Differential Revision: https://reviews.llvm.org/D46770 llvm-svn: 332137
* [InstCombine] Handle atomic memset in the same way as regular memsetDaniel Neilson2018-05-111-5/+61
| | | | | | | | | | | | | | | | | | Summary: This change adds handling of the atomic memset intrinsic to the code path that simplifies the regular memset. In practice this means that we will now also expand a small constant-length atomic memset into a single unordered atomic store. Reviewers: apilipenko, skatkov, mkazantsev, anna, reames Reviewed By: reames Subscribers: reames, llvm-commits Differential Revision: https://reviews.llvm.org/D46660 llvm-svn: 332132
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