| Commit message (Collapse) | Author | Age | Files | Lines |
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backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
llvm-svn: 100233
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llvm-svn: 100208
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llvm-svn: 100199
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Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
llvm-svn: 100191
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it can't currently observe such changes automatically.
llvm-svn: 100186
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in particular, they end up aligning strings at 16-byte boundaries, and
there's no way for GlobalOpt to check OptForSize.
llvm-svn: 100172
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adding it to CSE hash table since copies aren't being considered for CSE and they may be deleted.
rdar://7819990
llvm-svn: 100170
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unaligned loads into aligned loads.
llvm-svn: 100166
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llvm-svn: 100165
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llvm-svn: 100160
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llvm-svn: 100137
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zero.
- Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type.
llvm-svn: 100118
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hosts / targets.
llvm-svn: 100101
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1. Makes it possible to lower with floating point loads and stores.
2. Avoid unaligned loads / stores unless it's fast.
3. Fix some memcpy lowering logic bug related to when to optimize a
load from constant string into a constant.
4. Adjust x86 memcpy lowering threshold to make it more sane.
5. Fix x86 target hook so it uses vector and floating point memory
ops more effectively.
rdar://7774704
llvm-svn: 100090
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MD used here isn't valid for !dbg.
llvm-svn: 100085
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llvm-svn: 100050
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llvm-svn: 100043
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llvm-svn: 99975
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llvm-svn: 99974
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llvm-svn: 99959
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llvm-svn: 99954
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llvm-svn: 99948
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llvm-svn: 99938
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memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.
llvm-svn: 99928
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Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.
llvm-svn: 99910
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to be fixed any time soon.
llvm-svn: 99888
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llvm-svn: 99853
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llvm-svn: 99840
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"the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions:
-in vararg handling, registers are marked to be live, to not confuse the register scavenger
-function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack."
llvm-svn: 99819
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llvm-svn: 99818
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transforming it into (add (i32 GPR), 4). This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align. This allows us to fold an extra load
in the changed testcase.
llvm-svn: 99756
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llvm-svn: 99752
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llvm-svn: 99751
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llvm-svn: 99707
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llvm-svn: 99620
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llvm-svn: 99598
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for fear of tying up a physical register.
llvm-svn: 99575
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Re-commit. This time complete with testsuite updates.
llvm-svn: 99570
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llvm-svn: 99546
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opcode values fitting in one byte (svn r99494).
llvm-svn: 99514
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If a TableGen class has an initializer expression containing an X.Y subexpression,
AND X depends on template parameters,
AND those template parameters have defaults,
AND some parameters with defaults are beyond position 1,
THEN parts of the initializer expression are evaluated prematurely with the default values when the first explicit template parameter is substituted, before the remaining explicit template parameters have been substituted.
llvm-svn: 99492
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llvm-svn: 99488
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happening.
Enhance scheduling to set the DEAD flag on implicit defs
more aggressively. Before, we'd set an implicit def operand
to dead if it were present in the SDNode corresponding to
the machineinstr but had no use. Now we do it in this case
AND if the implicit def does not exist in the SDNode at all.
This exposes a couple of problems: one is the FIXME, which
causes a live intervals crash on CodeGen/X86/sibcall.ll.
The second is that it makes machinecse and licm more
aggressive (which is a good thing) but also exposes a case
where licm hoists a set0 and then it doesn't get resunk.
Talking to codegen folks about both these issues, but I need
this patch in in the meantime.
llvm-svn: 99485
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instead of InlineFunction.
llvm-svn: 99483
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Fariborz please review and make sure this is what you meant.
llvm-svn: 99472
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address with a symbol address.
- This fixes the integrated-as nightly test regressions.
llvm-svn: 99466
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llvm-svn: 99451
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--- Reverse-merging r99440 into '.':
U test/MC/AsmParser/X86/x86_32-bit_cat.s
U test/MC/AsmParser/X86/x86_32-encoding.s
U include/llvm/IntrinsicsX86.td
U include/llvm/CodeGen/SelectionDAGNodes.h
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.h
llvm-svn: 99450
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llvm-svn: 99440
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not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
llvm-svn: 99435
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