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* [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168)Simon Pilgrim2018-02-171-0/+3
| | | | llvm-svn: 325435
* [AArch64] Implement dynamic stack probing for windowsMartin Storsjo2018-02-172-3/+27
| | | | | | | | | This makes sure that alloca() function calls properly probe the stack as needed. Differential Revision: https://reviews.llvm.org/D42356 llvm-svn: 325433
* [dwarfdump] Fix spurious verification errors for DW_AT_location attributesJonas Devlieghere2018-02-174-8/+292
| | | | | | | | | | | Verifying any DWARF file that is optimized and contains at least one tag with a DW_AT_location with a location list offset as a DW_AT_form_dataXXX results in dwarfdump spuriously claiming that the location list is invalid. Differential revision: https://reviews.llvm.org/D40199 llvm-svn: 325430
* [DebugInfo] Removed assert on missing CountVarDIESander de Smalen2018-02-172-0/+48
| | | | | | | | | | | | | | | | | | | | Summary: The assert for a DISubrange's CountVarDIE to be available fails when the dbg.value() has been optimized away for any reason. Having the assert for that is a little heavy, so instead removing it now in favor of not generating the 'count' expression. Addresses http://llvm.org/PR36263 . Reviewers: aprantl, dblaikie, probinson Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits, dstenb Differential Revision: https://reviews.llvm.org/D43387 llvm-svn: 325427
* [AMDGPU] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-173-12/+12
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Stanislav Mekhanoshin, Tom Stellard. llvm-svn: 325425
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-17116-811/+455
| | | | | | | | | | | | | | | | | This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
* [DAG, X86] Revert r324797, r324491, and r324359.Chandler Carruth2018-02-1715-496/+738
| | | | | | | | | | | | Sadly, r324359 caused at least PR36312. There is a patch out for review but it seems to be taking a bit and we've already had these crashers in tree for too long. We're hitting this PR in real code now and are blocked on shipping new compilers as a consequence so I'm reverting us back to green. Sorry for the churn due to the stacked changes that I had to revert. =/ llvm-svn: 325420
* [InstSimplify] add vector select tests with undef elts in condition; NFCSanjay Patel2018-02-171-0/+20
| | | | llvm-svn: 325419
* [X86] Turn selects with constant condition into vector shuffles during DAG ↵Craig Topper2018-02-173-47/+44
| | | | | | | | | | | | | | | | | | | | | | | combine Summary: Currently we convert to shuffles during lowering. This moves it to DAG combine so hopefully we can get it done before type legalization has to extend the condition. I believe in some cases we're creating SHRUNKBLENDs that end up with constant conditions because we see the extended on the condition and think its a dynamic selelect before DAG combine gets a chance to constant fold the extend. We could add combines to turn SHRUNKBLENDs with constant condition back to vselect. But it seemed like it might be better to just send them to shuffles as early as possible so they never get a chance to become SHRUNKBLENDs. This the reason some tests went from blends controlled by a constant pool load to just move. Some of the constant pool entries changed because the sign_extend introduced by type legalization turned undef elements in select condition into 0s. While the select->shuffle used -1 in the shuffle mask. So now the shuffle lowering can do what it wants with them. I'll remove the lowering code as a follow up. We might be able to simplify some of the pre-checks for SHRUNKBLEND as the FIXME there says. Reviewers: spatel, RKSimon, efriedma, zvi, andreadb Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43367 llvm-svn: 325417
* [ThinLTO] Allow indexing to request backend to ignore the moduleVitaly Buka2018-02-161-0/+18
| | | | | | | | | | | | | | | | | | Summary: Gold plugin does not add pass to ThinLTO modules without useful symbols. In this case ThinLTO can't create corresponding index file and some features, like CFI, cannot be processes by backed correctly without index. Given that we don't need the backed output we can request it to avoid processing the module. This is implemented by this patch using new "SkipModuleByDistributedBackend" flag. Reviewers: pcc, tejohnson Subscribers: mehdi_amini, inglorion, eraman, cfe-commits Differential Revision: https://reviews.llvm.org/D42995 llvm-svn: 325411
* Run these tests, the errors were old and not valid anymore.Eric Christopher2018-02-161-11/+8
| | | | llvm-svn: 325407
* [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAGAditya Nandakumar2018-02-162-316/+343
| | | | | | | | | | | | This patch changes GlobalISelEmitter to rank patterns similar to how the DAG does it (ie it computes a score for a pattern and adds the added complexity to it). This is so that the decision tree for GISelSelector remains compatible with that of SelectionDAG. https://reviews.llvm.org/D43270 llvm-svn: 325401
* AMDGPU: Bring elf flags in sync with the specKonstantin Zhuravlyov2018-02-1611-185/+679
| | | | | | | | | | | - Add MACH flags - Add XNACK flag - Add reserved flags - Minor cleanups in docs Differential Revision: https://reviews.llvm.org/D43356 llvm-svn: 325399
* AMDGPU: Bring processors and features in sync with the specKonstantin Zhuravlyov2018-02-1611-54/+52
| | | | | | | | | | - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
* [AArch64] Fix BITCAST lowering crashEvandro Menezes2018-02-161-0/+28
| | | | | | | | | | | The data type is assumed to be a vector, but sometimes it is not, leading to an assertion. Add simple test-case to verify this. Differential revision: https://reviews.llvm.org/D42599 llvm-svn: 325378
* AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elementsChangpeng Fang2018-02-167-27/+29
| | | | | | | | | | | | | | Summary: This patch extends the promotion of alloca to vector to the arrays of up to 16 elements. Also we introduce an option, -disable-promote-alloca-to-vector, to switch promotion to vector off, if needed. Reviewers: arsenm Differential Revision: https://reviews.llvm.org/D33559 llvm-svn: 325372
* [X86] Only reorder srl/and on last DAG combiner runCraig Topper2018-02-164-28/+33
| | | | | | | | | | This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
* [WebAssembly] MC: Make explicit our current lack of support for relocations ↵Sam Clegg2018-02-161-0/+15
| | | | | | | | | | | | against unnamed temporary symbols. Add an explicit check before looking up symbol in SymbolIndices. This was previously silently succeeding and returning zero for such unnamed temporaries. Differential Revision: https://reviews.llvm.org/D43365 llvm-svn: 325367
* [InstCombine] add FMF to better show current fdiv fold behavior; NFCSanjay Patel2018-02-161-4/+4
| | | | llvm-svn: 325365
* [ThinLTO] Fix data race in test #2Eugene Leviant2018-02-161-1/+1
| | | | | | Switched to the right option (-thinlto-threads) llvm-svn: 325362
* [ThinLTO] Fix data race in testEugene Leviant2018-02-161-1/+1
| | | | llvm-svn: 325361
* [JumpThreading] PR36133 enable/disable DominatorTree for LVI analysisBrian M. Rzycki2018-02-161-0/+44
| | | | | | | | | | | | | | | | | | | | | | Summary: The LazyValueInfo pass caches a copy of the DominatorTree when available. Whenever there are pending DominatorTree updates within JumpThreading's DeferredDominance object we cannot use the cached DT for LVI analysis. This commit adds the new methods enableDT() and disableDT() to LVI. JumpThreading also sets the appropriate usage model before calling LVI analysis methods. Fixes https://bugs.llvm.org/show_bug.cgi?id=36133 Reviewers: sebpop, dberlin, kuhar Reviewed by: sebpop, kuhar Subscribers: uabelho, llvm-commits, aprantl, hiraditya, a.elovikov Differential Revision: https://reviews.llvm.org/D42717 llvm-svn: 325356
* AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested ↵Changpeng Fang2018-02-161-39/+23
| | | | | | | | | | | | | | | | | | instruction. Summary: In the current implementation of GPR Indexing Mode when the index is of non-uniform, the s_set_gpr_idx_off instruction is incorrectly inserted after the loop. This will lead the instructions with vgpr operands (v_readfirstlane for example) to read incorrect vgpr. In this patch, we fix the issue by inserting s_set_gpr_idx_on/off immediately around the interested instruction. Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D43297 llvm-svn: 325355
* [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying ↵Simon Pilgrim2018-02-163-55/+31
| | | | | | | | | | shuffle masks Based off the DemandedElts mask the and UNDEF elements returned from the SimplifyDemandedVectorElts calls to the shuffle operands, we can attempt to simplify the shuffle mask. I had to be very conservative here as accepting post-legalized shuffle masks could cause problems for targets that legalize UNDEF mask elements back to inrange values (PowerPC), similarly combining to identity shuffle masks could cause too much UNDEF information to disappear for later combines. llvm-svn: 325354
* [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles ↵Simon Pilgrim2018-02-165-43/+26
| | | | | | and the root started as a float domain shuffle llvm-svn: 325349
* [mips] Remove codegen support from some 16 bit instructionsSimon Dardis2018-02-166-319/+266
| | | | | | | | | | | | These instructions conflict with their full length variants for the purposes of FastISel as they cannot be distingushed based on the number and type of operands and predicates. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41285 llvm-svn: 325341
* [SelectionDAG] Add initial SimplifyDemandedVectorElts support for ↵Simon Pilgrim2018-02-161-4/+0
| | | | | | | | simplifying VSELECT operands This just adds a basic pass through - we can add constant selection mask handling in a future patch to fully match InstCombine. llvm-svn: 325338
* [Transforms] Propagate TBAA info in SROAIvan A. Kosarev2018-02-161-151/+274
| | | | | | | | | | | | | | | Now that we have the new TBAA metadata format that is capable of representing accesses to aggregates, we can propagate TBAA access tags from memory setting and transferring intrinsics to load and store instructions and vice versa. Since SROA produces lots of new loads and stores on optimized builds, this change significantly decreases the share of undecorated memory accesses on such builds. Differential Revision: https://reviews.llvm.org/D41563 llvm-svn: 325329
* [ARM] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-167-147/+144
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
* [LegalizeDAG] Fix legalization of SETCCMikhail Maltsev2018-02-161-0/+23
| | | | | | | | | | | | | | | | | | | Summary: Currently when expanding a SETCC node into a SELECT_CC, LLVM uses an incorrect type for determining BooleanContent of the result. This patch fixes the issue. Fixes PR36079. Reviewers: rogfer01, javed.absar, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D43282 llvm-svn: 325325
* [ARM] Materialise some boolean values to avoid a branchRoger Ferrer Ibanez2018-02-1620-713/+840
| | | | | | | | | | | | | This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
* [ThinLTO] Import global variablesEugene Leviant2018-02-163-2/+38
| | | | | | Differential revision: https://reviews.llvm.org/D43077 llvm-svn: 325320
* [X86] Allow CMOVs of constants to be sign extended from i32.Craig Topper2018-02-162-19/+13
| | | | | | Sign extending i32 constants only requires a REX prefix as does widening the CMOV. This is cheaper than the explicit sign extend op. llvm-svn: 325318
* [X86] Don't zero_extend cmov up to i64, stop at i32.Craig Topper2018-02-161-1/+1
| | | | | | Zero extend from i32 to i64 is free. So extend from i16 to i32, and then use a free zero extend to finish. llvm-svn: 325317
* Remove brittle check lines from a test, NFCVedant Kumar2018-02-161-41/+0
| | | | llvm-svn: 325310
* [GVN] Partially revert debug info salvage change (r325063)Vedant Kumar2018-02-161-1/+1
| | | | | | | | | | | | | In r325063, we salvaged debug values from dying instructions in GVN::processBlock() and GVN::performScalarPRE(). The change in performScalarPRE(), while correct, is unhelpful. It introduced a call to salvageDebugInfo() which was immediately followed by a RAUW, meaning it prevented the RAUW from efficiently updating dbg.value intrinsics. This commit reverts the mistake and tightens up the affected test case. llvm-svn: 325308
* [X86] Add the test cases that were supposed to go with r325287.Craig Topper2018-02-161-0/+242
| | | | llvm-svn: 325306
* Allow 0 to be a valid value pruning interval in C LTO API. Value 0 will ↵Ekaterina Romanova2018-02-151-0/+21
| | | | | | cause garbage collector to run. This matches the behavior in C++ LTO API. llvm-svn: 325303
* [DCE] Salvage debug info from dead instsVedant Kumar2018-02-151-4/+8
| | | | | | | This results in small increases in the size of the .debug_loc section and the number of unique source variables in a stage2 build of opt. llvm-svn: 325301
* [AMDGPU] Combine adjacent waitcounts in a single strongest waitStanislav Mekhanoshin2018-02-151-2/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D43350 llvm-svn: 325299
* [Debugify] Don't check functions which were skippedVedant Kumar2018-02-151-0/+4
| | | | | | | If no debug info was applied to a function, its debug info shouldn't be checked (it doesn't have any :). llvm-svn: 325297
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-151-0/+76
| | | | | | | | | | | | | | | | | | | Summary: This patch makes the decoder understand old AMD 3DNow! instructions that have never been properly supported in the X86 disassembler, despite being supported in other subsystems. Hopefully this should make the X86 decoder more complete with respect to binaries containing legacy code. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits, maksfb, bruno Differential Revision: https://reviews.llvm.org/D43311 llvm-svn: 325295
* [opt] Port the debugify passes to the new pass managerVedant Kumar2018-02-151-0/+7
| | | | llvm-svn: 325294
* [X86] Enable BT to be used in place of TEST for single bit checks under optsizeCraig Topper2018-02-151-6/+6
| | | | | | | | We already do this for 64-bit when it won't fit into a 64-bit AND/TEST's immediate field. This adds an additional qualifier to do it for any single bit constant larger than 8-bits under optsize Differential Revision: https://reviews.llvm.org/D43346 llvm-svn: 325290
* [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and ↵Craig Topper2018-02-151-3/+4
| | | | | | | | | | | | | | (zextload)) even when the and does not have multiple uses Same for the sign extend case. Currently we check for multiple uses on the binop. Then we call ExtendUsesToFormExtLoad to capture SetCCs that use the load. So we only end up finding any setccs when the and has additional uses and the load is used by a setcc. I don't think the and having multiple uses is relevant here. I think we should only be checking for the load having multiple uses. This changes an NVPTX test because we now find that the load has a second use by a truncate, but ExtendUsesToFormExtLoad only looks at setccs it can extend. All other operations just check isTruncateFree. Maybe we should allow widening of an existing truncate even if its not free? Differential Revision: https://reviews.llvm.org/D43063 llvm-svn: 325289
* [Coroutines] Don't move stores for allocator argsBrian Gesiak2018-02-151-0/+64
| | | | | | | | | | | | | | | | | | | | | Summary: The behavior described in Coroutines TS `[dcl.fct.def.coroutine]/7` allows coroutine parameters to be passed into allocator functions. The instructions to store values into the alloca'd parameters must not be moved past the frame allocation, otherwise uninitialized values are passed to the allocator. Test Plan: `check-llvm` Reviewers: rsmith, GorNishanov, eric_niebler Reviewed By: GorNishanov Subscribers: compnerd, EricWF, llvm-commits Differential Revision: https://reviews.llvm.org/D43000 llvm-svn: 325285
* [ARM] Fix redirect in inline assembly testPablo Barrio2018-02-151-1/+1
| | | | | | | | | | | | Summary: Fix silly mistake in a test Reviewers: gkistanova, apilipenko Subscribers: javed.absar, eraman, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D43342 llvm-svn: 325283
* [SCCP] Test that constant propagation updates debug info, NFCVedant Kumar2018-02-151-5/+17
| | | | | | | This extends an existing test to check that SCCP updates the operands of relevant dbg.value instructions as it does its work. llvm-svn: 325281
* [X86] Add test cases for opportunities for using BT instead of TEST under ↵Craig Topper2018-02-151-0/+372
| | | | | | optsize. llvm-svn: 325277
* [X86][SSE] Add saturated truncation tests for storing illegal v8i8 typesSimon Pilgrim2018-02-153-0/+1605
| | | | | | Tests showing missing opportunities to use PACK instructions in cases where we need to truncate to illegal types for stores llvm-svn: 325270
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