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* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-272-0/+32
| | | | llvm-svn: 191496
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-271-0/+137
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 llvm-svn: 191495
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-272-0/+5
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* Revert "llvm-objdump: Dump COFF import table if -private-headers option is ↵Rui Ueyama2013-09-2710-128/+125
| | | | | | | | given." This reverts commit r191472 because it's failing on BE machine. llvm-svn: 191480
* llvm-objdump: Dump COFF import table if -private-headers option is given.Rui Ueyama2013-09-2710-125/+128
| | | | | | | | | | | | | | | | This is a patch to add capability to llvm-objdump to dump COFF Import Table entries, so that we can write tests for LLD checking Import Table contents. llvm-objdump did not print anything but just file name if the format is COFF and -private-headers option is given. This is a patch adds capability for dumping DLL Import Table, which is specific to the COFF format. In this patch I defined a new iterator to iterate over import table entries. Also added a few functions to COFFObjectFile.cpp to access fields of the entry. Differential Revision: http://llvm-reviews.chandlerc.com/D1719 llvm-svn: 191472
* MCParser/Debug info: Accept line number 0 as a legitimate value, sinceAdrian Prantl2013-09-261-0/+1
| | | | | | | | CFE produces it to indicate artificial locations. c.f.: DWARF standard, Table 6.2: line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line. llvm-svn: 191471
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-261-0/+252
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+22
| | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. llvm-svn: 191441
* [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.Bill Schmidt2013-09-261-0/+39
| | | | | | | | When generating code for shared libraries, even local calls may be intercepted, so we need a nop after the call for the linker to fix up the TOC. Test case adapted from the one provided in PR17354. llvm-svn: 191440
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-261-181/+0
| | | | llvm-svn: 191438
* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-261-0/+112
| | | | llvm-svn: 191432
* Implements parsing and emitting of .cfi_window_save in MC.Venkatraman Govindaraju2013-09-262-0/+66
| | | | llvm-svn: 191431
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-262-15/+1345
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-261-1/+4
| | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. llvm-svn: 191426
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-261-4/+8
| | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. llvm-svn: 191419
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+720
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-251-0/+90
| | | | | | Patch by Matheus Almeida llvm-svn: 191413
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+12
| | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+11
| | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. llvm-svn: 191410
* Unify pubsection/gnu pubsection printing.Eric Christopher2013-09-251-7/+8
| | | | llvm-svn: 191407
* Test commit. Removed trailing whitespace.Josh Magee2013-09-251-1/+1
| | | | llvm-svn: 191402
* Fix a bad typo in the inline assembly code for mips16 pic fp stubsReed Kotler2013-09-252-12/+33
| | | | | | | and make one cosmetic cleanup to make it look the same as gcc in this area; adjusting test cases. llvm-svn: 191400
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-251-0/+181
| | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. llvm-svn: 191393
* SLPVectorize: Put horizontal reductions feeding a store under separate flagArnold Schwaighofer2013-09-251-8/+10
| | | | | | | Put them under a separate flag for experimentation. They are more likely to interfere with loop vectorization which happens later in the pass pipeline. llvm-svn: 191371
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-251-0/+5
| | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. llvm-svn: 191368
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-251-0/+38
| | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. llvm-svn: 191349
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-253-5/+5
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
* Move LTO support library to a component, allowing it to be testedPeter Collingbourne2013-09-242-0/+0
| | | | | | more reliably across platforms. Patch by Tom Roeder! llvm-svn: 191343
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+18
| | | | | | PR17338. llvm-svn: 191337
* llvm-dwarfdump support for gnu_pubtypesDavid Blaikie2013-09-241-3/+15
| | | | llvm-svn: 191329
* Test case for r191314. Yi Jiang2013-09-241-0/+27
| | | | | | Some supplemental information for r191314: We would like to make sure SLP Vectorizer will not try to vectorize tiny trees even with a negative threshold so we set the cost to INT_MAX. llvm-svn: 191327
* Verify that we don't optimize null return checks to the nothrow_t version of ↵Benjamin Kramer2013-09-241-0/+23
| | | | | | operator new. llvm-svn: 191325
* Make the size and expr arguments of .fill directive optional.Roman Divacky2013-09-241-0/+16
| | | | llvm-svn: 191318
* MemoryBuiltins: Reinstate optimizing (uninitialized) loads from operator new.Benjamin Kramer2013-09-241-3/+28
| | | | llvm-svn: 191315
* MemoryBuiltins: Fix operator new bits.Benjamin Kramer2013-09-241-0/+20
| | | | | | We really don't want to optimize malloc return value checks away. llvm-svn: 191313
* Teach MemoryBuiltins and InstructionSimplify that operator new never returns ↵Benjamin Kramer2013-09-241-0/+20
| | | | | | | | | | | | NULL. This is safe per C++11 18.6.1.1p3: [operator new returns] a non-null pointer to suitably aligned storage (3.7.4), or else throw a bad_alloc exception. This requirement is binding on a replacement version of this function. Brings us a tiny bit closer to eliminating more vector push_backs. llvm-svn: 191310
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+132
| | | | | | not intrinsics) llvm-svn: 191306
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-241-0/+262
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191304
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-8/+51
| | | | llvm-svn: 191302
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-242-12/+336
| | | | llvm-svn: 191301
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-241-0/+110
| | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. llvm-svn: 191297
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+30
| | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-241-0/+240
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191293
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-243-4/+1096
| | | | | | (i.e. not intrinsics) llvm-svn: 191291
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-244-7/+413
| | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
* [msan] Handling of atomic load/store, atomic rmw, cmpxchg.Evgeniy Stepanov2013-09-242-4/+193
| | | | llvm-svn: 191287
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-242-0/+1159
| | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-241-0/+168
| | | | | | (i.e. not intrinsics) llvm-svn: 191285
* llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, ↵NAKAMURA Takumi2013-09-241-1/+1
| | | | | | or aach64-pecoff might be misassumed on win32 hosts. llvm-svn: 191275
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