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* [AMDGPU] add LDS f32 intrinsicsDaniil Fukalov2018-01-171-0/+69
| | | | | | | | | | | | added llvm.amdgcn.atomic.{add|min|max}.f32 intrinsics to allow generate ds_{add|min|max}[_rtn]_f32 instructions needed for OpenCL float atomics in LDS Reviewed by: arsenm Differential Revision: https://reviews.llvm.org/D37985 llvm-svn: 322656
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-172-20/+349
| | | | | | | | | See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771 Differential Revision: https://reviews.llvm.org/D42058 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322655
* [ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNCDiana Picus2018-01-171-0/+79
| | | | | | | | | | | Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware support, but only for conversions between float and double. Also add the necessary boilerplate so that the LegalizerHelper can introduce the required libcalls. This also works only for float and double, but isn't too difficult to extend when the need arises. llvm-svn: 322651
* [Transforms] Support making mutable versions of new-format TBAA access tagsIvan A. Kosarev2018-01-171-7/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D41565 llvm-svn: 322650
* [X86] Don't mutate shuffle arguments after early-out for AVX512Benjamin Kramer2018-01-171-0/+40
| | | | | | | | | | The match* functions have the annoying behavior of modifying its inputs. Save and restore the inputs, just in case the early out for AVX512 is hit. This is still not great and its only a matter of time this kind of bug happens again, but I couldn't come up with a better pattern without rewriting significant chunks of this code. Fixes PR35977. llvm-svn: 322644
* Don't emit apple accelerator tables on non-darwin targetsPavel Labath2018-01-171-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently -glldb turns on emission of apple tables on all targets, but lldb is only really capable of consuming them on darwin. Furthermore, making lldb consume these tables is not straight-forward because of the differences in how the debug info is distributed on darwin vs. elf targets. The darwin debug model assumes that the debug info (along with accelerator tables) will either remain in the .o files or it will be linked into a dsym bundle by a linker that knows how to merge these tables. In the elf world, all present linkers will simply concatenate these accelerator tables into the shared object. Since the tables are not self-terminating, this renders the tables unusable, as the debugger cannot pry the individual tables apart anymore. It might theoretically be possible to make the tables work with split dwarf, as that is somewhat similar to the apple .o model, but unfortunately right now the combination of -glldb and -gsplit-dwarf produces broken object files. Until these issues are resolved there is no point in emitting the apple tables for these targets. At best, it wastes space; at worst, it breaks compilation and prevents the user from getting other benefits of -glldb. Reviewers: probinson, aprantl, dblaikie Subscribers: emaste, dim, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D41986 llvm-svn: 322633
* Rewrite debugger tuning test case to not depend on apple sectionsPavel Labath2018-01-171-26/+40
| | | | | | | | | | | | | | | | | | | | | Summary: In a follow-up commit I'll change the rules for emission of accelerator tables, which means we won't be able to use them as a litmus test for the debugger tuning options. Instead of sections, I base the test on the presence/absence of some debug info attributes and opcodes: LLDB - prefers DW_OP_form_tls_address and uses DW_AT_APPLE_optimized GDB - prefers DW_OP_GNU_push_tls_address and does not use the optimized attribute SCE - prefers DW_OP_form_tls_address and does not use the optimized attribute Reviewers: probinson, aprantl, dblaikie Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41985 llvm-svn: 322630
* [X86][AVX] Add extra 'interleaved+lanepermute' shuffle testSimon Pilgrim2018-01-171-0/+51
| | | | | | Possible missed opportunity to use 64-bit lane permute on AVX1 in lowerShuffleAsRepeatedMaskAndLanePermute llvm-svn: 322628
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-172-2/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [MC] Fix -stack-size-section on ARMSean Eveson2018-01-171-0/+30
| | | | | | | | Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size. Differential Revision: https://reviews.llvm.org/D42108 llvm-svn: 322619
* [pdbutil] Replace 0 byte PDB input with correct version to fix failing unit testAaron Smith2018-01-171-0/+0
| | | | llvm-svn: 322614
* Fix pretty printing the unspecified param of a variadic functionAaron Smith2018-01-173-0/+74
| | | | | | | | | | | | | | | | | | | | | | | Summary: - Fix a bug in PrettyBuiltinDumper that returns "void" as the name for an unspecified builtin type. Since the unspecified param of a variadic function is considered a builtin of unspecified type in PDBs, we set "..." for its name. - Provide a method to determine if a PDBSymbolFunc is variadic in PrettyFunctionDumper since PDBSymbolFunc::getArgument() doesn't return the last unspecified-type param. - Add a pretty-func-dumper.test to test pretty dumping of variadic functions. Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41801 llvm-svn: 322608
* [hwasan] Rename sized load/store callbacks to be consistent with ASan.Evgeniy Stepanov2018-01-162-10/+10
| | | | | | | | | | | | Summary: __hwasan_load is now __hwasan_loadN. Reviewers: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D42138 llvm-svn: 322601
* [X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructionsSimon Pilgrim2018-01-162-4/+4
| | | | | | For some reason they don't have a trailing i like the packed equivalents. llvm-svn: 322600
* [CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.Florian Hahn2018-01-164-92/+92
| | | | | | | | | | | | | | | This removes some duplication from splitCallSite and makes it easier to add additional code dealing with each predecessor. It also allows us to split for more than 2 predecessors, although that is not enabled for now. Reviewers: junbuml, mcrosier, davidxl, davide Reviewed By: junbuml Differential Revision: https://reviews.llvm.org/D41858 llvm-svn: 322599
* [GlobalISel][TableGen] Add support for SDNodeXFormVolkan Keles2018-01-162-16/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
* [SLP] Fix for PR32164: Improve vectorization of reverse order of extract ↵Alexey Bataev2018-01-161-20/+16
| | | | | | | | | | | | | | operations. Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33954 llvm-svn: 322579
* [X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMXSimon Pilgrim2018-01-161-78/+48
| | | | llvm-svn: 322574
* [LiveDebugValues] update kill-after-spill test with target triplePetar Jovanovic2018-01-161-0/+1
| | | | | | Set target triple to "x86_64-unknown-linux-gnu". llvm-svn: 322568
* [LiveDebugValues] recognize spilled reg killed in instruction after spillPetar Jovanovic2018-01-161-0/+387
| | | | | | | | | | | Current condition for spill instruction recognition in LiveDebugValues does not recognize case when register is spilled and killed in next instruction. Patch by Nikola Prica. Differential Revision: https://reviews.llvm.org/D41226 llvm-svn: 322554
* [X86][MMX] Improve MMX constant generationSimon Pilgrim2018-01-162-23/+12
| | | | | | Extend the MMX zero code to take any constant with zero'd upper 32-bits llvm-svn: 322553
* [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC ↵Gadi Haber2018-01-1614-0/+16124
| | | | | | | | | | | | | | | encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC> NFC. Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. Started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D40879 Change-Id: I231a35861611bfd3d23c74cc59507373f021a629 llvm-svn: 322544
* [DebugInfo] Unify dumping of address rangesJonas Devlieghere2018-01-1647-211/+211
| | | | | | | | | | | | | | | Summary: This patch unifies the printing of address ranges as [0x0, 0x1). rdar://34822059 Reviewers: aprantl, dblaikie Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D42056 llvm-svn: 322543
* [X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>Gadi Haber2018-01-1611-0/+614
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover the XSAVE ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D41282 Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45 llvm-svn: 322537
* [FileCheck] - Fix possible buffer out of bounds access when parsing ↵George Rimar2018-01-161-0/+4
| | | | | | | | | | | | | | | | | | | --check-prefix. FileCheck tool crashes when trying to parse --check-prefix argument if there is no any data after it. For example test like following would crash if there are no symbols and no EOL mark after `boom`: # REQUIRES: x86 # RUN: <skipped few lines> # RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom Patch fixes the issue. Differential revision: https://reviews.llvm.org/D42057 llvm-svn: 322536
* [BPF] Teach DAG2DAG AND elimination about load intrinsicsYonghong Song2018-01-161-0/+58
| | | | | | | | | | | | | | | | | | As commented on the existing code: // The Reg operand should be a virtual register, which is defined // outside the current basic block. DAG combiner has done a pretty // good job in removing truncating inside a single basic block. However, when the Reg operand comes from bpf_load_[byte | half | word] intrinsics, the generic optimizer doesn't understand their results are zero extended, so these single basic block elimination opportunities were missed. Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> llvm-svn: 322534
* [SROA] fix assetion failureHiroshi Inoue2018-01-163-17/+83
| | | | | | | | | | | | | | This patch fixes the assertion failure in SROA reported in PR35657. PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522. The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert. In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets. This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices. Differential Revision: https://reviews.llvm.org/D41981 llvm-svn: 322533
* [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.Craig Topper2018-01-161-2/+2
| | | | | | Previously we encoded it as 0x48 0x90. llvm-svn: 322531
* [X86][MMX] Add support for MMX zero vector creationSimon Pilgrim2018-01-152-34/+22
| | | | | | | | | | As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register. This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well. Differential Revision: https://reviews.llvm.org/D41908 llvm-svn: 322525
* [X86][SSE] Add custom execution domain fixing for ↵Simon Pilgrim2018-01-1549-1156/+821
| | | | | | | | | | BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW. Differential Revision: https://reviews.llvm.org/D42042 llvm-svn: 322524
* [x86] add tests to show missed constant shrinking (PR35907); NFCSanjay Patel2018-01-151-4/+81
| | | | llvm-svn: 322523
* [x86] regenerate test checks; NFCSanjay Patel2018-01-151-7/+21
| | | | llvm-svn: 322522
* [x86] regenerate test checks; NFCSanjay Patel2018-01-151-127/+249
| | | | llvm-svn: 322521
* [x86] regenerate test checks; NFCSanjay Patel2018-01-151-4/+7
| | | | llvm-svn: 322519
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-153-37/+66
| | | | | | Differential Revision: https://reviews.llvm.org/D41617 llvm-svn: 322500
* [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectorsKrzysztof Parzyszek2018-01-152-0/+152
| | | | | | | The old implementation was not always correct. The new one recognizes more shuffles that match specific instructions. llvm-svn: 322498
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-151-0/+52
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322488
* Update BTVER2 sched numbers for some AVX instructions (xmm version).Andrew V. Tischenko2018-01-153-29/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D40067 llvm-svn: 322485
* Revert "[DAG] Elide overlapping stores"Benjamin Kramer2018-01-151-2/+3
| | | | | | | This reverts commit r322085. Internal PPC testing is still showing the same symptoms as when this patch landed the last time. llvm-svn: 322474
* [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV ↵Andrei Elovikov2018-01-151-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | from a trunc. Summary: This method is supposed to be called for IVs that have casts in their use-def chains that are completely ignored after vectorization under PSE. However, for truncates of such IVs the same InductionDescriptor is used during creation/widening of both original IV based on PHINode and new IV based on TruncInst. This leads to unintended second call to recordVectorLoopValueForInductionCast with a VectorLoopVal set to the newly created IV for a trunc and causes an assert due to attempt to store new information for already existing entry in the map. This is wrong and should not be done. Fixes PR35773. Reviewers: dorit, Ayal, mssimpso Reviewed By: dorit Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41913 llvm-svn: 322473
* [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 ↵Gadi Haber2018-01-152-0/+70464
| | | | | | | | | | | | | | | bits isa sets.<NFC> NFC. Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41172 Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39 llvm-svn: 322471
* [GlobalsAA] Don't let dbg intrinsics affect analysis resultMikael Holmen2018-01-151-0/+57
| | | | | | | | | | | | | | | | | | Summary: This fixes PR35899. Debug info intrinsics shouldn't affect code generation so ignore them in GlobalsAA. Reviewers: hfinkel, aprantl Reviewed By: aprantl Subscribers: aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D41984 llvm-svn: 322470
* [BasicAA] Stop crashing when dealing with pointers > 64 bits.Davide Italiano2018-01-151-0/+12
| | | | | | | | | | | | | | | An alternative (and probably better) fix would be that of making `Scale` an APInt, and there's a patch floating around to do this. As we're still discussing it, at least stop crashing in the meanwhile (added bonus, we now have a regression test for this situation). Fixes PR35843. Thanks to Eli for suggesting the fix and Simon for reporting and reducing the bug. llvm-svn: 322467
* [X86][SSE] Tag PR21137 test caseSimon Pilgrim2018-01-141-1/+2
| | | | | | The test was added ages ago, but we didn't comment where it came from. llvm-svn: 322465
* [X86] Add test cases for D41794.Craig Topper2018-01-142-0/+408
| | | | llvm-svn: 322464
* [X86][SSE] Add PR22391 test caseSimon Pilgrim2018-01-141-0/+45
| | | | llvm-svn: 322463
* [X86] Autoupgrade kunpck intrinsics using vector operations instead of ↵Craig Topper2018-01-144-72/+67
| | | | | | | | | | | | | | | | scalar operations Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free. Reviewers: spatel, RKSimon, zvi, jina.nahias Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42018 llvm-svn: 322462
* [X86] Regenerate fp128 testSimon Pilgrim2018-01-141-11/+18
| | | | llvm-svn: 322460
* [X86][SSE] Support combining MOVLHPS undef inputsSimon Pilgrim2018-01-141-2/+1
| | | | llvm-svn: 322459
* [X86][SSE] Add v2f64 3u shuffle testSimon Pilgrim2018-01-141-0/+14
| | | | | | Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask. llvm-svn: 322458
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