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* [WebAssembly][NFC] Add colon to label in testThomas Lively2018-09-041-1/+1
| | | | llvm-svn: 341414
* [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructionsScott Linder2018-09-042-0/+469
| | | | | | | | | Emit a waterfall loop in the general case for a potentially-divergent Rsrc operand. When practical, avoid this by using Addr64 instructions. Differential Revision: https://reviews.llvm.org/D50982 llvm-svn: 341413
* [WebAssembly][NFC] Fix formatting and testsThomas Lively2018-09-041-6/+8
| | | | | | | | | | | | Summary: Small fixes Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51656 llvm-svn: 341411
* [InstCombine] make ((X & C) ^ C) form consistent for vectorsSanjay Patel2018-09-041-2/+2
| | | | | | It would be better to create a 'not' here, but that's not possible yet. llvm-svn: 341410
* [Hexagon] Don't packetize new-value stores with any other storesKrzysztof Parzyszek2018-09-041-0/+25
| | | | llvm-svn: 341409
* NFC: expand memset inline arm64 coverageJF Bastien2018-09-041-15/+212
| | | | | | I'm looking at some codegen optimization in this area and want to make sure I understand the current codegen and don't regress it. This patch simply expands the two existing tests to capture more of the current code generation when it comes to heap-based and stack-based small memset on arm64. The tested code is already pretty good, notably when it comes to using STP, FP stores, FP immediate generation, and folding one of the stores into a stack spill when possible. The uses of STUR could be improved, and some more pairing could occur. Straying from bzero patterns currently yield suboptimal code, and I expect a variety of small changes could make things way better. llvm-svn: 341406
* [MinGW] [AArch64] Add stubs for potential automatic dllimported variablesMartin Storsjo2018-09-041-0/+97
| | | | | | | | | | | The runtime pseudo relocations can't handle the AArch64 format PC relative addressing in adrp+add/ldr pairs. By using stubs, the potentially dllimported addresses can be touched up by the runtime pseudo relocation framework. Differential Revision: https://reviews.llvm.org/D51452 llvm-svn: 341401
* [SimpleLoopUnswitch] remove a chain of dead blocks at onceFedor Sergeev2018-09-041-0/+56
| | | | | | | | | | | | | | | | | | | | | | Recent change to deleteDeadBlocksFromLoop was not enough to fix all the problems related to dead blocks after nontrivial unswitching of switches. We need to delete all the dead blocks that were created during unswitching, otherwise we will keep having problems with phi's or dead blocks. This change removes all the dead blocks that are reachable from the loop, not trying to track whether these blocks are newly created by unswitching or not. While not completely correct, we are unlikely to get loose but reachable dead blocks that do not belong to our loop nest. It does fix all the failures currently known, in particular PR38778. Reviewed By: asbirlea Differential Revision: https://reviews.llvm.org/D51519 llvm-svn: 341398
* [InstCombine] improve xor+and/or testsSanjay Patel2018-09-041-90/+172
| | | | | | | | | | | The tests attempted to check for commuted variants of these folds, but complexity-based canonicalization meant we had no coverage for at least 1/2 of the cases. Also, the folds correctly check hasOneUse(), but there was no coverage for that. llvm-svn: 341394
* AMDGPU: Fix DAG divergence not reporting flat loadsMatt Arsenault2018-09-041-0/+30
| | | | | | Match behavior in DAG of r340343 llvm-svn: 341393
* [WebAssembly] Fix operand rewriting in inline asm lowering.Dan Gohman2018-09-041-1/+1
| | | | | | | | | | | Use MachineOperand::ChangeToImmediate rather than reassigning MachineOperands to new values created from MachineOperand::CreateImm, so that their parent pointers are preserved. This fixes "Instruction has operand with wrong parent set" errors reported by the MachineVerifier. llvm-svn: 341389
* [PGO] Control Height ReductionHiroshi Yamauchi2018-09-041-0/+1912
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Control height reduction merges conditional blocks of code and reduces the number of conditional branches in the hot path based on profiles. if (hot_cond1) { // Likely true. do_stg_hot1(); } if (hot_cond2) { // Likely true. do_stg_hot2(); } -> if (hot_cond1 && hot_cond2) { // Hot path. do_stg_hot1(); do_stg_hot2(); } else { // Cold path. if (hot_cond1) { do_stg_hot1(); } if (hot_cond2) { do_stg_hot2(); } } This speeds up some internal benchmarks up to ~30%. Reviewers: davidxl Reviewed By: davidxl Subscribers: xbolva00, dmgreen, mehdi_amini, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D50591 llvm-svn: 341386
* [MachO] Fix inconsistency between error messages when validating LC_DYSYMTABFrancis Visoiu Mistrih2018-09-041-1/+1
| | | | llvm-svn: 341379
* [MachO] Fix LC_DYSYMTAB validation for external symbolsFrancis Visoiu Mistrih2018-09-041-0/+51
| | | | | | | We were validating the same index (ilocalsym) twice, while iextdefsym was never validated. llvm-svn: 341378
* [dwarfdump] Improve -diff option by hiding more data.Jonas Devlieghere2018-09-041-0/+489
| | | | | | | | | | The -diff option makes it easy to diff dwarf by hiding addresses and offsets. However not all of them were hidden, which should be fixed by this patch. Differential revision: https://reviews.llvm.org/D51593 llvm-svn: 341377
* Revert r341269: [Constant Hoisting] Hoisting Constant GEP ExpressionsChandler Carruth2018-09-044-230/+0
| | | | | | | | | | One of the tests is failing 50% of the time when expensive checks are enabled. Not sure how deep the problem is so just reverting while the author can investigate so that the bots stop repeatedly failing and blaming things incorrectly. Will respond with details on the original commit. llvm-svn: 341365
* [x86/SLH] Add a real Clang flag and LLVM IR attribute for SpeculativeChandler Carruth2018-09-045-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load Hardening. Wires up the existing pass to work with a proper IR attribute rather than just a hidden/internal flag. The internal flag continues to work for now, but I'll likely remove it soon. Most of the churn here is adding the IR attribute. I talked about this Kristof Beyls and he seemed at least initially OK with this direction. The idea of using a full attribute here is that we *do* expect at least some forms of this for other architectures. There isn't anything *inherently* x86-specific about this technique, just that we only have an implementation for x86 at the moment. While we could potentially expose this as a Clang-level attribute as well, that seems like a good question to defer for the moment as it isn't 100% clear whether that or some other programmer interface (or both?) would be best. We'll defer the programmer interface side of this for now, but at least get to the point where the feature can be enabled without relying on implementation details. This also allows us to do something that was really hard before: we can enable *just* the indirect call retpolines when using SLH. For x86, we don't have any other way to mitigate indirect calls. Other architectures may take a different approach of course, and none of this is surfaced to user-level flags. Differential Revision: https://reviews.llvm.org/D51157 llvm-svn: 341363
* Revert r341342: Dwarf .debug section compression support (zlib, zlib-gnu).Chandler Carruth2018-09-046-146/+0
| | | | | | | | | | | | Also reverts follow-up commits r341343 and r341344. The primary commit continues to break some build bots even after the fixes in r341343 for UBSan issues: http://lab.llvm.org:8011/builders/clang-cmake-aarch64-full/builds/5823 It is also failing for me locally (linux, x86-64). llvm-svn: 341360
* [x86/SLH] Teach SLH to harden against the "ret2spec" attack byChandler Carruth2018-09-043-55/+683
| | | | | | | | | | | | | | | | | | | | | | | | | | | | implementing the proposed mitigation technique described in the original design document. The idea is to check after calls that the return address used to arrive at that location is in fact the correct address. In the event of a mis-predicted return which reaches a *valid* return but not the *correct* return, this will detect the mismatch much like it would a mispredicted conditional branch. This is the last published attack vector that I am aware of in the Spectre v1 space which is not mitigated by SLH+retpolines. However, don't read *too* much into that: this is an area of ongoing research where we expect more issues to be discovered in the future, and it also makes no attempt to mitigate Spectre v4. Still, this is an important completeness bar for SLH. The change here is of course delightfully simple. It was predicated on cutting support for post-instruction symbols into LLVM which was not at all simple. Many thanks to Hal Finkel, Reid Kleckner, and Justin Bogner who helped me figure out how to do a bunch of the complex changes involved there. Differential Revision: https://reviews.llvm.org/D50837 llvm-svn: 341358
* [x86/SLH] Teach SLH to harden indirect branches and switches withoutChandler Carruth2018-09-041-21/+418
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | retpolines. This implements the core design of tracing the intended target into the target, checking it, and using that to update the predicate state. It takes advantage of a few interesting aspects of SLH to make it a bit easier to implement: - We already split critical edges with conditional branches, so we can assume those are gone. - We already unfolded any memory access in the indirect branch instruction itself. I've left hard errors in place to catch if any of these somewhat subtle invariants get violated. There is some code that I can factor out and share with D50837 when it lands, but I didn't want to couple landing the two patches, so I'll do that in a follow-up cleanup commit if alright. Factoring out the code to handle different scenarios of materializing an address remains frustratingly hard. In a bunch of cases you want to fold one of the cases into an immediate operand of some other instruction, and you also have both symbols and basic blocks being used which require different methods on the MI builder (and different operand kinds). Still, I'll take a stab at sharing at least some of this code in a follow-up if I can figure out how. Differential Revision: https://reviews.llvm.org/D51083 llvm-svn: 341356
* [InstCombine] Fold icmp ugt/ult (add nuw X, C2), C --> icmp ugt/ult X, (C - C2)Nicola Zaghen2018-09-045-14/+41
| | | | | | | | | | Support for sgt/slt was added in rL294898, this adds the same cases also for unsigned compares. This is the Alive proof: https://rise4fun.com/Alive/nyY Differential Revision: https://reviews.llvm.org/D50972 llvm-svn: 341353
* [NFC] correcting patterns in time-passes test to fix buildbotFedor Sergeev2018-09-041-2/+2
| | | | llvm-svn: 341348
* [PassTiming] reporting time-passes separately for multiple pass instances of ↵Fedor Sergeev2018-09-041-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | the same pass Summary: Refactoring done by rL340872 accidentally appeared to be non-NFC, changing the way how multiple instances of the same pass are handled - aggregation of results by PassName forced data for multiple instances to be merged together and reported as one line. Getting back to creating/reporting timers per pass instance. Reporting was a bit enhanced by counting pass instances and adding #<num> suffix to the pass description. Note that it is instances that are being counted, not invocations of them. time-passes test updated to account for multiple passes being run. Reviewers: paquette, jhenderson, MatzeB, skatkov Reviewed By: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51535 llvm-svn: 341346
* [IndVars] Fix usage of SCEVExpander to not mess with SCEVConstant. PR38674Max Kazantsev2018-09-041-0/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the function `expandSCEVIfNeeded` which behaves not as it was intended. This function tries to make a lookup for exact existing expansion and only goes to normal expansion via `expandCodeFor` if this lookup hasn't found anything. As a result of this, if some instruction above the loop has a `SCEVConstant` SCEV, this logic will return this instruction when asked for this `SCEVConstant` rather than return a constant value. This is both non-profitable and in some cases leads to breach of LCSSA form (as in PR38674). Whether or not it is possible to break LCSSA with this algorithm and with some non-constant SCEVs is still in question, this is still being investigated. I wasn't able to construct such a test so far, so maybe this situation is impossible. If it is, it will go as a separate fix. Rather than do it, it is always correct to just invoke `expandCodeFor` unconditionally: it behaves smarter about insertion points, and as side effect of this it will choose a constant value for SCEVConstants. For other SCEVs it may end up finding a better insertion point. So it should not be worse in any case. NOTE: So far the only known case for which this transform may break LCSSA is mapping of SCEVConstant to an instruction. However there is a suspicion that the entire algorithm can compromise LCSSA form for other cases as well (yet not proved). Differential Revision: https://reviews.llvm.org/D51286 Reviewed By: etherzhhb llvm-svn: 341345
* [llvm-objcopy] Dwarf .debug section compression support (zlib, zlib-gnu).Puyan Lotfi2018-09-036-0/+146
| | | | | | | | | | | | | | | | | | | Usage: llvm-objcopy --compress-debug-sections=zlib foo.o llvm-objcopy --compress-debug-sections=zlib-gnu foo.o In both cases the debug section contents is compressed with zlib. In the GNU style case the header is the "ZLIB" magic string followed by the uint64 big- endian decompressed size. In the non-GNU mode the header is the Elf(32|64)_Chdr. Decompression support is coming soon. Differential Revision: https://reviews.llvm.org/D49678 llvm-svn: 341342
* [AArch64][x86] add tests for pow(x, 0.25); NFCSanjay Patel2018-09-032-0/+344
| | | | | | | Folds for this were proposed in D49306, but we decided the transform is better suited for the backend. llvm-svn: 341341
* [mips] Disable the selection of mixed microMIPS/MIPS codeSimon Atanasyan2018-09-031-2/+1
| | | | | | | | | | | | | This patch modifies hasStandardEncoding() / inMicroMipsMode() / inMips16Mode() methods of the MipsSubtarget class so only one can be true at any one time. That prevents the selection of microMIPS and MIPS instructions and patterns that are defined in TableGen files at the same time. A few new patterns and instruction definitions hae been added to keep test cases passed. Differential revision: https://reviews.llvm.org/D51483 llvm-svn: 341338
* [InstCombine] allow add+not --> sub for arbitrary vector constants.Sanjay Patel2018-09-031-2/+1
| | | | llvm-svn: 341335
* [InstCombine] consolidate tests for ~(X+C); NFCSanjay Patel2018-09-033-74/+33
| | | | llvm-svn: 341332
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-031-23/+0
| | | | | | Support required to build the Hexagon Linux kernel. llvm-svn: 341331
* [SLC] Support expanding pow(x, n+0.5) to x * x * ... * sqrt(x)Florian Hahn2018-09-031-0/+106
| | | | | | | | | | Reviewers: evandro, efriedma, spatel Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D51435 llvm-svn: 341330
* [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.Andrea Di Biagio2018-09-031-87/+89
| | | | | | | | | | | | | | | | | | | | | | A ReadAdvance was incorrectly added to the SchedReadWrite list associated with the following SSE instructions: sqrtss sqrtsd rsqrtss rcpss As a consequence, a wrong operand latency was computed for the register operand used as the base address of the folded load operand. This patch removes the wrong ReadAdvance, and updates the llvm-mca test cases. There is still a problem with correctly modeling partial register writes on XMM registers This other problem is currently tracked here: https://bugs.llvm.org/show_bug.cgi?id=38813 Differential Revision: https://reviews.llvm.org/D51542 llvm-svn: 341326
* DAG: Handle extract_vector_elt in isKnownNeverNaNMatt Arsenault2018-09-031-0/+25
| | | | llvm-svn: 341317
* [DebugInfo] Have the verifier accept missing linkage names.Jonas Devlieghere2018-09-031-0/+646
| | | | | | | | | | | | | | | | | | According to the standard, for the .debug_names (the "dwarf accelerator tables"): > If a subprogram or inlined subroutine is included, and has a > DW_AT_linkage_name attribute, there will be an additional index entry > for the linkage name. For Swift we generate DW_structure_types with a linkage name and the verifier was incorrectly rejecting this. This patch fixes that by only considering the linkage name in those particular cases. The test is the "reduced" debug info of the failing swift test on swift.org. Differential revision: https://reviews.llvm.org/D51420 llvm-svn: 341311
* [Sparc] allow tls_add/tls_call syntax in assembler parserDaniel Cederman2018-09-031-45/+118
| | | | | | | | | | | | | | | | | Summary: Removing unneeded isCodeGenOnly from tls-specific instructions - TLS_ADD/TLS_LD/TLS_LDX/TLS_CALL. Author: fedor.sergeev Reviewers: jyknight, fedor.sergeev Reviewed By: jyknight Subscribers: dcederman, brad, llvm-commits Differential Revision: https://reviews.llvm.org/D36463 llvm-svn: 341308
* Test commit.Carlos Alberto Enciso2018-09-031-2/+0
| | | | | | | | Revert change done in r341297. NFC. Differential Revision: https://reviews.llvm.org/D51583 llvm-svn: 341302
* Extend hasStoreToStackSlot with list of FI accesses.Sander de Smalen2018-09-036-32/+32
| | | | | | | | | | | | | | | | | | For instructions that spill/fill to and from multiple frame-indices in a single instruction, hasStoreToStackSlot and hasLoadFromStackSlot should return an array of accesses, rather than just the first encounter of such an access. This better describes FI accesses for AArch64 (paired) LDP/STP instructions. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D51537 llvm-svn: 341301
* Test commit - adding a new line.Carlos Alberto Enciso2018-09-031-0/+1
| | | | llvm-svn: 341297
* [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8QingShan Zhang2018-09-034-67/+67
| | | | | | | | | | | | | | | | | | When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
* [InstCombine] allow not+sub fold for arbitrary vector constantsSanjay Patel2018-09-021-1/+1
| | | | | | | | The fold was implemented for the general case but use-limitation, but the later constant version which didn't check uses was only matching splat constants. llvm-svn: 341292
* [InstCombine] move/add tests for not+sub; NFCSanjay Patel2018-09-022-34/+84
| | | | llvm-svn: 341291
* Revert "[DebugInfo] Fix bug in LiveDebugVariables."Hsiangkai Wang2018-09-021-51/+0
| | | | | | | | | This reverts commit 8f548ff2a1819e1bc051e8218584f1a3d2cf178a. buildbot failure in LLVM on clang-ppc64be-linux http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/19765 llvm-svn: 341290
* [DebugInfo] Fix bug in LiveDebugVariables.Hsiangkai Wang2018-09-021-0/+51
| | | | | | | | | | | | | | | In lib/CodeGen/LiveDebugVariables.cpp, it uses std::prev(MBBI) to get DebugValue's SlotIndex. However, the previous instruction may be also a debug instruction. It could not use a debug instruction to query SlotIndex in mi2iMap. Scan all debug instructions and use the first debug instruction to query SlotIndex for following debug instructions. Only handle DBG_VALUE in handleDebugValue(). Differential Revision: https://reviews.llvm.org/D50621 llvm-svn: 341289
* [Reassociate] swap binop operands to increase factoring potentialSanjay Patel2018-09-021-35/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we have a pair of binops feeding another pair of binops, rearrange the operands so the matching pair are together because that allows easy factorization folds to happen in instcombine: ((X << S) & Y) & (Z << S) --> ((X << S) & (Z << S)) & Y (reassociation) --> ((X & Z) << S) & Y (factorize shift from 'and' ops optimization) This is part of solving PR37098: https://bugs.llvm.org/show_bug.cgi?id=37098 Note that there's an instcombine version of this patch attached there, but we're trying to make instcombine have less responsibility to improve compile-time efficiency. For reasons I still don't completely understand, reassociate does this kind of transform sometimes, but misses everything in my motivating cases. This patch on its own is gluing an independent cleanup chunk to the end of the existing RewriteExprTree() loop. We can build on it and do something stronger to better order the full expression tree like D40049. That might be an alternative to the proposal to add a separate reassociation pass like D41574. Differential Revision: https://reviews.llvm.org/D45842 llvm-svn: 341288
* [DAGCombine] optimizeSetCCOfSignedTruncationCheck(): handle inverted patternRoman Lebedev2018-09-024-170/+146
| | | | | | | | | | | | | | | | | | | | | | Summary: A follow-up for D49266 / rL337166 + D49497 / rL338044. This is still the same pattern to check for the [lack of] signed truncation, but in this case the constants and the predicate are negated. https://rise4fun.com/Alive/BDV https://rise4fun.com/Alive/n7Z Reviewers: spatel, craig.topper, RKSimon, javed.absar, efriedma, dmgreen Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51532 llvm-svn: 341287
* [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'Dylan McKay2018-09-013-3/+3
| | | | | | The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'. llvm-svn: 341278
* [AVR] Redefine the 'SBR' instruction as an aliasDylan McKay2018-09-011-5/+5
| | | | | | | | | | | This fixes a TableGen warning about duplicate bit patterns. SBR === This is an alias of 'ORI Rd, K'. llvm-svn: 341277
* [AVR] Define the ROL instruction as an alias of ADCDylan McKay2018-09-011-1/+1
| | | | | | | | | The 'rol Rd' instruction is equivalent to 'adc Rd'. This caused compile warnings from tablegen because of conflicting bits shared between each instruction. llvm-svn: 341275
* AMDGPU/GlobalISel: Define instruction mapping for G_SELECTTom Stellard2018-09-011-0/+214
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D49737 llvm-svn: 341271
* [Constant Hoisting] Hoisting Constant GEP ExpressionsZhaoshi Zheng2018-09-014-0/+230
| | | | | | | | | | Leverage existing logic in constant hoisting pass to transform constant GEP expressions sharing the same base global variable. Multi-dimensional GEPs are rewritten into single-dimensional GEPs. Differential Revision: https://reviews.llvm.org/D51396 llvm-svn: 341269
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