summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [yaml2obj] - Don't crash on invalid document.George Rimar2017-09-201-0/+2
| | | | | | | | | | Previously jaml2obj would segfault on empty document. (without yaml description). Patch fixes the issue. Differential revision: https://reviews.llvm.org/D38036 llvm-svn: 313746
* [IfConversion] Add testcases [NFC]Mikael Holmen2017-09-206-0/+211
| | | | | | | These tests should have been included in r310697 / D34099 but apparently I missed them. llvm-svn: 313737
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-09-204-52/+102
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 Commit after rebase for patch D36130 Change-Id: I8add1c265455669ef288d880f870a9522c8c08ab llvm-svn: 313736
* 'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko2017-09-201-0/+6
| | | | llvm-svn: 313735
* AMDGPU: Match load d16 hi instructionsMatt Arsenault2017-09-205-16/+525
| | | | | | | | | | | | Also starts selecting global loads for constant address in some cases. Some end up selecting to mubuf still, which requires investigation. We still get sub-optimal regalloc and extra waitcnts inserted due to not really tracking the liveness of the separate register halves. llvm-svn: 313716
* [AMDGPU] Port of HSAIL inlinerStanislav Mekhanoshin2017-09-202-15/+157
| | | | | | Differential Revision: https://reviews.llvm.org/D36849 llvm-svn: 313714
* AMDGPU: Match store d16_hi instructionsMatt Arsenault2017-09-203-6/+601
| | | | llvm-svn: 313712
* Tighten the invariants around LoopBase::invalidateSanjoy Das2017-09-201-2/+2
| | | | | | | | | | | | | | | | | Summary: With this change: - Methods in LoopBase trip an assert if the receiver has been invalidated - LoopBase::clear frees up the memory held the LoopBase instance This change also shuffles things around as necessary to work with this stricter invariant. Reviewers: chandlerc Subscribers: mehdi_amini, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D38055 llvm-svn: 313708
* Reverting due to Green Dragon bot failure.Mike Edwards2017-09-206-64/+3
| | | | | | http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42594/ llvm-svn: 313706
* [MIRPrinter] Print empty successor lists when they cannot be guessedQuentin Colombet2017-09-192-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-applies commit r313685, this time with the proper updates to the test cases. Original commit message: Unreachable blocks in the machine instr representation are these weird empty blocks with no successors. The MIR printer used to not print empty lists of successors. However, the MIR parser now treats non-printed list of successors as "please guess it for me". As a result, the parser tries to guess the list of successors and given the block is empty, just assumes it falls through the next block (if any). For instance, the following test case used to fail the verifier. The MIR printer would print entry / \ true (def) false (no list of successors) | split.true (use) The MIR parser would understand this: entry / \ true (def) false | / <-- invalid edge split.true (use) Because of the invalid edge, we get the "def does not dominate all uses" error. The fix consists in printing empty successor lists, so that the parser knows what to do for unreachable blocks. rdar://problem/34022159 llvm-svn: 313696
* [WebAssembly] Add support for naming wasm data segmentsSam Clegg2017-09-196-3/+64
| | | | | | | | | Add adds support for naming data segments. This is useful useful linkers so that they can merge similar sections. Differential Revision: https://reviews.llvm.org/D37886 llvm-svn: 313692
* Revert "[MIRPrinter] Print empty successor lists when they cannot be guessed"Quentin Colombet2017-09-191-48/+0
| | | | | | | | | This reverts commit r313685. I thought I had ran ninja check, but apparently I didn't... Need to update a bunch of mir tests. llvm-svn: 313686
* [MIRPrinter] Print empty successor lists when they cannot be guessedQuentin Colombet2017-09-191-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unreachable blocks in the machine instr representation are these weird empty blocks with no successors. The MIR printer used to not print empty lists of successors. However, the MIR parser now treats non-printed list of successors as "please guess it for me". As a result, the parser tries to guess the list of successors and given the block is empty, just assumes it falls through the next block (if any). For instance, the following test case used to fail the verifier. The MIR printer would print entry / \ true (def) false (no list of successors) | split.true (use) The MIR parser would understand this: entry / \ true (def) false | / <-- invalid edge split.true (use) Because of the invalid edge, we get the "def does not dominate all uses" error. The fix consists in printing empty successor lists, so that the parser knows what to do for unreachable blocks. rdar://problem/34022159 llvm-svn: 313685
* Reland "[llvm-objcopy] Add support for nested and overlapping segments"Jake Ehrlich2017-09-195-0/+455
| | | | | | | | | | | I didn't initialize a pointer to be nullptr that I needed to. This change adds support for nested and even overlapping segments. This means that PT_PHDR, PT_GNU_RELRO, PT_TLS, and PT_DYNAMIC can be supported properly. Differential Revision: https://reviews.llvm.org/D36558 llvm-svn: 313682
* [ARM] Relax 'cpsie'/'cpsid' flag parsing.Jonathan Roelofs2017-09-191-0/+2
| | | | | | | | | | The ARM docs suggest in examples that the flags can have either case, and there are applications in the wild that (libopencm3, for example) that expect to be able to use the uppercase spelling. https://reviews.llvm.org/D37953 llvm-svn: 313680
* Revert "[DebugInfo] Insert DW_OP_deref when spilling indirect DBG_VALUEs"Reid Kleckner2017-09-194-308/+3
| | | | | | | | | This reverts r313640, originally r313400, one more time for essentially the same issue. My BitVector of spilled location numbers isn't working because we coalesce identical DBG_VALUE locations as we rewrite them, invalidating the location numbers used to index the BitVector. llvm-svn: 313679
* Import all inlined indirect call targets for SamplePGO.Dehao Chen2017-09-192-6/+16
| | | | | | | | | | | | | | Summary: In the ThinLTO compilation, if a function is inlined in the profiling binary, we need to inline it before annotation. If the callee is not available in the primary module, a first step is needed to import that callee function. For the current implementation, if the call is an indirect call, which has been promoted to >1 targets and inlined, SamplePGO will only import one target with the largest sample count. This patch fixed the bug to import all targets instead. Reviewers: tejohnson, davidxl Reviewed By: tejohnson Subscribers: sanjoy, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D36637 llvm-svn: 313678
* llvm-dwarfdump: un-hide more command line optionsAdrian Prantl2017-09-191-0/+5
| | | | llvm-svn: 313673
* Move test into non-target-specific directory.Adrian Prantl2017-09-191-0/+0
| | | | llvm-svn: 313672
* [AMDGPU] Prevent post-RA scheduler from breaking memory clausesStanislav Mekhanoshin2017-09-1923-87/+119
| | | | | | | | | The pre-RA scheduler does load/store clustering, but post-RA scheduler undoes it. Add mutation to prevent it. Differential Revision: https://reviews.llvm.org/D38014 llvm-svn: 313670
* [SystemZ] Fix truncstore + bswap codegen bugUlrich Weigand2017-09-191-0/+17
| | | | | | | | | | | | | SystemZTargetLowering::combineSTORE contains code to transform a combination of STORE + BSWAP into a STRV type instruction. This transformation is correct for regular stores, but not for truncating stores. The routine neglected to check for that case. Fixes a miscompilation of llvm-objcopy with clang, which caused test suite failures in the SystemZ multistage build bot. llvm-svn: 313669
* Revert "ExecutionEngine: add R_AARCH64_ABS{16,32}"Saleem Abdulrasool2017-09-191-13/+0
| | | | | | | | This reverts commit SVN r313654. Seems that it is triggering an assertion on Windows specifically. Revert until I can build on Windows and look into what is happening there. llvm-svn: 313668
* Revert "[llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstr"Jake Ehrlich2017-09-195-123/+0
| | | | | | | This reverts commit r313663. Broken because overlapping-sections was reverted. llvm-svn: 313665
* Revert "[llvm-objcopy] Add support for nested and overlapping segments"Jake Ehrlich2017-09-195-455/+0
| | | | | | This reverts commit r313656. Appears to be broken on Windows. llvm-svn: 313664
* [llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstrJake Ehrlich2017-09-195-0/+123
| | | | | | | | | | | | | | | This change adds support for sections involved in dynamic loading such as SHT_DYNAMIC, SHT_DYNSYM, and allocated string tables. The two added binaries used for tests can be downloaded [[ https://drive.google.com/file/d/0B3gtIAmiMwZXOXE3T0RobFg4ZTg/view?usp=sharing | here ]] and [[ https://drive.google.com/file/d/0B3gtIAmiMwZXTFJSQUJZMGxNSXc/view?usp=sharing | here ]] Differential Revision: https://reviews.llvm.org/D36560 llvm-svn: 313663
* Fix test to not depend on another subdirectories Input directoryDavid Blaikie2017-09-192-2/+51
| | | | | | | | Inputs should be placed local to the test (or possibly in a common parent? I think we do that in some places - but the only common parent between these two directories is 'test' which seems a bit overly broad). llvm-svn: 313662
* [llvm-objcopy] Add test to check that architecture specific values are not ↵Jake Ehrlich2017-09-192-1/+16
| | | | | | | | | | | used on wrong architecture. This change adds a test that checks the an error is produced when a hexagon specific reserved section index is used but e_machine is not EM_HEXAGON. Differential Revision: https://reviews.llvm.org/D38017 llvm-svn: 313661
* Handle profile mismatch correctly for SamplePGO.Dehao Chen2017-09-192-0/+23
| | | | | | | | | | | | | | Summary: Fix the bug when promoted call return type mismatches with the promoted function, we should not try to inline it. Otherwise it may lead to compiler crash. Reviewers: davidxl, tejohnson, eraman Reviewed By: tejohnson Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D38018 llvm-svn: 313658
* Re-land "Fix Bug 30978 by emitting cv file checksums."Reid Kleckner2017-09-194-17/+77
| | | | | | | This reverts r313431 and brings back r313374 with a fix to write checksums as binary data and not ASCII hex strings. llvm-svn: 313657
* [llvm-objcopy] Add support for nested and overlapping segmentsJake Ehrlich2017-09-195-0/+455
| | | | | | | | | This change adds support for nested and even overlapping segments. This means that PT_PHDR, PT_GNU_RELRO, PT_TLS, and PT_DYNAMIC can be supported properly. Differential Revision: https://reviews.llvm.org/D36558 llvm-svn: 313656
* ExecutionEngine: add R_AARCH64_ABS{16,32}Saleem Abdulrasool2017-09-191-0/+13
| | | | | | | | | | Add support for the R_AARCH64_ABS{16,32} relocations in the execution engine. This is primarily used for DWARF debug information relocations and needed by the LLVM JIT to support JITing for lldb. Patch by Alex Langford! llvm-svn: 313654
* Re-land r313400 "[DebugInfo] Insert DW_OP_deref when spilling indirect ↵Reid Kleckner2017-09-194-3/+308
| | | | | | | | | | | | | | DBG_VALUEs" I forgot to zero out the BitVector when reusing it between UserValues. Later uses of the same location number for a different UserValue would falsely indicate that they were spilled. Usually this would lead to incorrect debug info, but in some cases they would indicate something nonsensical like a memory location based on a vector register (Q8 on ARM). llvm-svn: 313640
* [PowerPC Peephole] Constants into a join add, use ADDI over LI/ADD.Tony Jiang2017-09-191-0/+60
| | | | | | | | | | Two blocks prior to the join each perform an li and the the join block has an add using the initialized register. Optimize each predecessor block to instead use addi and delete the li's and add. Differential Revision: https://reviews.llvm.org/D36734 llvm-svn: 313639
* [AArch64] Extend tests of loads and stores of register pairsEvandro Menezes2017-09-192-2/+45
| | | | | | Include instances of FP register pairs. llvm-svn: 313638
* [Power9] Add missing Power9 instructions.Tony Jiang2017-09-192-0/+53
| | | | | | | The following 8 instructions are implemented in this patch. addpcis(subpcis, lnia), darn, maddhd, maddhdu, maddld, setb llvm-svn: 313636
* [globalisel] Add a G_BSWAP instruction and support bswap using it.Daniel Sanders2017-09-191-0/+60
| | | | llvm-svn: 313633
* [X86][SSE] Add 'redundant pand' test case from PR34620Simon Pilgrim2017-09-191-0/+19
| | | | llvm-svn: 313632
* [x86] regenerate checks; NFCSanjay Patel2017-09-191-13/+76
| | | | llvm-svn: 313631
* [SLP] Reduce test, NFC.Alexey Bataev2017-09-191-134/+56
| | | | llvm-svn: 313630
* [globalisel] Add support for intrinsic_voidDaniel Sanders2017-09-191-0/+29
| | | | llvm-svn: 313629
* [globalisel] Add support for intrinsic_w_chain.Daniel Sanders2017-09-191-0/+27
| | | | | | This maps directly to G_INTRINSIC_W_SIDE_EFFECTS. llvm-svn: 313627
* [x86] Lowering Mask Set1 intrinsics to LLVM IRJina Nahias2017-09-1912-262/+2275
| | | | | | | | This patch, together with a matching clang patch (https://reviews.llvm.org/D37668), implements the lowering of X86 mask set1 intrinsics to IR. Differential Revision: https://reviews.llvm.org/D37669 llvm-svn: 313625
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-193-15/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 313618
* Test commit.Andrei Elovikov2017-09-191-1/+0
| | | | llvm-svn: 313617
* AMDGPU: Run internalize symbols at -O0Matt Arsenault2017-09-191-15/+48
| | | | | | | | The relocations used for externally visible functions aren't supported, so the direct call emitted ends up hitting a linker error. llvm-svn: 313616
* [X86][Skylake] Adding the scheduling information for the SkylakeClient targetGadi Haber2017-09-1914-850/+1033
| | | | | | | | | | | | | | This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
* [X86] Add VPERMPD/VPERMQ and VPERMPS/VPERMD to the execution domain fixing ↵Craig Topper2017-09-1929-549/+555
| | | | | | table. llvm-svn: 313610
* [llvm-cov] Make report metrics agree with line exec counts, fixes PR34615Vedant Kumar2017-09-195-9/+9
| | | | | | | | | Use the same logic as the line-oriented coverage view to determine the number of covered lines in a function. Fixes llvm.org/PR34615. llvm-svn: 313604
* [Coverage] Use gap regions to select better line exec countsVedant Kumar2017-09-182-21/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | After clang started emitting deferred regions (r312818), llvm-cov has had a hard time picking reasonable line execuction counts. There have been one or two generic improvements in this area (e.g r310012), but line counts can still report coverage for whitespace instead of code (llvm.org/PR34612). To fix the problem: * Introduce a new region kind so that frontends can explicitly label gap areas. This is done by changing the encoding of the columnEnd field of MappingRegion. This doesn't substantially increase binary size, and makes it easy to maintain backwards-compatibility. * Don't set the line count to a count from a gap area, unless the count comes from a wrapped segment. * Don't highlight gap areas as uncovered. Fixes llvm.org/PR34612. llvm-svn: 313597
* [llvm-cov] Repair a test. NFC.Vedant Kumar2017-09-181-1/+1
| | | | | | | The checks with the MARKER prefix were not being run over the right input, because stderr was not redirected properly. llvm-svn: 313596
OpenPOWER on IntegriCloud