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* Revert r304824 "Fix PR23384 (part 3 of 3)"Hans Wennborg2017-06-1913-93/+89
| | | | | | | | | | | | | | | | | This seems to be interacting badly with ASan somehow, causing false reports of heap-buffer overflows: PR33514. > Summary: > The patch makes instruction count the highest priority for > LSR solution for X86 (previously registers had highest priority). > > Reviewers: qcolombet > > Differential Revision: http://reviews.llvm.org/D30562 > > From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 305720
* [CodeView] Fix dumping of public symbol record flagsReid Kleckner2017-06-191-2/+2
| | | | | | | I noticed nonsensical type information while dumping PDBs produced by MSVC. llvm-svn: 305708
* [InstCombine] Cleanup some duplicated one use checksCraig Topper2017-06-192-4/+4
| | | | | | | | | | | | | | | | | | | Summary: These 4 patterns have the same one use check repeated twice for each. Once without a cast and one with. But the cast has no effect on what method is called. For the OR case I believe it is always profitable regardless of the number of uses since we'll never increase the instruction count. For the AND case I believe it is profitable if the pair of xors has one use such that we'll get rid of it completely. Or if the C value is something freely invertible, in which case the not doesn't cost anything. Reviewers: spatel, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34308 llvm-svn: 305705
* [Reassociate] Support some reassociation of vector xorsCraig Topper2017-06-191-4/+14
| | | | | | | | | | | | | | | | | Summary: Currently we don't try to do anything with vector xors. This patch adds support for removing duplicate pairs from a chain of vector xors as its pretty easy to support. We still dont' try to combine the xors with and/ors, but I might try that in a future patch. Reviewers: mcrosier, davide, resistor Reviewed By: mcrosier Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34338 llvm-svn: 305704
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.Artem Tamazov2017-06-195-82692/+259228
| | | | | | | | | | | A new Gfx9 dasm test added with approx 29000 cases. Existing tests extended by (approx.): * Gfx7 asm: 5000 test cases * Gfx8 asm: 5000 test cases * Gfx9 asm: 14400 test cases * Gfx8 dasm: 5200 test cases llvm-svn: 305702
* [JumpThreading][LVI] Invalidate LVI information after blocks are mergedAnna Thomas2017-06-191-0/+87
| | | | | | | | | | | | | | | | | | | Summary: After a single predecessor is merged into a basic block, we need to invalidate the LVI information for the new merged block, when LVI is not provably true for all of instructions in the new block. The test cases added show the correct LVI information using the LVI printer pass. Reviewers: reames, dberlin, davide, sanjoy Reviewed by: dberlin, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34108 llvm-svn: 305699
* [TRE] Improve code motion in TRE, use AA to tell whether a load can be moved ↵Xin Tong2017-06-191-0/+27
| | | | | | | | | | | | | | | | before a call that writes to memory. Summary: use AA to tell whether a load can be moved before a call that writes to memory. Reviewers: dberlin, davide, sanjoy, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D34115 llvm-svn: 305698
* Add test for store merge with noimplicitfloatNirav Dave2017-06-191-0/+23
| | | | llvm-svn: 305697
* AMDGPU/GlobalISel: Mark G_BITCAST s32 <--> <2 x s16> legalTom Stellard2017-06-191-0/+23
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D34129 llvm-svn: 305692
* [GlobalISel][X86] Fold FI/G_GEP into LDR/STR instruction addressing mode.Igor Breger2017-06-197-171/+206
| | | | | | | | | | | | | | Summary: Implement some of the simplest addressing modes.It should help to test ABI. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33888 llvm-svn: 305691
* [ARM] GlobalISel: Support G_ICMP for s8 and s16Diana Picus2017-06-192-3/+74
| | | | | | Widen to s32 (like all other binary ops). llvm-svn: 305683
* [ARM] GlobalISel: Support G_ICMP for i32 and pointersDiana Picus2017-06-194-0/+457
| | | | | | | | | | | | | | Add support throughout the pipeline: - mark as legal for s32 and pointers - map to GPRs - lower to a sequence of instructions, which moves 0 or 1 into the result register based on the flags set by a CMPrr We have copied from FastISel a helper function which maps CmpInst predicates into ARMCC codes. Ideally, we should be able to move it somewhere that both FastISel and GlobalISel can use. llvm-svn: 305672
* [X86] Simplify vector-shuffle-v48 test. NFC.Guy Blank2017-06-191-42/+39
| | | | llvm-svn: 305670
* [SCEV] Teach SCEVExpander to expand BinPowMax Kazantsev2017-06-191-0/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of SCEVExpander demonstrates a very naive behavior when it deals with power calculation. For example, a SCEV for x^8 looks like (x * x * x * x * x * x * x * x) If we try to expand it, it generates a very straightforward sequence of muls, like: x2 = mul x, x x3 = mul x2, x x4 = mul x3, x ... x8 = mul x7, x This is a non-efficient way of doing that. A better way is to generate a sequence of binary power calculation. In this case the expanded calculation will look like: x2 = mul x, x x4 = mul x2, x2 x8 = mul x4, x4 In some cases the code size reduction for such SCEVs is dramatic. If we had a loop: x = a; for (int i = 0; i < 3; i++) x = x * x; And this loop have been fully unrolled, we have something like: x = a; x2 = x * x; x4 = x2 * x2; x8 = x4 * x4; The SCEV for x8 is the same as in example above, and if we for some reason want to expand it, we will generate naively 7 multiplications instead of 3. The BinPow expansion algorithm here allows to keep code size reasonable. This patch teaches SCEV Expander to generate a sequence of BinPow multiplications if we have repeating arguments in SCEVMulExpressions. Differential Revision: https://reviews.llvm.org/D34025 llvm-svn: 305663
* NewGVN: Fix PR 33461, caused by slightly overzealous verification.Daniel Berlin2017-06-191-0/+36
| | | | llvm-svn: 305657
* [x86] specify triples and auto-generate complete checks; NFCSanjay Patel2017-06-183-80/+174
| | | | llvm-svn: 305656
* [x86] specify triples and auto-generate complete checks; NFCSanjay Patel2017-06-184-122/+244
| | | | llvm-svn: 305655
* [x86] specify triple and auto-generate checks; NFCSanjay Patel2017-06-183-86/+182
| | | | llvm-svn: 305654
* x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-184-33/+33
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305646
* [x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-181-7/+7
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305645
* [x86] adjust test constants to maintain coverage; NFCSanjay Patel2017-06-181-10/+10
| | | | | | Increment (add 1) could be transformed to sub -1, and we'd lose coverage for these patterns. llvm-svn: 305644
* Add argmononly attribute to strlen and wcslen, i.e. they only read memory ↵Xin Tong2017-06-182-3/+23
| | | | | | | | | | | | | | | | (string) passed to them. Summary: This allows strlen to be moved out of the loop in case its argument is not modified in the loop in LICM. Reviewers: hfinkel, davide, sanjoy, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34323 llvm-svn: 305641
* [SROA] Add support for non-integral pointersSanjoy Das2017-06-171-0/+46
| | | | | | | | | | | | | | Summary: C.f. http://llvm.org/docs/LangRef.html#non-integral-pointer-type Reviewers: chandlerc, loladiro Reviewed By: loladiro Subscribers: reames, loladiro, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D32203 llvm-svn: 305639
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2017-06-1712-117/+238
| | | | | | | | | | | | | | | | | | | Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
* [SelectionDAG] Update Loop info after splitting critical edges.Davide Italiano2017-06-171-0/+27
| | | | | | The analysis is expected to be preserved by SelectionDAG. llvm-svn: 305621
* [InstCombine] Make FPMathOperator working with ConstantExpression(s).Davide Italiano2017-06-171-0/+15
| | | | | | | | Fixes PR33453. Differential Revision: https://reviews.llvm.org/D34303 llvm-svn: 305618
* [WebAssembly] Use __stack_pointer global when writing wasm binarySam Clegg2017-06-166-49/+69
| | | | | | | | | | | | | | | | | | This ensures that symbolic relocations are generated for stack pointer manipulations. These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB. This change also adds support for reading relocations of this type in WasmObjectFile.cpp. Since its a globally imported symbol this does mean that the get_global/set_global instruction won't be valid until the objects are linked that global used in no longer an imported global. Differential Revision: https://reviews.llvm.org/D34172 llvm-svn: 305616
* obj2yaml: Improve error reportingSam Clegg2017-06-163-2/+6
| | | | | | | | | | Previously only the error codes were reported which meant that useful information about malformed inputs was not shown. Differential Revision: https://reviews.llvm.org/D34008 llvm-svn: 305609
* Revert rL305578. There is still some buildbot failure to be fixed.Wei Mi2017-06-163-135/+4
| | | | llvm-svn: 305603
* Move testcase into the target-appropriate subdirectory.Adrian Prantl2017-06-161-0/+0
| | | | llvm-svn: 305602
* Improve the accuracy of variable ranges .debug_loc location lists.Adrian Prantl2017-06-169-60/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the following motivating example bool c(); void f(); bool start() { bool result = c(); if (!c()) { result = false; goto exit; } f(); result = true; exit: return result; } we would previously generate a single DW_AT_const_value(1) because only the DBG_VALUE in the second-to-last basic block survived codegen. This patch improves the heuristic used to determine when a DBG_VALUE is available at the beginning of its variable's enclosing lexical scope: - Stop giving singular constants blanket permission to take over the entire scope. There is still a special case for constants in the function prologue that we also miight want to retire later. - Use the lexical scope information to determine available-at-entry instead of proximity to the function prologue. After this patch we generate a location list with a more accurate narrower availability for the constant true value. As a pleasant side effect, we also generate inline locations instead of location lists where a loacation covers the entire range of the enclosing lexical scope. Measured on compiling llc with four targets this doesn't have an effect on compile time and reduces the size of the debug info for llc by ~600K. rdar://problem/30286912 llvm-svn: 305599
* [DWARF] Corrected behavior for when no .apple_names section is present in ↵Spyridoula Gravani2017-06-162-1/+175
| | | | | | | | | | the object. The verifier should not output any message in such a case. Added test case with no .apple_name section in the file to verify new functionality. Made existing test case more specific. llvm-svn: 305597
* [InstCombine] Set correct insertion point for selects generated while ↵Anna Thomas2017-06-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | folding phis Summary: When we fold vector constants that are operands of phi's that feed into select, we need to set the correct insertion point for the *new* selects that get generated. The correct insertion point is the incoming block for the phi. Such cases can occur with patch r298845, which fixed folding of vector constants, but the new selects could be inserted incorrectly (as the added test case shows). Reviewers: majnemer, spatel, sanjoy Reviewed by: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34162 llvm-svn: 305591
* Change YAML traits for vector<string> to flow_vector.Evgeniy Stepanov2017-06-161-7/+2
| | | | | | | This is a workaround for an ODR conflict with the definition in AMDGPUCodeObjectMetadata.cpp. llvm-svn: 305584
* [GVN] Recommit the patch "Add phi-translate support in scalarpre".Wei Mi2017-06-163-4/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recommit fixes two bugs: The first one is to use CurrentBlock instead of PREInstr's Parent as param of performScalarPREInsertion because the Parent of a clone instruction may be uninitialized. The second one is stop PRE when CurrentBlock to its predecessor is a backedge and an operand of CurInst is defined inside of CurrentBlock. The same value defined inside of loop in last iteration can not be regarded as available. Right now scalarpre doesn't have phi-translate support, so it will miss some simple pre opportunities. Like the following testcase, current scalarpre cannot recognize the last "a * b" is fully redundent because a and b used by the last "a * b" expr are both defined by phis. long a[100], b[100], g1, g2, g3; __attribute__((pure)) long goo(); void foo(long a, long b, long c, long d) { g1 = a * b; if (__builtin_expect(g2 > 3, 0)) { a = c; b = d; g2 = a * b; } g3 = a * b; // fully redundant. } The patch adds phi-translate support in scalarpre. This is only a temporary solution before the newpre based on newgvn is available. Differential Revision: https://reviews.llvm.org/D32252 llvm-svn: 305578
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2017-06-1612-181/+117
| | | | | | | | | Revert because of reports of some PPC input starting to spill when it was predicted that it wouldn't and no spillslot was reserved. This reverts commit r305516. llvm-svn: 305566
* [InstCombine] Add test cases to show missed opportunities due to overly ↵Craig Topper2017-06-162-0/+77
| | | | | | conservative single use checks. NFC llvm-svn: 305562
* bpf: avoid load from read-only sectionsYonghong Song2017-06-164-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | If users tried to have a structure decl/init code like below struct test_t t = { .memeber1 = 45 }; It is very likely that compiler will generate a readonly section to hold up the init values for variable t. Later load of t members, e.g., t.member1 will result in a read from readonly section. BPF program cannot handle relocation. This will force users to write: struct test_t t = {}; t.member1 = 45; This is just inconvenient and unintuitive. This patch addresses this issue by implementing BPF PreprocessISelDAG. For any load from a global constant structure or an global array of constant struct, it attempts to translate it into a constant directly. The traversal of the constant struct and other constant data structures are similar to where the assembler emits read-only sections. Four different unit test cases are also added to cover different scenarios. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 305560
* [Atomics] Rename and change prototype for atomic memcpy intrinsicDaniel Neilson2017-06-165-61/+72
| | | | | | | | | | | | | | | | | | Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
* Revert "[mips][microMIPS] Extending size reduction pass with ADDIUSP and ↵Simon Dardis2017-06-161-17/+0
| | | | | | | | | ADDIUR1SP" This reverts commit r305455. This commit was reported as breaking one of the sanitizer buildbots. Reverting until lab.llvm.org comes back online. llvm-svn: 305557
* [Hexagon] Don't kill live registers when creating mux out of tfrKrzysztof Parzyszek2017-06-161-0/+17
| | | | | | | | | The second part of r305300: when placing the mux at the later location, make sure that it won't use any register that was killed between the two original instructions. Remove any such kills and transfer them to the mux. llvm-svn: 305553
* [InstCombine] Fold (!iszero(A & K1) & !iszero(A & K2)) -> (A & (K1 | K2)) ↵Craig Topper2017-06-161-12/+8
| | | | | | | | | | | | | | | | == (K1 | K2) if K1 and K2 are a 1-bit mask Summary: This is the demorganed version of the case we already handle for the OR of iszero. Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34244 llvm-svn: 305548
* [cfi] CFI-ICall for ThinLTO.Evgeniy Stepanov2017-06-165-0/+181
| | | | | | | | Implement ControlFlowIntegrity for indirect function calls in ThinLTO. Design follows the RFC in llvm-dev, see https://groups.google.com/d/msg/llvm-dev/MgUlaphu4Qc/kywu0AqjAQAJ llvm-svn: 305533
* [llvm-pdbutil] Add support for dumping lines and inlinee lines.Zachary Turner2017-06-151-0/+11
| | | | llvm-svn: 305529
* [llvm-pdbutil] Add back support for dumping file checksums.Zachary Turner2017-06-151-399/+371
| | | | | | When dumping module source files, also dump checksums. llvm-svn: 305526
* [llvm-pdbutil] Add back the ability to dump hashes and index offsets.Zachary Turner2017-06-151-90/+96
| | | | | | | This was regressed in a previous patch that re-wrote the dumper, and I'm incrementally adding back the pieces that are missing. llvm-svn: 305524
* Resubmit "[llvm-pdbutil] rewrite the "raw" output style."Zachary Turner2017-06-1510-3372/+1274
| | | | | | | | | This resubmits commit c0c249e9f2ef83e1d1e5f166b50673d92f3579d7. It was broken due to some weird template issues, which have since been fixed. llvm-svn: 305517
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2017-06-1512-117/+181
| | | | | | | | | | | | | | | | | | Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64 problems reported in the stage2 build last time, which I cannot reproduce right now. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305516
* [InstCombine] Add test cases to demonstrate instcombine increasing ↵Craig Topper2017-06-151-0/+237
| | | | | | instruction count when trying to fold (select (icmp eq (and X, C1), 0), Y, (or Y, C2))->(or (shl (and X, C1), C3), y) when the pieces have multiple uses. llvm-svn: 305509
* Revert "[llvm-pdbutil] rewrite the "raw" output style."Zachary Turner2017-06-1510-1274/+3372
| | | | | | | | | This reverts commit 83ea17ebf2106859a51fbc2a86031b44d33696ad. This is failing due to some strange template problems, so reverting until it can be straightened out. llvm-svn: 305505
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