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* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-0/+28
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [ARM] GlobalISel: Tighten G_FCMP selection test. NFCDiana Picus2017-07-111-68/+68
| | | | | | | | Use CHECK-NEXT for the comparison sequence, to make sure we don't get any unexpected instructions in the middle of our flag manipulation efforts. llvm-svn: 307656
* [DWARF] - Add testcase for checking message about broken relocations.George Rimar2017-07-111-0/+35
| | | | | | Addresses comments for r306677, which fixed error message itself. llvm-svn: 307655
* [X86][AVX512] regenerate avx512-insert-extract.llGuy Blank2017-07-111-3/+3
| | | | llvm-svn: 307654
* [ARM] GlobalISel: Add reg mapping for s64 G_FCMPDiana Picus2017-07-111-0/+29
| | | | | | Map the result into GPR and the operands into FPR. llvm-svn: 307653
* [ARM] GlobalISel: Tighten legalizer tests. NFCDiana Picus2017-07-113-0/+110
| | | | | | | | | | | | | | Make sure that all the legalizer tests where the original instruction needs to be removed check for the removal. We do this by adding CHECK-NOT lines before and after the replacement sequence. This won't catch pathological cases where the instruction remains somewhere in the middle of the instruction sequence that's supposed to replace it, but hopefully that won't occur in practice (since ideally we'd be setting the insert point for the new instruction sequence either before or after the original instruction and not fiddle with it while building the sequence). llvm-svn: 307647
* [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is ↵Daniel Sanders2017-07-111-46/+102
| | | | | | | | | | | | | | | | | | | | | | used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
* [ARM] ldr pc,=expression should be allowed in Thumb2Peter Smith2017-07-111-8/+8
| | | | | | | | | | | This change allows the pc to be used as a destination register for the pseudo instruction LDR pc,=expression . The pseudo instruction must not be transformed into a MOV, but it can use the Thumb2 LDR (literal) instruction to a constant pool entry. See (A7.7.43 from ARMv7M ARM ARM). Differential Revision: https://reviews.llvm.org/D34751 llvm-svn: 307640
* [ARM] GlobalISel: Fix oversight in G_FCMP legalizationDiana Picus2017-07-111-0/+8
| | | | | | | We used to forget to erase the original instruction when replacing a G_FCMP true/false. Fix this bug and make sure the tests check for it. llvm-svn: 307639
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-112-2/+40
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [ARM] GlobalISel: Legalize s64 G_FCMPDiana Picus2017-07-111-0/+878
| | | | | | Same as the s32 version, for both hard and soft float. llvm-svn: 307633
* Revert Revert [MBP] do not rotate loop if it creates extra branchSerguei Katkov2017-07-112-4/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a second attempt to land this patch. The first one resulted in a crash of clang sanitizer buildbot. The fix is here and regression test is added. This is a last fix for the corner case of PR32214. Actually this is not really corner case in general. We should not do a loop rotation if we create an additional branch due to it. Consider the case where we have a loop chain H, M, B, C , where H is header with viable fallthrough from pre-header and exit from the loop M - some middle block B - backedge to Header but with exit from the loop also. C - some cold block of the loop. Let's H is determined as a best exit. If we do a loop rotation M, B, C, H we can introduce the extra branch. Let's compute the change in number of branches: +1 branch from pre-header to header -1 branch from header to exit +1 branch from header to middle block if there is such -1 branch from cold bock to header if there is one So if C is not a predecessor of H then we introduce extra branch. This change actually prohibits rotation of the loop if both true Best Exit has next element in chain as successor. Last element in chain is not a predecessor of first element of chain. Reviewers: iteratee, xur, sammccall, chandlerc Reviewed By: iteratee Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34745 llvm-svn: 307631
* [GlobalISel][X86] Use correct AND instructions.Igor Breger2017-07-111-1/+1
| | | | | | AND8ri8 not supported in 64bit. llvm-svn: 307630
* [CGP] Relax a bit restriction for optimizeMemoryInst to extend scopeSerguei Katkov2017-07-111-0/+25
| | | | | | | | | | | | | | | | | | CodeGenPrepare::optimizeMemoryInst contains a check that we do nothing if all instructions combining the address for memory instruction is in the same block as memory instruction itself. However if any of these instruction are placed after memory instruction then address calculation will not be folded to memory instruction. The added test case shows an example. Reviewers: loladiro, spatel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34862 llvm-svn: 307628
* fix typos in comments; NFCHiroshi Inoue2017-07-111-1/+1
| | | | llvm-svn: 307626
* [PM/ThinLTO] Fix PR33536, a bug where the ThinLTO bitcode writer wasChandler Carruth2017-07-111-0/+37
| | | | | | | | | | | | | querying for analysis results on a function declaration rather than a definition. The only reason this worked previously is by chance -- because the way we got alias analysis results with the legacy PM, we happened to not compute a dominator tree and so we happened to not hit an assert even though it didn't make any real sense. Now we bail out before trying to compute alias analysis so that we don't hit these asserts. llvm-svn: 307625
* [InstCombine] Add test case for PR33721.Craig Topper2017-07-111-0/+7
| | | | llvm-svn: 307621
* [AVR] Use the generic branch relaxerDylan McKay2017-07-114-7/+104
| | | | llvm-svn: 307617
* [llvm-cov] Disable threading in a test. NFC.Vedant Kumar2017-07-111-1/+1
| | | | | | | | | | | | PR30735 reports an issue where llvm-cov hangs with a worker thread waiting on a condition, and the main thread waiting to join() the workers. While this doesn't appear to be a bug in llvm-cov or the ThreadPool implementation, it would be helpful to disable the use of threading in the llvm-cov tests where no test coverage is added. More context: https://bugs.llvm.org/show_bug.cgi?id=30735 llvm-svn: 307610
* [llvm-cov] Add a cl::opt to control the number of threadsVedant Kumar2017-07-111-0/+11
| | | | | | | | | | When an output directory is specified, llvm-cov spawns some threads to speed up the process of writing out file reports. Add an option which allows users to control how many threads llvm-cov uses. A CommandGuide.rst update + test is included. llvm-svn: 307609
* Revert "[DAG] Improve Aliasing of operations to static alloca"Matthias Braun2017-07-1023-152/+119
| | | | | | | | | Reverting as it breaks tramp3d-v4 in the llvm test-suite. I added some comments to https://reviews.llvm.org/D33345 about it. This reverts commit r307546. llvm-svn: 307589
* [WebAssembly] Add more details to llvm-readobj for wasm filesSam Clegg2017-07-101-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D35208 llvm-svn: 307588
* [ConstantHoisting] Remove dupliate logic in constant hoistingLeo Li2017-07-102-0/+62
| | | | | | | | | | | | | | | | | | | | | Summary: As metioned in https://reviews.llvm.org/D34576, checkings in `collectConstantCandidates` can be replaced by using `llvm::canReplaceOperandWithVariable`. The only special case is that `collectConstantCandidates` return false for all `IntrinsicInst` but it is safe for us to collect constant candidates from `IntrinsicInst`. Reviewers: pirama, efriedma, srhines Reviewed By: efriedma Subscribers: llvm-commits, javed.absar Differential Revision: https://reviews.llvm.org/D34921 llvm-svn: 307587
* [WebAssembly] Be consistent in generating trivial test input filesSam Clegg2017-07-1016-112/+184
| | | | | | | | | | | | | For each checked-in wasm file, make sure the there is corresponding .ll file that can be used to regenerate it if needed. Add test/Object/Inputs/trivial-object-test.wasm to match other formats and add some new wasm tests in test/Object. Differential Revision: https://reviews.llvm.org/D35213 llvm-svn: 307585
* AMDGPU: Allow SIShrinkInstructions to fold FrameIndexesMatt Arsenault2017-07-102-4/+163
| | | | llvm-svn: 307576
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-1068-430/+470
| | | | | | | | Immediates can be folded as long as the immediate is a vreg. Also undo commuting instructions if it didn't fold an immediate. llvm-svn: 307575
* [Hexagon] Fix check for HMOTF_ConstExtend operand flagKrzysztof Parzyszek2017-07-101-0/+24
| | | | | | This fixes https://llvm.org/PR33718. llvm-svn: 307566
* [WebAssembly] Use the correct size for MCFillFragmentSam Clegg2017-07-101-0/+14
| | | | | | | | | | | Summary: When implementing MCFillFragment, use the size of the fragment, rather than the size of the section. Patch by Dan Gohman Differential Revision: https://reviews.llvm.org/D35090 llvm-svn: 307565
* [Hexagon] Handle Hexagon-specific machine operand target flags in MIRKrzysztof Parzyszek2017-07-101-0/+36
| | | | llvm-svn: 307564
* [PPC CodeGen] Expand the bitreverse.i64 intrinsic.Tony Jiang2017-07-102-0/+161
| | | | | | | Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
* Fix invalid cast in instcombine UMul/ZExt idiomSerge Guelton2017-07-101-0/+29
| | | | | | | | | | | Fixes https://bugs.llvm.org/show_bug.cgi?id=25454 Do not assume IRBuilder creates Instruction where it can create Value. Do not assume idiom operands are constant, leave generalisation ot the IRBuilder. Differential Revision: https://reviews.llvm.org/D35114 llvm-svn: 307554
* [PowerPC] Reduce register pressure by not materializing a constant just for ↵Lei Huang2017-07-104-12/+49
| | | | | | | | | | | | | | | | | | | | | | | | use as an index register for X-Form loads/stores. For this example: float test (int *arr) { return arr[2]; } We currently generate the following code: li r4, 8 lxsiwax f0, r3, r4 xscvsxdsp f1, f0 With this patch, we will now generate: addi r3, r3, 8 lxsiwax f0, 0, r3 xscvsxdsp f1, f0 Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204 Differential Revision: https://reviews.llvm.org/D35027 llvm-svn: 307553
* [X86] Model 256-bit AVX instructions in the AMD Jaguar scheduler Part-1 ↵Andrew V. Tischenko2017-07-103-161/+161
| | | | | | | | | | | (PR28573). The new version of the model is definitely faster. Differential Revision: https://reviews.llvm.org/D35198 llvm-svn: 307552
* [LLVM] Get rid of white spaces in file names in a DebugInfo test. NFCEric Liu2017-07-102-3/+4
| | | | | | | | | | | | Summary: White spaces in file names are causing Phabricator/SVN to crash. Reviewers: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35206 llvm-svn: 307550
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-1023-119/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory accesses offset from frame indices may alias, e.g., we may merge write from function arguments passed on the stack when they are contiguous. As a result, when checking aliasing, we consider the underlying frame index's offset from the stack pointer. Static allocs are realized as stack objects in SelectionDAG, but its offset is not set until post-DAG causing DAGCombiner's alias check to consider access to static allocas to frequently alias. Modify isAlias to consider access between static allocas and access from other frame objects to be considered aliasing. Many test changes are included here. Most are fixes for tests which indirectly relied on our aliasing ability and needed to be modified to preserve their original intent. The remaining tests have minor improvements due to relaxed ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll which has a minor degradation dispite though the pre-legalized DAG is improved. Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand Reviewed By: rnk Subscribers: sdardis, nemanjai, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33345 llvm-svn: 307546
* [LoopUnrollRuntime] Remove strict assert about VMap requirementAnna Thomas2017-07-101-1/+42
| | | | | | | | | | | | | When unrolling under multiple exits which is under off-by-default option, the assert that checks for VMap entry in loop exit values is too strong. (assert if VMap entry did not exist, the value should be a constant). However, values derived from constants or from values outside loop, does not have a VMap entry too. Removed the assert and added a testcase showcasing the property for non-constant values. llvm-svn: 307542
* [PM] Enable registration of out-of-tree passes with PassBuilderPhilip Pfaffe2017-07-102-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a callback registration API to the PassBuilder, enabling registering out-of-tree passes with it. Through the Callback API, callers may register callbacks with the various stages at which passes are added into pass managers, including parsing of a pass pipeline as well as at extension points within the default -O pipelines. Registering utilities like `require<>` and `invalidate<>` needs to be handled manually by the caller, but a helper is provided. Additionally, adding passes at pipeline extension points is exposed through the opt tool. This patch adds a `-passes-ep-X` commandline option for every extension point X, which opt parses into pipelines inserted into that extension point. Reviewers: chandlerc Reviewed By: chandlerc Subscribers: lksbhm, grosser, davide, mehdi_amini, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D33464 llvm-svn: 307532
* This patch completely replaces the scheduling information for the ↵Gadi Haber2017-07-1012-896/+896
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SandyBridge architecture target by modifying the file X86SchedSandyBridge.td located under the X86 Target. The SandyBridge architects have provided us with a more accurate information about each instruction latency, number of uOPs and used ports and I used it to replace the existing estimated SNB instructions scheduling and to add missing scheduling information. Please note that the patch extensively affects the X86 MC instr scheduling for SNB. Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX. The updated and extended information about each instruction includes the following details: •static latency of the instruction •number of uOps from which the instruction consists of •all ports used by the instruction's' uOPs For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5: def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { let Latency = 9; let NumMicroOps = 6; let ResourceCycles = [1,2,2,1]; } def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>; def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>; Note that apart for the header, most of the X86SchedSandyBridge.td file was generated by a script. Reviewers: zvi, chandlerc, RKSimon, m_zuckerman, craig.topper, igorb Differential Revision: https://reviews.llvm.org/D35019#inline-304691 llvm-svn: 307529
* [GlobalISel][X86] Support G_LOAD/G_STORE i1.Igor Breger2017-07-103-0/+52
| | | | | | | | | | | | | | Summary: Support G_LOAD/G_STORE i1. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35178 llvm-svn: 307527
* [GlobalISel][X86] extend G_ZEXT support.Igor Breger2017-07-103-1/+270
| | | | | | | | | | | | | | | | | Summary: Mark G_ZEXT/G_SEXT i1 to i8/i16, i8 to i16 as legal. Support G_ZEXT i1 to i8/i16 instruction selection ( C++ code). This patch requred to support G_LOAD/G_STORE i1. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D35177 llvm-svn: 307526
* [ArgumentPromotion] Change use of removed argument in llvm.dbg.value to undefMikael Holmen2017-07-101-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This solves PR33641. When removing a dead argument we must also handle possibly existing calls to llvm.dbg.value that use the removed argument. Now we change the use of the otherwise dead argument to an undef for some other pass to cleanup later. If the calls are left untouched, they will later on cause errors: "function-local metadata used in wrong function" since the ArgumentPromotion rewrites the code by creating a new function with the wanted signature, but the metadata is not recreated so the new function may then erroneously use metadata from the old function. Reviewers: mstorsjo, rnk, arsenm Reviewed By: rnk Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D34874 llvm-svn: 307521
* [X86] Relax an assertion when legalizing vector types.Davide Italiano2017-07-091-0/+16
| | | | | | | | | | | | | | WidenVSELECTAndMask can fold (and it folds in this case) so we get a BUILD_VECTOR of constants as mask. convertMask() seems to work fine when the input is a vector of constants, and we still need to call it to extend/add elements at the end. but the current code just asserts on anything but a SETCC or AND/OR/XOR of 2xSETCC. This change was discussed briefly with Simon Pilgrim, who also suggests we might consider dropping this assertion in the future. Fixes PR33715. llvm-svn: 307508
* [AVR] Fix test errors due to tied operands not matchingDylan McKay2017-07-095-7/+7
| | | | | | Broken due to r307259. llvm-svn: 307503
* Handle ConstantExpr correctly in SelectionDAGBuilderSimon Pilgrim2017-07-091-0/+18
| | | | | | | | | | | | This change fixes a bug in SelectionDAGBuilder::visitInsertValue and SelectionDAGBuilder::visitExtractValue where constant expressions (InsertValueConstantExpr and ExtractValueConstantExpr) would be treated as non-constant instructions (InsertValueInst and ExtractValueInst). This bug resulted in an incorrect memory access, which manifested as an assertion failure in SDValue::SDValue. Fixes PR#33094. Submitted on behalf of @Praetonus (Benoit Vey) Differential Revision: https://reviews.llvm.org/D34538 llvm-svn: 307502
* [X86][AVX512] Regenerate AVX512VL comparison tests. Simon Pilgrim2017-07-092-4686/+47145
| | | | | | Show poor codegen on KNL targets as mentioned on D35179 llvm-svn: 307500
* [PM] Fix a nasty bug in the new PM where we failed to properlyChandler Carruth2017-07-091-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | invalidation of analyses when merging SCCs. While I've added a bunch of testing of this, it takes something much more like the inliner to really trigger this as you need to have partially-analyzed SCCs with updates at just the right time. So I've added a direct test for this using the inliner and verifying the domtree. Without the changes here, this test ends up finding a stale dominator tree. However, to handle this properly, we need to invalidate analyses *before* merging the SCCs. After talking to Philip and Sanjoy about this they convinced me this was the right approach. To do this, we need a callback mechanism when merging SCCs so we can observe the cycle that will be merged before the merge happens. This API update ended up being surprisingly easy. With this commit, the new PM passes the test-suite again. It hadn't since MemorySSA was enabled for EarlyCSE as that also will find this bug very quickly. llvm-svn: 307498
* [GlobalISel][X86] Add legalizer tests for G_LOAD/G_STORE operations. NFC.Igor Breger2017-07-091-0/+100
| | | | llvm-svn: 307494
* [FastISel] fix a fallback diagnostic.Igor Breger2017-07-091-1/+18
| | | | | | | | | | | | | | Summary: FastISel was marked as failed in case instruction selection succeeded. Reviewers: qcolombet, zvi, rovka, ab Reviewed By: zvi Subscribers: javed.absar, ab, qcolombet, bogner, llvm-commits Differential Revision: https://reviews.llvm.org/D34438 llvm-svn: 307489
* fix trivial typos; NFCHiroshi Inoue2017-07-091-1/+1
| | | | | | sucessor -> successor llvm-svn: 307488
* [PM] Finish implementing and fix a chain of bugs uncovered by testingChandler Carruth2017-07-091-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the invalidation propagation logic from an SCC to a Function. I wrote the infrastructure to test this but didn't actually use it in the unit test where it was designed to be used. =[ My bad. Once I actually added it to the test case I discovered that it also hadn't been properly implemented, so I've implemented it. The logic in the FAM proxy for an SCC pass to propagate invalidation follows the same ideas as the FAM proxy for a Module pass, but the implementation is a bit different to reflect the fact that it is forwarding just for an SCC. However, implementing this correctly uncovered a surprising "bug" (it was conservatively correct but relatively very expensive) in how we handle invalidation when splitting one SCC into multiple SCCs. We did an eager invalidation when in reality we should be deferring invaliadtion for the *current* SCC to the CGSCC pass manager and just invaliating the newly constructed SCCs. Otherwise we end up invalidating too much too soon. This was exposed by the inliner test case that I've updated. Now, we invalidate *just* the split off '(test1_f)' SCC when doing the CG update, and then the inliner finishes and invalidates the '(test1_g, test1_h)' SCC's analyses. The first few attempts at fixing this hit still more bugs, but all of those are covered by existing tests. For example, the inliner should also preserve the FAM proxy to avoid unnecesasry invalidation, and this is safe because the CG update routines it uses handle any necessary adjustments to the FAM proxy. Finally, the unittests for the CGSCC pass manager needed a bunch of updates where we weren't correctly preserving the FAM proxy because it hadn't been fully implemented and failing to preserve it didn't matter. Note that this doesn't yet fix the current crasher due to MemSSA finding a stale dominator tree, but without this the fix to that crasher doesn't really make any sense when testing because it relies on the proxy behavior. llvm-svn: 307487
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