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* [X86][AVX512]Improving shuffle lowering by using AVX-512 EXPAND* instructions Michael Zuckerman2017-01-101-0/+333
| | | | | | | | | | | | | | | | | This patch fix PR31351: https://llvm.org/bugs/show_bug.cgi?id=31351 1. This patch adds new type of shuffle lowering 2. We can use the expand instruction, When the shuffle pattern is as following: { 0*a[0]0*a[1]...0*a[n] , n >=0 where a[] elements in a ascending order}. Reviewers: 1. igorb 2. guyblank 3. craig.topper 4. RKSimon Differential Revision: https://reviews.llvm.org/D28352 llvm-svn: 291584
* [SimplifyLibCalls] Propagate fast math flags while optimizing pow().Davide Italiano2017-01-101-28/+28
| | | | llvm-svn: 291577
* [AArch64] Add support for lowering bitreverse to the rbit instruction.Chad Rosier2017-01-102-24/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D28379 llvm-svn: 291575
* [mips] Fix Mips MSA instrinsicsSimon Dardis2017-01-102-0/+2957
| | | | | | | | | | | | | | | | The usage of some MIPS MSA instrinsics that took immediates could crash LLVM during lowering. This patch addresses that behaviour. Crucially this patch also makes the use of intrinsics with out of range immediates as producing an internal error. The ld,st instrinsics would trigger an assertion failure for MIPS64 as their lowering would attempt to add an i32 offset to a i64 pointer. Reviewers: vkalintiris, slthakur Differential Revision: https://reviews.llvm.org/D25438 llvm-svn: 291571
* [mips] Honour -mno-odd-spreg for vector splat (again)Simon Dardis2017-01-101-0/+55
| | | | | | | | | | | | | | | | | | | | Previous the lowering of FILL_FW would use the MSA128W register class when performing a vector splat. Instead it should be honouring -mno-odd-spreg and only use the even registers when performing a splat from word to vector register. Logical follow-on from r230235. This fixes PR/31369. A previous commit was missing the test case and had another differential in it. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D28373 llvm-svn: 291566
* RuntimeDyldELF: implement R_AARCH64_PREL64 relocEugene Leviant2017-01-102-1/+9
| | | | | | Differential revision: https://reviews.llvm.org/D28122 llvm-svn: 291558
* [ObjectYAML] Missed one mixup in the debug_line testChris Bieneman2017-01-101-1/+0
| | | | llvm-svn: 291547
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-102-0/+648
| | | | | | | | | | | | | | One more try... relanding r291541 with a fix to properly gate MaxOpsPerInst on DWARF version. Description from r291541: This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly. Original description: This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291546
* AMD family 17h (znver1) enablementCraig Topper2017-01-104-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This item is linked to clang review item https://reviews.llvm.org/D28018 Patch by Ganesh Gopalasubramanian Reviewers: RKSimon, craig.topper Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28017 llvm-svn: 291543
* Revert "[ObjectYAML] Support for DWARF line tables"Chris Bieneman2017-01-102-650/+0
| | | | | | | | | | This reverts commit r291541. Still failing on a bot: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47224/steps/test_llvm/logs/stdio llvm-svn: 291542
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-102-0/+650
| | | | | | | | | | This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly. Original description: This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291541
* [XRay] Use regular expression for finding symbolsDean Michael Berris2017-01-101-4/+4
| | | | | | | | Un-break the test in Windows. Follow-up on D24376. llvm-svn: 291538
* [StructurizeCfg] Update dominator info.Serge Pavlov2017-01-101-1/+1
| | | | | | | | | | | | | | In some cases StructurizeCfg updates root node, but dominator info remains unchanges, it causes crash when expensive checks are enabled. To cope with this problem a new method was added to DominatorTreeBase that allows adding new root nodes, it is called in StructurizeCfg to put dominator tree in sync. This change fixes PR27488. Differential Revision: https://reviews.llvm.org/D28114 llvm-svn: 291530
* [XRay] Implement `llvm-xray convert` -- trace file conversionDean Michael Berris2017-01-1010-0/+134
| | | | | | | | | | | | | | | | | | | | This is the second part of a multi-part change to define additional subcommands to the `llvm-xray` tool. This change defines a conversion subcommand to take XRay log files, and turns them from one format to another (binary or YAML). This currently only supports the first version of the log file format, defined in the compiler-rt runtime. Depends on D21987. Reviewers: dblaikie, echristo Subscribers: mehdi_amini, dberris, beanz, llvm-commits Differential Revision: https://reviews.llvm.org/D24376 llvm-svn: 291529
* Commit a test for match-full-lines.James Y Knight2017-01-092-14/+53
| | | | | | | | | | | I unfortunately neglected to add it in r260540, but it has been sitting in my working dir ever since. D'oh. Modified to work with r290069, which made the CHECK patterns themselves whitespace-sensitive as well, and remove the test added then, as this tests both strict and non-strict modes. llvm-svn: 291499
* [X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift testsSimon Pilgrim2017-01-097-1/+842
| | | | llvm-svn: 291488
* [SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).Davide Italiano2017-01-091-1/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D28479 llvm-svn: 291486
* PeepholeOptimizer: Do not replace SubregToReg(bitcast like)Matthias Braun2017-01-091-0/+40
| | | | | | | | | | | While we can usually replace bitcast like instructions (MachineInstr::isBitcast()) with a COPY this is not legal if any of the users uses SUBREG_TO_REG to assert the upper bits of the result are zero. Differential Revision: https://reviews.llvm.org/D28474 llvm-svn: 291483
* Drive by typo fixMatthias Braun2017-01-092-2/+2
| | | | llvm-svn: 291482
* Revert r291092 because it introduces a crash.Michael Kuperstein2017-01-091-107/+0
| | | | | | See PR31589 for details. llvm-svn: 291478
* X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.Vyacheslav Klochkov2017-01-091-0/+129
| | | | | | Differential Revision: https://reviews.llvm.org/D28087 llvm-svn: 291473
* [InstCombine] add test to show missed fold using llvm.assume; NFCSanjay Patel2017-01-091-0/+13
| | | | llvm-svn: 291472
* Revert "[ObjectYAML] Support for DWARF line tables"Chris Bieneman2017-01-092-650/+0
| | | | | | | | This reverts commit r291470 due to failing bots: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio llvm-svn: 291471
* [ObjectYAML] Support for DWARF line tablesChris Bieneman2017-01-092-0/+650
| | | | | | This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly. llvm-svn: 291470
* [InstCombine] regenerate checks; NFCSanjay Patel2017-01-091-13/+12
| | | | llvm-svn: 291469
* [ValueTracking] regenerate checks; NFCSanjay Patel2017-01-091-7/+15
| | | | llvm-svn: 291468
* [InstCombine] regenerate checks; NFCSanjay Patel2017-01-091-66/+63
| | | | llvm-svn: 291464
* [InstCombine] remove unnecessary attribute comments from test files; NFCSanjay Patel2017-01-092-21/+0
| | | | llvm-svn: 291463
* [LV] Fix-up external IV users after updating dominator treeMatthew Simpson2017-01-091-0/+45
| | | | | | | | | | | | | This patch delays the fix-up step for external induction variable users until after the dominator tree has been properly updated. This should fix PR30742. The SCEVExpander in InductionDescriptor::transform can generate code in the wrong location if the dominator tree is not up-to-date. We should work towards keeping the dominator tree up-to-date throughout the transformation. Reference: https://llvm.org/bugs/show_bug.cgi?id=30742 Differential Revision: https://reviews.llvm.org/D28168 llvm-svn: 291462
* AMDGPU: Add Assert[SZ]Ext during argument load creationMatt Arsenault2017-01-091-75/+97
| | | | | | | | | | | For i16 zeroext arguments when i16 was a legal type, the known bits information from the truncate was lost. Insert a zeroext so the known bits optimizations work with the 32-bit loads. Fixes code quality regressions vs. SI in min.ll test. llvm-svn: 291461
* Intrinsic::Bitreverse is safe to speculateXin Tong2017-01-091-0/+27
| | | | | | | | | | | | Summary: Intrinsic::Bitreverse is safe to speculate Reviewers: hfinkel, mkuper, arsenm, jmolloy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28471 llvm-svn: 291456
* [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an ↵Simon Pilgrim2017-01-096-318/+279
| | | | | | | | | | extend+shift+truncate pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets. Cost model updates to follow. llvm-svn: 291451
* [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate ↵Simon Pilgrim2017-01-096-145/+56
| | | | | | | | | | pattern. Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw). Cost model updates to follow. llvm-svn: 291445
* [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift testsSimon Pilgrim2017-01-096-84/+215
| | | | llvm-svn: 291444
* [SelectionDAG] Fix in legalization of UMAX/SMAX/UMIN/SMIN. Solves PR31486.Bjorn Pettersson2017-01-091-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Originally i64 = umax t8, Constant:i64<4> was expanded into i32,i32 = umax Constant:i32<0>, Constant:i32<0> i32,i32 = umax t7, Constant:i32<4> Now instead the two produced umax:es return i32 instead of i32, i32. Thanks to Jan Vesely for help with the test case. Patch by mikael.holmen at ericsson.com Reviewers: bogner, jvesely, tstellarAMD, arsenm Subscribers: test, wdng, RKSimon, arsenm, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D28135 llvm-svn: 291441
* RuntimeDyldELF: add missing test cases for AArch64Eugene Leviant2017-01-092-3/+43
| | | | llvm-svn: 291438
* RuntimeDyldELF: don't create thunk if not neededEugene Leviant2017-01-091-0/+14
| | | | | | | | | | | | | This patch doesn't create thunk for branch operation when following conditions are met: - Architecture is AArch64 - Relocation target is in the same object file - Relocation target is close enough to be encoded in immediate offset In such case we branch directly to the target instead of branching to thunk Differential revision: https://reviews.llvm.org/D28108 llvm-svn: 291431
* [PM] Teach SCEV to invalidate itself when its dependencies becomeChandler Carruth2017-01-091-0/+70
| | | | | | | | | | | | | invalid. This fixes use-after-free bugs that will arise with any interesting use of SCEV. I've added a dedicated test that works diligently to trigger these kinds of bugs in the new pass manager and also checks for them explicitly as well as triggering ASan failures when things go squirly. llvm-svn: 291426
* NewGVN: Fix PR 31573, a failure to verify memory congruency due toDaniel Berlin2017-01-091-0/+42
| | | | | | | not excluding ourselves when checking if any equivalent stores exist. llvm-svn: 291421
* [AVX-512] Change another pattern that was using BLENDM to use masked moves. ↵Craig Topper2017-01-092-23/+23
| | | | | | A future patch will conver it back to BLENDM if its beneficial to register allocation. llvm-svn: 291419
* [AVX-512] Add patterns to use a zero masked VPTERNLOG instruction for ↵Craig Topper2017-01-0911-217/+153
| | | | | | | | vselects of all ones and all zeros. Previously we emitted a VPTERNLOG and a separate masked move. llvm-svn: 291415
* [MemDep] NFC walk invariant.group graph only downPiotr Padlewski2017-01-082-0/+104
| | | | | | | | | | | | | | Summary: By using stripPointerCasts we can get to the root value and then walk down the bitcast graph Reviewers: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28181 llvm-svn: 291405
* [AVX-512] If avx512dq is available use vpmovm2d/vpmovm2q instead of vselect ↵Craig Topper2017-01-081-28/+88
| | | | | | of zeroes/ones when handling sign extends of i1 without VLX. llvm-svn: 291402
* [X86] Add avx512bw and avx512dq command lines to the vector compare results ↵Craig Topper2017-01-081-1498/+4602
| | | | | | | | test. This is preparation for improving a case with avx512dq. llvm-svn: 291401
* [x86] fix usage of stale operands when lowering selectSanjay Patel2017-01-081-5/+1
| | | | | | | | | | | | | | | | | | | | | I noticed this problem as part of the ongoing attempt to canonicalize min/max ops in IR. The debug output shows nodes like this: t4: i32 = xor t2, Constant:i32<-1> t21: i8 = setcc t4, Constant:i32<0>, setlt:ch t14: i32 = select t21, t4, Constant:i32<-1> And because the select is holding onto the t4 (xor) node while EmitTest creates a new x86-specific xor node, the lowering results in: t4: i32 = xor t2, Constant:i32<-1> t25: i32,i32 = X86ISD::XOR t2, Constant:i32<-1> t28: i32,glue = X86ISD::CMOV Constant:i32<-1>, t4, Constant:i8<15>, t25:1 Differential Revision: https://reviews.llvm.org/D28374 llvm-svn: 291392
* [CostModel][X86] Fixed vXi8 uniform shift costs.Simon Pilgrim2017-01-085-39/+45
| | | | | | | | | | The 'fast' costs should only work for shifts by uniform constants (uniform non-constant are lowered using the slow default implementation). Logical shifts were not taking into account that we must mask the psrlw result, so the costs needed to be doubled. Added missing AVX2/AVX512BW costs as well. llvm-svn: 291391
* [CostModel][X86] Moved legal uniform shift costs earlier.Simon Pilgrim2017-01-082-8/+5
| | | | | | XOP was prematurely matching, doubling the cost of ashr/lshr uniform shifts. llvm-svn: 291390
* [AVR] Implement TargetLoweing::getRegisterByNameDylan McKay2017-01-071-0/+17
| | | | | | | This allows the use of the 'read_register' intrinsics used by clang's named register globals features. llvm-svn: 291375
* [CostModel][X86] Update SSE41/AVX1 vXi32 SHL costsSimon Pilgrim2017-01-071-12/+12
| | | | | | SSE41 provides pmulld which allows the simpler pslld/paddd/cvttps2dq/pmulld pattern than SSE2's use of pmuludq. llvm-svn: 291372
* [AVX-512] Remove patterns from the other VBLENDM instructions. They are all ↵Craig Topper2017-01-0712-172/+300
| | | | | | | | redundant with masked move instructions. We should probably teach the two address instruction pass to turn masked moves into BLENDM when its beneficial to the register allocator. llvm-svn: 291371
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