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* [llvm-profdata] Improve error messaging when merging mismatched profile dataNathan Slingerland2015-11-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change tries to make the root cause of instrumented profile data merge failures clearer. Previous: $ llvm-profdata merge test_0.profraw test_1.profraw -o test_merged.profdata test_1.profraw: foo: Function count mismatch test_1.profraw: bar: Function count mismatch test_1.profraw: baz: Function count mismatch ... Changed: $ llvm-profdata merge test_0.profraw test_1.profraw -o test_merged.profdata test_1.profraw: foo: Function basic block count change detected (counter mismatch) Make sure that all profile data to be merged is generated from the same binary. test_1.profraw: bar: Function basic block count change detected (counter mismatch) test_1.profraw: baz: Function basic block count change detected (counter mismatch) ... Reviewers: dnovillo, davidxl, bogner Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14739 llvm-svn: 253384
* [X86][SSE] Share AVX1/AVX2 shuffle tests with AVX512 where possibleSimon Pilgrim2015-11-172-323/+504
| | | | llvm-svn: 253379
* [WinEH] Move WinEHFuncInfo from MachineModuleInfo to MachineFunctionReid Kleckner2015-11-172-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that there is a one-to-one mapping from MachineFunction to WinEHFuncInfo, we don't need to use a DenseMap to select the right WinEHFuncInfo for the current funclet. The main challenge here is that X86WinEHStatePass is an IR pass that doesn't have access to the MachineFunction. I gave it its own WinEHFuncInfo object that it uses to calculate state numbers, which it then throws away. As long as nobody creates or removes EH pads between this pass and SDAG construction, we will get the same state numbers. The other thing X86WinEHStatePass does is to mark the EH registration node. Instead of communicating which alloca was the registration through WinEHFuncInfo, I added the llvm.x86.seh.ehregnode intrinsic. This intrinsic generates no code and simply marks the alloca in use. Reviewers: JCTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14668 llvm-svn: 253378
* dwarfdump: Reference the appropriate line table segment when dumping dwp filesDavid Blaikie2015-11-171-2/+14
| | | | | | Also improves .dwo type unit dumping which didn't handle this either. llvm-svn: 253377
* [EH] Keep filter clauses for types that have been caught.Andrew Kaylor2015-11-171-4/+7
| | | | | | | | The instruction combiner previously removed types from filter clauses in Landing Pad instructions if the type had previously been seen in a catch clause. This is incorrect and prevents unexpected exception handlers from rethrowing the caught type. Differential Revision: http://reviews.llvm.org/D14669 llvm-svn: 253370
* Vector of pointers in function attributes calculationElena Demikhovsky2015-11-171-0/+38
| | | | | | | | | While setting function attributes we check all instructions that may access memory. For a call instruction we check all arguments. The special check is required for pointers. I added vector-of-pointers to the call arguments types that should be checked. Differential Revision: http://reviews.llvm.org/D14693 llvm-svn: 253363
* enabling sancov tests on linux x86_64 onlyMike Aizatsky2015-11-173-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D14728 llvm-svn: 253354
* [ARM] Don't pessimize i32 vselect.Charlie Turner2015-11-172-8/+9
| | | | | | | | | | | | | | | | | | The underlying issues surrounding codegen for 32-bit vselects have been resolved. The pessimistic costs for 64-bit vselects remain due to the bad scalarization that is still happening there. I tested this on A57 in T32, A32 and A64 modes. I saw no regressions, and some improvements. From my benchmarks, I saw these improvements in A57 (T32) spec.cpu2000.ref.177_mesa 5.95% lnt.SingleSource/Benchmarks/Shootout/strcat 12.93% lnt.MultiSource/Benchmarks/MiBench/telecomm-CRC32/telecomm-CRC32 11.89% I also measured A57 A32, A53 T32 and A9 T32 and found no performance regressions. I see much bigger wins in third-party benchmarks with this change Differential Revision: http://reviews.llvm.org/D14743 llvm-svn: 253349
* [AArch64] Promote f16 SELECT_CC CC operands when op is legal.Ahmed Bougacha2015-11-171-0/+27
| | | | | | | | | | | | | | | | SELECT_CC has the nasty property of having operands with unrelated types. So if you do something like: f32 = select_cc f16, f16, f32, f32, cc You'd only look for the action for <select_cc, f32>, but never f16. If the types are all legal, but the op isn't (as for f16 on AArch64, or for f128 on x86_64/AArch64?), then you get into trouble. For f128, we have softenSetCCOperands to handle this case. Similarly, for f16, we can directly promote the CC operands. llvm-svn: 253344
* Update DebugInfo tests for the change in DEBUG_VALUE output in r253338.Dan Gohman2015-11-177-9/+9
| | | | llvm-svn: 253340
* Lower statepoints with multi-def targets.Pat Gavlin2015-11-171-1/+19
| | | | | | | | | | Statepoint lowering currently expects that the target method of a statepoint only defines a single value. This precludes using statepoints with ABIs that return values in multiple registers (e.g. the SysV AMD64 ABI). This change adds support for lowering statepoints with mutli-def targets. llvm-svn: 253339
* Use TargetRegisterInfo for printing MachineOperand register commentsDan Gohman2015-11-178-10/+10
| | | | | | | | | | | | | | | | Several places in AsmPrinter.cpp print comments describing MachineOperand registers using MCRegisterInfo, which uses MCOperand-oriented names. This doesn't work for targets that use virtual registers exclusively, as WebAssembly does, since virtual registers are represented and printed differently. This patch preserves what seems to be the spirit of r229978, avoiding the use of TM.getSubtargetImpl(), while still using MachineOperand-oriented printing for MachineOperands. Differential Revision: http://reviews.llvm.org/D14709 llvm-svn: 253338
* [ARM] Match VABDL from log2 shuffles.Charlie Turner2015-11-171-0/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D14664 llvm-svn: 253334
* [mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, ↵Zlatko Buljan2015-11-174-0/+48
| | | | | | | | EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions Differential Revision: http://reviews.llvm.org/D14174 llvm-svn: 253332
* [mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, ↵Zlatko Buljan2015-11-174-0/+36
| | | | | | | | SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions Differential Revision: http://reviews.llvm.org/D14114 llvm-svn: 253329
* [Assembler] Make fatal assembler errors non-fatalOliver Stannard2015-11-1729-91/+199
| | | | | | | | | | | | | | Currently, if the assembler encounters an error after parsing (such as an out-of-range fixup), it reports this as a fatal error, and so stops after the first error. However, for most of these there is an obvious way to recover after emitting the error, such as emitting the fixup with a value of zero. This means that we can report on all of the errors in a file, not just the first one. MCContext::reportError records the fact that an error was encountered, so we won't actually emit an object file with the incorrect contents. Differential Revision: http://reviews.llvm.org/D14717 llvm-svn: 253328
* [Assembler] Allow non-fatal errors after parsingOliver Stannard2015-11-172-2/+2
| | | | | | | | | | | | | | | | | This adds reportError to MCContext, which can be used as an alternative to reportFatalError when the assembler wants to try to continue processing the rest of the file after the error is reported, so that all of the errors ina file can be reported. It records the fact that an error was encountered, so we can avoid emitting an object file if any errors occurred. This patch doesn't add any uses of this function (a later patch will convert most uses of reportFatalError to use it), but there is a small functional change: we use the SourceManager to print the error message, even if we have a null SMLoc. This means that we get a SourceManager-style message, with the file and line information shown as <unknown>, rather than the "LLVM ERROR" style used by report_fatal_error. llvm-svn: 253327
* [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, ↵Zlatko Buljan2015-11-174-0/+40
| | | | | | | | PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions Differential Revision: http://reviews.llvm.org/D14279 llvm-svn: 253326
* AVX512 : regenerate the test file against trunk.Igor Breger2015-11-171-117/+478
| | | | | | Differential Revision: http://reviews.llvm.org/D14742 llvm-svn: 253321
* Added microMIPSDSPr1 assembler and disassembler tests to existing ↵Zlatko Buljan2015-11-174-10/+82
| | | | | | microMIPSDSPr2 test files. llvm-svn: 253320
* Drop prelink support.Rafael Espindola2015-11-177-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way prelink used to work was * The compiler decides if a given section only has relocations that are know to point to the same DSO. If so, it names it .data.rel.ro.local<something>. * The static linker puts all of these together. * The prelinker program assigns addresses to each library and resolves the local relocations. There are many problems with this: * It is incompatible with address space randomization. * The information passed by the compiler is redundant. The linker knows if a given relocation is in the same DSO or not. If could sort by that if so desired. * There are newer ways of speeding up DSO (gnu hash for example). * Even if we want to implement this again in the compiler, the previous implementation is pretty broken. It talks about relocations that are "resolved by the static linker". If they are resolved, there are none left for the prelinker. What one needs to track is if an expression will require only dynamic relocations that point to the same DSO. At this point it looks like the prelinker is an historical curiosity. For example, fedora has retired it because it failed to build for two releases (http://pkgs.fedoraproject.org/cgit/prelink.git/commit/?id=eb43100a8331d91c801ee3dcdb0a0bb9babfdc1f) This patch removes support for it. That is, it stops printing the ".local" sections. llvm-svn: 253280
* dwarfdump: Use the index to find the right abbrev offset in DWP filesDavid Blaikie2015-11-172-7/+24
| | | | llvm-svn: 253277
* [WebAssembly] Fix printing of global operandsDerek Schuff2015-11-171-0/+7
| | | | | | | | | | This was regressed in r252656 which wasn't quite NFC. Instead of using a custom instruction as before, use a pattern to select CONST_I32 for the global addrs. Differential Revision: http://reviews.llvm.org/D14587 llvm-svn: 253276
* [PRE] Preserve !invariant.load metadataPhilip Reames2015-11-171-0/+17
| | | | | | Spoted via inspection. Test case included. llvm-svn: 253275
* [WebAssembly] Fix function return type printingDerek Schuff2015-11-161-0/+21
| | | | | | | | | | | Summary: Previously return type information for a function was derived from return dag nodes. But this didn't work for dags with != return node. So instead compute it directly from the LLVM function as is done for imports. Differential Revision: http://reviews.llvm.org/D14593 llvm-svn: 253251
* [WebAssembly] Reverse the order of operands for br_ifDerek Schuff2015-11-161-11/+11
| | | | | | | | | | | | Summary: This is to match the new version in the spec Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D14519 llvm-svn: 253249
* Find available scratch register to use in function prologue and epilogue as ↵Kit Barton2015-11-164-31/+366
| | | | | | | part of shrink wrapping. Phabricator: http://reviews.llvm.org/D13955 llvm-svn: 253247
* [WinEH] Don't let UnwindHelp alias the return addressReid Kleckner2015-11-162-0/+50
| | | | | | | | | | | On top of that, don't bother allocating and initializing UnwindHelp if we don't have any funclets. Currently we always use RBP as our frame pointer when funclets are present, so this change makes it impossible to come here without any fixed stack objects. Fixes PR25533. llvm-svn: 253245
* Add intermediate subtract instructions to reassociation worklist.Owen Anderson2015-11-168-17/+48
| | | | | | | | | | We sometimes create intermediate subtract instructions during reassociation. Adding these to the worklist to revisit exposes many additional reassociation opportunities. Patch by Aditya Nandakumar. llvm-svn: 253240
* [LoopStrengthReduce] Don't increment iterator past the end of the BBDavid Majnemer2015-11-161-0/+51
| | | | | | | | | | | We tried to move the insertion point beyond instructions like landingpad and cleanuppad. However, we *also* tried to move past catchpad. This is problematic because catchpad is also a terminator. This fixes PR25541. llvm-svn: 253238
* [mips] Disable code generation through FastISel for MIPS32R6.Vasileios Kalintiris2015-11-161-0/+27
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
* [ARM,AArch64] Store source location of asm constant pool entriesOliver Stannard2015-11-162-0/+10
| | | | | | | | | | Storing the source location of the expression that created a constant pool entry allows us to emit better error messages if we later discover that the expression cannot be represented by a relocation. Differential Revision: http://reviews.llvm.org/D14646 llvm-svn: 253220
* [ARM,AArch64] Store source location for values in assembly filesOliver Stannard2015-11-162-0/+10
| | | | | | | | | | | The MCValue class can store a SMLoc to allow better error messages to be emitted if an error is detected after parsing. The ARM and AArch64 assembly parsers were not setting this, so error messages did not have source information. Differential Revision: http://reviews.llvm.org/D14645 llvm-svn: 253219
* [mips][ias] Remove spurious ';' from inline assembly test.Daniel Sanders2015-11-161-4/+4
| | | | | | | IAS will not emit it. NFC at the moment but will prevent a test failure once IAS is enabled. llvm-svn: 253210
* [mips][ias] Accept $31 or $ra in hf16call32.ll. IAS prints the latter.Daniel Sanders2015-11-161-14/+14
| | | | | | NFC at the moment, but it will prevent a test failure once IAS is enabled. llvm-svn: 253209
* [mips][ias] Allow whitespace after commas in inlineasm*.ll tests.Daniel Sanders2015-11-164-59/+59
| | | | | | | IAS always prints whitespace after a comma. NFC at the moment but this will prevent failures when IAS is enabled. llvm-svn: 253208
* Handle ARMv6KZ namingArtyom Skrobov2015-11-162-40/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
* Properly check if a CMPZ node is in fact comparing against zeroJames Molloy2015-11-161-0/+11
| | | | | | | | This was left implicit and never ever checked, which means we could have a CMPZ against some non-zero value and we were carrying on with BFI conversion regardless. Caught by Oliver Stannard using csmith; regression test added. llvm-svn: 253195
* Don't generate discriminators for calls to debug intrinsicsPavel Labath2015-11-161-0/+30
| | | | | | | | | | | | | | Summary: This fails a check in Verifier.cpp, which checks for location matches between the declared variable and the !dbg attachments. Reviewers: dnovillo, dblaikie, danielcdh Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14657 llvm-svn: 253194
* [AArch64] ldr= pseudo-instruction silently ignored if register invalidOliver Stannard2015-11-161-0/+18
| | | | | | | | | | | | | The AArch64 assembler was silently ignoring instructions like this: ldr foo, =bar AArch64AsmParser::parseOperand was returning true as the parse failed, but was not calling AArch64AsmParser::Error to report this to the user, so the instruction was ignored without printing an error message. Differential Revision: http://reviews.llvm.org/D14651 llvm-svn: 253193
* Fix r253186 test caseKeno Fischer2015-11-161-1/+2
| | | | | | | Referencing a DILocation whose scope is a different subprogram causes an assertion failure. llvm-svn: 253187
* [DIBuilder] Make createReferenceType take size and alignKeno Fischer2015-11-161-0/+46
| | | | | | | | | | | | | | | | | | Summary: Since we're passing references to dbg.value as pointers, we need to have the frontend properly declare their sizes and alignments (as it already does for regular pointers) in preparation for my upcoming patch to have the verifer check that the sizes agree. Also augment the backend logic that skips actually emitting this information into DWARF such that it also handles reference types. Reviewers: aprantl, dexonsmith, dblaikie Subscribers: dblaikie, llvm-commits Differential Revision: http://reviews.llvm.org/D14275 llvm-svn: 253186
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-165-0/+384
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* [Sink] Don't move landingpadsKeno Fischer2015-11-161-0/+33
| | | | | | | | | | | | | | | Summary: Moving landingpads into successor basic blocks makes the verifier sad. Teach Sink that much like PHI nodes and terminator instructions, landingpads (and cleanuppads, etc.) may not be moved between basic blocks. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14475 llvm-svn: 253182
* [GlobalOpt] Demote globals to locals more aggressivelyJames Molloy2015-11-153-2/+82
| | | | | | | | | | | | | | | | Global to local demotion can speed up programs that use globals a lot. It is particularly useful with LTO, when the entire call graph is known and most functions have been internalized. For a global to be demoted, it must only be accessed by one function and that function: 1. Must never recurse directly or indirectly, else the GV would be clobbered. 2. Must never rely on the value in GV at the start of the function (apart from the initializer). GlobalOpt can already do this, but it is hamstrung and only ever tries to demote globals inside "main", because C++ gives extra guarantees about how main is called - once and only once. In LTO mode, we can often prove the first property (if the function is internal by this point, we know enough about the callgraph to determine if it could possibly recurse). FunctionAttrs now infers the "norecurse" attribute for this reason. The second property can be proven for a subset of functions by proving that all loads from GV are dominated by a store to GV. This is conservative in the name of compile time - this only requires a DominatorTree which is fairly cheap in the grand scheme of things. We could do more fancy stuff with MemoryDependenceAnalysis too to catch more cases but this appears to catch most of the useful ones in my testing. llvm-svn: 253168
* Revert r253160.Igor Breger2015-11-155-384/+0
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* Fixed GEP visitor in the InstCombine pass.Elena Demikhovsky2015-11-151-0/+23
| | | | | | | | | | | | | The current implementation of GEP visitor in InstCombine fails with assertion on Vector GEP with mix of scalar and vector types, like this: getelementptr double, double* %a, <8 x i32> %i (It fails to create a "sext" from <8 x i32> to <8 x i64>) I fixed it and added some tests. Differential Revision: http://reviews.llvm.org/D14485 llvm-svn: 253162
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-155-0/+384
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* [WebAssembly] Make indentation consistent with the other testcases. NFC.Dan Gohman2015-11-142-14/+14
| | | | llvm-svn: 253149
* [WebAssembly] Support signext, zeroext, and several other function attributes.Dan Gohman2015-11-141-0/+76
| | | | llvm-svn: 253148
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