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* Revert "Add opt-viewer testing"Adam Nemet2017-11-2811-1121/+0
| | | | | | | | This reverts commit r319073. Bot fails with a mismatch that looks like pygments-generated HTML. llvm-svn: 319146
* [WebAssembly] Handle errors better in fast-isel.Dan Gohman2017-11-281-0/+54
| | | | | | | | | Fast-isel routines need to bail out in the case that fast-isel fails on the operands. This fixes https://bugs.llvm.org/show_bug.cgi?id=35064 llvm-svn: 319144
* [DAGCombine] Disable finding better chains for stores at O0Simon Dardis2017-11-284-60/+679
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unoptimized IR can have linear sequences of stores to an array, where the initial GEP for the first store is formed from the pointer to the array, and the GEP for each store after the first is formed from the previous GEP with some offset in an inductive fashion. The (large) resulting DAG when analyzed by DAGCombine undergoes an excessive number of combines as each store node is examined every time its' offset node is combined with any child of the offset. One of the transformations is findBetterNeighborChains which assists MergeConsecutiveStores. The former relies on repeated chain walking to do its' work, however MergeConsecutiveStores is disabled at O0 which makes the transformation redundant. Any optimization level other than O0 would invoke InstCombine which would resolve the chain of GEPs into flat base + offset GEP for each store which does not exhibit the repeated examination of each store to the array. Disabling this optimization fixes an excessive compile time issue (30~ minutes for the test case provided) at O0. Reviewers: niravd, craig.topper, t.p.northover Differential Revision: https://reviews.llvm.org/D40193 llvm-svn: 319142
* [X86] Make zero extend from v16i1/v8i1 to v16i8/v8i16/v16i16 not scalarize ↵Craig Topper2017-11-281-650/+34
| | | | | | under AVX512. llvm-svn: 319136
* [X86] Add command line without AVX512BW/AVX512VL to ↵Craig Topper2017-11-281-201/+845
| | | | | | bitcast-int-to-vector-bool-zext.ll. llvm-svn: 319135
* This reverts commit r319096 and r319097.Rafael Espindola2017-11-281-20/+0
| | | | | | | | | Revert "[SROA] Propagate !range metadata when moving loads." Revert "[Mem2Reg] Clang-format unformatted parts of this file. NFCI." Davide says they broke a bot. llvm-svn: 319131
* ARM: Fix PR32578Matthias Braun2017-11-281-0/+27
| | | | | | | | | | https://llvm.org/PR32578 I simplified and converted the reproducer into a lit test. Patch by Vedant Kumar! llvm-svn: 319130
* [WebAssembly] Fix trapping behavior in fptosi/fptoui.Dan Gohman2017-11-282-9/+172
| | | | | | | | | | | | This adds code to protect WebAssembly's `trunc_s` family of opcodes from values outside their domain. Even though such conversions have full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do not, and only return undef. This also implements the proposed non-trapping float-to-int conversion feature and uses that instead when available. llvm-svn: 319128
* SROA: Avoid creating a fragment expression that covers the entire variable.Adrian Prantl2017-11-281-0/+114
| | | | | | | | Fixes PR35416. https://bugs.llvm.org/show_bug.cgi?id=35416 llvm-svn: 319126
* [DAGCombiner] Don't combine aext(setcc) if the setcc is already using the ↵Craig Topper2017-11-271-1774/+1070
| | | | | | | | | | target's preferred result type. With AVX512 vXi1 types are legal so we shouldn't be extending them. This change is similar to existing code in the zext(setcc) combine. llvm-svn: 319120
* [X86] Teach getSetCCResultType to handle more than just SimpleVTs when ↵Craig Topper2017-11-271-1007/+57
| | | | | | | | looking at larger than 512-bit vectors. Which VTs are considered simple is determined by the superset of the legal types of all targets in LLVM. If we're looking at VTs that are going to be split down to 512-bits we should allow any VT not just simple ones since the simple list changes over time as new targets are added. llvm-svn: 319110
* [SROA] Propagate !range metadata when moving loads.Davide Italiano2017-11-271-0/+20
| | | | | | | | | | | | | This tries to propagate !range metadata to a pre-existing load when a load is optimized out. This is done instead of adding an assume because converting loads to and from assumes creates a lot of IR. Patch by Ariel Ben-Yehuda. Differential Revision: https://reviews.llvm.org/D37216 llvm-svn: 319096
* [PartiallyInlineLibCalls][x86] add TTI hook to allow sqrt inlining to depend ↵Sanjay Patel2017-11-272-20/+22
| | | | | | | | | | | on arg rather than result This should fix PR31455: https://bugs.llvm.org/show_bug.cgi?id=31455 Differential Revision: https://reviews.llvm.org/D28314 llvm-svn: 319094
* [AMDGPU] Update test nullptr.ll to use amdgiz environmentYaxun Liu2017-11-271-57/+63
| | | | | | | | | | This test needs to be manually updated since it is difficult to do it with script. Addr space 6 to 23 are only used by r600, therefore only check them for r600. Differential Revision: https://reviews.llvm.org/D40117 llvm-svn: 319092
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-271-0/+123
| | | | | | | | | | This patch adds a peep hole optimization to remove any redundant toc save instructions added as part of the call sequence for indirect calls. It removes any toc saves within a function that are dominated by another toc save. Differential Revision: https://reviews.llvm.org/D39736 llvm-svn: 319087
* Inliner: Don't mark notail calls with the 'tail' attributeArnold Schwaighofer2017-11-271-0/+15
| | | | | | | | | | | | enum TailCallKind { TCK_None = 0, TCK_Tail = 1, TCK_MustTail = 2, TCK_NoTail = 3 }; TCK_NoTail is greater than TCK_Tail so taking the min does not do the correct thing. rdar://35639547 llvm-svn: 319075
* Add opt-viewer testingAdam Nemet2017-11-2711-0/+1121
| | | | | | | | | | | | | | | Detects whether we have the Python modules (pygments, yaml) required by opt-viewer and hooks this up to REQUIRES. This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer testing). It's also related to https://github.com/apple/swift/pull/12938 and the idea is to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake. Differential Revision: https://reviews.llvm.org/D40202 llvm-svn: 319073
* [llvm-objcopy] Add --strip-all-gnu and change --strip-allJake Ehrlich2017-11-272-34/+63
| | | | | | | | | | | | | | GNU's --strip-all doesn't strip as aggressively as it could in general. Currently llvm-objcopy copies the exact behavoir of GNU's --strip-all. eu-strip is used as a drop in replacement for GNU strip/objcopy in many many places without issue. eu-strip removes non-allocated sections and keeps .gnu.warning* sections. Because --strip-all will likely be the most widely used stripping option we should make --strip-all as aggressive as it can safely be. Since we have evidence from eu-strip that this is a safe option we should allow it. For those that might still have an issue afterwards I've added --strip-all-gnu as an exact drop in replacement for GNU's --strip-all as well. llvm-svn: 319071
* [X86] Add avx512bw command lines to vselect-packss.llCraig Topper2017-11-271-36/+109
| | | | | | This shows several places where we fail to use masked move or blendm. llvm-svn: 319063
* [X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over ↵Craig Topper2017-11-272-802/+43
| | | | | | | | | | 512 bits long when AVX512 is enabled. Similar for vXi16/vXi8 with BWI. Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization. llvm-svn: 319059
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-271-0/+85
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* [Power9] Improvements to vector extract with variable index exploitationZaara Syeda2017-11-271-3/+3
| | | | | | | | | | This patch extends on to rL307174 to not use the power9 vector extract with variable index instructions when extracting word element 1. For such cases, the existing selection of MFVSRWZ provides a better sequence. Differential Revision: https://reviews.llvm.org/D38287 llvm-svn: 319049
* [llvm-dwarfdump] Display DW_AT_high_pc as absolute valueJonas Devlieghere2017-11-274-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | DWARF4 relative DW_AT_high_pc values are now displayed as absolute addresses. The relative value is only shown when explicitly dumping the forms, i.e. in show-form or verbose mode. ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x00000019) ``` becomes ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x0000000000000062) ``` Differential revision: https://reviews.llvm.org/D40317 rdar://35416943 llvm-svn: 319044
* [InstSimplify] add fcmp with negative constant tests; NFCSanjay Patel2017-11-271-0/+46
| | | | | | This is a superset of the tests proposed with D40012 to show another potential improvement. llvm-svn: 319041
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-2711-74/+78
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [X86] Add INVLPGA to the existing INVLPG schedulingSimon Pilgrim2017-11-271-10/+10
| | | | llvm-svn: 319031
* [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic2017-11-271-0/+62
| | | | | | | | | | | | | | | Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 llvm-svn: 319030
* [X86] Add scheduling tests for invlpg/invlpgaSimon Pilgrim2017-11-271-0/+84
| | | | llvm-svn: 319029
* [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic2017-11-274-0/+320
| | | | | | | | | | | | | | AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025
* [CGP] Fix handling of null pointer values in optimizeMemoryInstJohn Brawn2017-11-271-0/+52
| | | | | | | | | | | The current way that trivial addressing modes are detected incorrectly thinks that null pointers are non-trivial, leading to an infinite loop where we keep duplicating the same select. Fix this by aware of null when deciding if an addressing mode is trivial. Differential Revision: https://reviews.llvm.org/D40447 llvm-svn: 319019
* [ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov2017-11-273-6/+6
| | | | | | | | | | | | | | The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from. The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4). Differential revision: https://reviews.llvm.org/D40305 llvm-svn: 319014
* Update BTVER2 sched numbers for SSE42 string instructions.Andrew V. Tischenko2017-11-271-8/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D39846 llvm-svn: 319013
* [SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the ↵Craig Topper2017-11-271-351/+325
| | | | | | operands have already been split. llvm-svn: 319010
* [X86][3DNow] Add 3DNow! instruction itinerary and scheduling classesSimon Pilgrim2017-11-261-48/+48
| | | | llvm-svn: 319005
* [X86][SSE] Add SSE42 tests to the clear upper testsSimon Pilgrim2017-11-261-352/+593
| | | | llvm-svn: 319003
* [X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary classSimon Pilgrim2017-11-261-5/+5
| | | | llvm-svn: 318999
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-2611-84/+509
| | | | | | | | | | | | | | | | | | Shadow stack solution introduces a new stack for return addresses only. The HW has a Shadow Stack Pointer (SSP) that points to the next return address. If we return to a different address, an exception is triggered. The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP). The intrinsics are mapped to new instruction set that implements CET mechanism. The patch also includes initial infrastructure support for IBT. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40223 Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4 llvm-svn: 318996
* [x86][icelake]GFNICoby Tayree2017-11-266-0/+1065
| | | | | | | | | | galois field arithmetic (GF(2^8)) insns: gf2p8affineinvqb gf2p8affineqb gf2p8mulb Differential Revision: https://reviews.llvm.org/D40373 llvm-svn: 318993
* [X86] Add separate intrinsics for scalar FMA4 instructions.Craig Topper2017-11-258-769/+1081
| | | | | | | | | | | | | | | | | | | | | | | Summary: These instructions zero the non-scalar part of the lower 128-bits which makes them different than the FMA3 instructions which pass through the non-scalar part of the lower 128-bits. I've only added fmadd because we should be able to derive all other variants using operand negation in the intrinsic header like we do for AVX512. I think there are still some missed negate folding opportunities with the FMA4 instructions in light of this behavior difference that I hadn't noticed before. I've split the tests so that we can use different intrinsics for scalar testing between the two. I just copied the tests split the RUN lines and changed out the scalar intrinsics. fma4-fneg-combine.ll is a new test to make sure we negate the fma4 intrinsics correctly though there are a couple TODOs in it. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39851 llvm-svn: 318984
* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is ↵Craig Topper2017-11-251-0/+480
| | | | | | | | | | | | | | | | | | | disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions. Summary: This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior. Test command lines have been added for these two cases. Reviewers: magabari, delena, RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40282 llvm-svn: 318983
* Add BTVER2 sched support for SHLD/SHRD.Andrew V. Tischenko2017-11-251-24/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D40124 llvm-svn: 318977
* [X86] Support folding to andnps with SSE1 only.Craig Topper2017-11-251-4/+2
| | | | | | With SSE1 only, we emit FAND and FXOR nodes for v4f32. llvm-svn: 318968
* [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into ↵Craig Topper2017-11-253-268/+70
| | | | | | | | | | FAND/FOR/FXOR whe only SSE1 is available. v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise. This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header. llvm-svn: 318967
* [X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.Craig Topper2017-11-241-112/+6
| | | | | | | | This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops. For now just stop this from happening by disabling the optimization with sse1. llvm-svn: 318965
* [CodeGenPrepare] Check that erased sunken address are not reusedSimon Dardis2017-11-242-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | CodeGenPrepare sinks address computations from one basic block to another and attempts to reuse address computations that have already been sunk. If the same address computation appears twice with the first instance as an operand of a load whose result is an operand to a simplifable select, CodeGenPrepare simplifies the select and recursively erases the now dead instructions. CodeGenPrepare then attempts to use the erased address computation for the second load. Fix this by erasing the cached address value if it has zero uses before looking for the address value in the sunken address map. This partially resolves PR35209. Thanks to Alexander Richardson for reporting the issue! This fixed version relands r318032 which was reverted in r318049 due to sanitizer buildbot failures. Reviewers: john.brawn Differential Revision: https://reviews.llvm.org/D39841 llvm-svn: 318956
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-242-0/+72
| | | | | | | | | | See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39488 llvm-svn: 318955
* [AVR] Use the short form of 'clr <reg>'Dylan McKay2017-11-244-14/+15
| | | | | | | r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
* [CGP] Make optimizeMemoryInst able to combine more kinds of ExtAddrMode fieldsJohn Brawn2017-11-241-1/+351
| | | | | | | | | | | | | This patch extends the recent work in optimizeMemoryInst to make it able to combine more ExtAddrMode fields than just the BaseReg. This fixes some benchmark regressions introduced by r309397, where GVN PRE is hoisting a getelementptr such that it can no longer be combined into the addressing mode of the load or store that uses it. Differential Revision: https://reviews.llvm.org/D38133 llvm-svn: 318949
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-242-0/+21
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility ↵Dmitry Preobrazhensky2017-11-241-0/+4
| | | | | | | | | | | | with SP3 See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329 Reviewers: arsenm, vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D40350 llvm-svn: 318947
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