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* [InstCombine] [NFC] Add more tests for getting rid of select of bittest ↵Roman Lebedev2018-04-051-19/+178
| | | | | | | | | | | | | | | | | | | (D45108, PR36950 / PR17564) Summary: More tests for D45108: * One use tests * allow shift to be a variable, too Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45329 llvm-svn: 329348
* [X86] Add LEAVE instruction to the scheduler models using the same data as ↵Craig Topper2018-04-052-7/+7
| | | | | | | | | | LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
* [X86][SSE] Add floating point add/mul fast-math vector.reduce testsSimon Pilgrim2018-04-052-0/+2013
| | | | | | Strict versions aren't working at all (PR36732) and the accumulators aren't supported (PR36734) llvm-svn: 329344
* [X86][SSE] Add floating point min/max vector.reduce testsSimon Pilgrim2018-04-054-0/+1336
| | | | llvm-svn: 329343
* AMDGPU/Metadata: Always report a fixed number of hidden argumentsKonstantin Zhuravlyov2018-04-052-1/+70
| | | | | | | | | | Currently it is 6. If the "feature" was not used, report dummy hidden argument. Otherwise it does not match the kernarg size reported in the kernel header. Differential Revision: https://reviews.llvm.org/D45129 llvm-svn: 329341
* [X86] Remove some InstRWs for plain store instructions on Sandy Bridge.Craig Topper2018-04-0513-162/+160
| | | | | | We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329339
* [InstCombine] Properly change GEP type when reassociating loop invariant GEP ↵Daniel Neilson2018-04-051-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chains Summary: This is a fix to PR37005. Essentially, rL328539 ([InstCombine] reassociate loop invariant GEP chains to enable LICM) contains a bug whereby it will convert: %src = getelementptr inbounds i8, i8* %base, <2 x i64> %val %res = getelementptr inbounds i8, <2 x i8*> %src, i64 %val2 into: %src = getelementptr inbounds i8, i8* %base, i64 %val2 %res = getelementptr inbounds i8, <2 x i8*> %src, <2 x i64> %val By swapping the index operands if the GEPs are in a loop, and %val is loop variant while %val2 is loop invariant. This fix recreates new GEP instructions if the index operand swap would result in the type of %src changing from vector to scalar, or vice versa. Reviewers: sebpop, spatel Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45287 llvm-svn: 329331
* [X86] Synchronize the SchedRW on some EVEX instructions with their VEX ↵Craig Topper2018-04-052-264/+264
| | | | | | | | equivalents. Mostly vector load, store, and move instructions. llvm-svn: 329330
* [InstCombine] add test for fneg+fsub with nsz; NFCSanjay Patel2018-04-051-3/+17
| | | | | | | | There used to be a fold that would handle this case more generally, but it was removed at rL73243 to fix PR4374: https://bugs.llvm.org/show_bug.cgi?id=4374 llvm-svn: 329322
* [X86][SSE] Add integer add/mul vector.reduce testsSimon Pilgrim2018-04-052-0/+4317
| | | | llvm-svn: 329321
* [X86][SSE] Add integer and/or/xor vector.reduce testsSimon Pilgrim2018-04-053-0/+3084
| | | | llvm-svn: 329320
* [X86][SSE] Add integer min/max vector.reduce testsSimon Pilgrim2018-04-054-0/+7300
| | | | llvm-svn: 329319
* [InstCombine] use pattern matchers for fsub --> fadd foldsSanjay Patel2018-04-051-3/+2
| | | | | | This allows folding for vectors with undef elements. llvm-svn: 329316
* [WebAssembly] Allow for the creation of user-defined custom sectionsSam Clegg2018-04-052-0/+43
| | | | | | | | | | | | | This patch adds a way for users to create their own custom sections to be added to wasm files. At the LLVM IR layer, they are defined through the "wasm.custom_sections" named metadata. The expected use case for this is bindings generators such as wasm-bindgen. Patch by Dan Gohman Differential Revision: https://reviews.llvm.org/D45297 llvm-svn: 329315
* [InstCombine] add tests for fsub --> fadd; NFCSanjay Patel2018-04-051-3/+65
| | | | llvm-svn: 329313
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-49/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [PatternMatch] define m_FNeg using m_FSubSanjay Patel2018-04-054-20/+9
| | | | | | | | | Using cstfp_pred_ty in the definition allows us to match vectors with undef elements. This replicates the change for m_Not from D44076 / rL326823 and continues towards making all pattern matchers allow undef elements in vectors. llvm-svn: 329303
* [InstCombine] add vector and vector undef tests for FP folds; NFCSanjay Patel2018-04-053-89/+226
| | | | llvm-svn: 329294
* ARM: Do not spill CSR to stack on entry to noreturn functionsTim Northover2018-04-057-11/+62
| | | | | | | | | | | | | | A noreturn nounwind function can be expected to never return in any way, and by never returning it will also never have to restore any callee-saved registers for its caller. This makes it possible to skip spills of those registers during function entry, saving some stack space and time in the process. This is rather useful for embedded targets with limited stack space. Should fix PR9970. Patch by myeisha (pmb). llvm-svn: 329287
* [DAGCombine] Revert r329160Sam Parker2018-04-052-114/+22
| | | | | | Again, broke the big endian stage 2 builders. llvm-svn: 329283
* [LoopInterchange] Require asserts for test using -stats (NFC)Florian Hahn2018-04-051-1/+2
| | | | | | This fixes a buildbot failure. llvm-svn: 329279
* [LoopInterchange] Add stats counter for number of interchanged loops.Florian Hahn2018-04-051-1/+5
| | | | | | | | | | Reviewers: samparker, karthikthecool, blitz.opensource Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D45209 llvm-svn: 329269
* [mips] Regenerate test before posting patch for constant multiplication (NFC)Simon Dardis2018-04-051-56/+748
| | | | llvm-svn: 329268
* [LoopInterchange] Preserve LoopInfo after interchanging.Florian Hahn2018-04-0513-14/+22
| | | | | | | | | | | | | | LoopInterchange relies on LoopInfo being up-to-date, so we should preserve it after interchanging. This patch updates restructureLoops to move the BBs of the interchanged loops to the right place. Reviewers: davide, efriedma, karthikthecool, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45278 llvm-svn: 329264
* [X86] Revert r329251-329254Craig Topper2018-04-0514-866/+627
| | | | | | | | | | | | | It's failing on the bots and I'm not sure why. This reverts: [X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents. [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256. [X86] Remove some InstRWs for plain store instructions on Sandy Bridge. [X86] Auto-generate complete checks. NFC llvm-svn: 329256
* [X86] Synchronize the SchedRW on some EVEX instructions with their VEX ↵Craig Topper2018-04-052-264/+264
| | | | | | | | equivalents. Mostly vector load, store, and move instructions. llvm-svn: 329254
* [X86] Remove some InstRWs for plain store instructions on Sandy Bridge.Craig Topper2018-04-051-36/+36
| | | | | | We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329252
* [X86] Auto-generate complete checks. NFCCraig Topper2018-04-0512-327/+566
| | | | llvm-svn: 329251
* [CallSiteSplitting] Do not perform callsite splitting inside landing padTaewook Oh2018-04-051-0/+40
| | | | | | | | | | | | | | | | | | | Summary: If the callsite is inside landing pad, do not perform callsite splitting. Callsite splitting uses utility function llvm::DuplicateInstructionsInSplitBetween, which eventually calls llvm::SplitEdge. llvm::SplitEdge calls llvm::SplitCriticalEdge with an assumption that the function returns nullptr only when the target edge is not a critical edge (and further assumes that if the return value was not nullptr, the predecessor of the original target edge always has a single successor because critical edge splitting was successful). However, this assumtion is not true because SplitCriticalEdge returns nullptr if the destination block is a landing pad. This invalid assumption results assertion failure. Fundamental solution might be fixing llvm::SplitEdge to not to rely on the invalid assumption. However, it'll involve a lot of work because current API assumes that llvm::SplitEdge never fails. Instead, this patch makes callsite splitting to not to attempt splitting if the callsite is in a landing pad. Attached test case will crash with assertion failure without the fix. Reviewers: fhahn, junbuml, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45130 llvm-svn: 329250
* [gold] Add debug-pass-manager option, and use it to test new-pass-managerTeresa Johnson2018-04-051-0/+19
| | | | | | | | | | | | Summary: Follow up from r314963. Reviewers: pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45293 llvm-svn: 329249
* [IR] Upgrade comment token in objc retain release markerGerolf Hoflehner2018-04-052-0/+6
| | | | | | Older compiler issued '#' instead of ';' llvm-svn: 329248
* [MIR-Canon] Improving performance by switching to named vregs.Puyan Lotfi2018-04-052-11/+11
| | | | | | No more skipping thounsands of vregs. Much faster running time. llvm-svn: 329246
* [MIR-Canon] Adding support for multi-def -> user distance reduction.Puyan Lotfi2018-04-051-0/+32
| | | | llvm-svn: 329243
* [WebAssembly] Only write 32-bits for WebAssembly::OPERAND_OFFSET32Sam Clegg2018-04-041-0/+21
| | | | | | | | | A bug was found where an offset of -1 would generate an encoding of max int64 which is invalid in the binary format. Differential Revision: https://reviews.llvm.org/D45280 llvm-svn: 329238
* AArch64: Implement support for the shadowcallstack attribute.Peter Collingbourne2018-04-041-0/+47
| | | | | | | | | | | | The implementation of shadow call stack on aarch64 is quite different to the implementation on x86_64. Instead of reserving a segment register for the shadow call stack, we reserve the platform register, x18. Any function that spills lr to sp also spills it to the shadow call stack, a pointer to which is stored in x18. Differential Revision: https://reviews.llvm.org/D45239 llvm-svn: 329236
* Don't inline @llvm.icall.branch.funnelVitaly Buka2018-04-042-6/+49
| | | | | | | | | | | | | | Summary: @llvm.icall.branch.funnel is musttail with variable number of arguments. After inlining current backend can't separate call targets from call arguments. Reviewers: pcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45116 llvm-svn: 329235
* hwasan: add -hwasan-match-all-tag flagEvgeniy Stepanov2018-04-041-5/+11
| | | | | | | | | | | | | | | | Sometimes instead of storing addresses as is, the kernel stores the address of a page and an offset within that page, and then computes the actual address when it needs to make an access. Because of this the pointer tag gets lost (gets set to 0xff). The solution is to ignore all accesses tagged with 0xff. This patch adds a -hwasan-match-all-tag flag to hwasan, which allows to ignore accesses through pointers with a particular pointer tag value for validity. Patch by Andrey Konovalov. Differential Revision: https://reviews.llvm.org/D44827 llvm-svn: 329228
* [Analysis] Support aligned new/delete functions.Eric Fiselier2018-04-041-0/+40
| | | | | | | | | | | | | | | | Summary: Clang's __builtin_operator_new/delete was recently taught about the aligned allocation overloads (r328134). This patch makes LLVM aware of them as well. This allows the compiler to perform certain optimizations including eliding new/delete calls. Reviewers: rsmith, majnemer, dblaikie, vsk, bkramer Reviewed By: bkramer Subscribers: ckennelly, llvm-commits Differential Revision: https://reviews.llvm.org/D44769 llvm-svn: 329218
* Revert "[Analysis] Support aligned new/delete functions."Eric Fiselier2018-04-041-40/+0
| | | | | | This reverts commit bee3bbd9bdd3ab3364b8fb0cdb6326bc1ae740e0. llvm-svn: 329217
* [Analysis] Support aligned new/delete functions.Eric Fiselier2018-04-041-0/+40
| | | | | | | | | | | | | | | | Summary: Clang's __builtin_operator_new/delete was recently taught about the aligned allocation overloads (r328134). This patch makes LLVM aware of them as well. This allows the compiler to perform certain optimizations including eliding new/delete calls. Reviewers: rsmith, majnemer, dblaikie, vsk, bkramer Reviewed By: bkramer Subscribers: ckennelly, llvm-commits Differential Revision: https://reviews.llvm.org/D44769 llvm-svn: 329215
* [X86] Separate BSWAP32r and BSWAP64r scheduling data in ↵Craig Topper2018-04-041-6/+6
| | | | | | | | SandyBridge/Haswell/Broadwell/Skylake scheduler models. The BSWAP64r version is 2 uops and BSWAP32r is only 1 uop. The regular expressions also looked for a non-existant BSWAP16r. llvm-svn: 329211
* [Power9]Legalize and emit code for quad-precision fma instructionsLei Huang2018-04-041-0/+203
| | | | | | | | | | | | | Legalize and emit code for the following quad-precision fma: * xsmaddqp * xsnmaddqp * xsmsubqp * xsnmsubqp Differential Revision: https://reviews.llvm.org/D44843 llvm-svn: 329206
* Re-commit r329179 after fixing build&test issuesPavel Labath2018-04-048-5/+1878
| | | | | | | | | | | - MSVC was not OK with a static_assert referencing a non-static member variable, even though it was just in a sizeof(expression). I move the assert into the emit function, where it is probably more useful. - Tests were failing in builds which did not have the X86 target configured. Since this functionality is not target-specific, I have removed the target specifiers from the .ll files. llvm-svn: 329201
* [InstCombine] [NFC] Add tests for getting rid of select of bittest (PR36950 ↵Roman Lebedev2018-04-041-0/+464
| | | | | | | | | | | | | | | | / PR17564) Summary: See [[ https://bugs.llvm.org/show_bug.cgi?id=36950 | PR36950 ]], [[ https://bugs.llvm.org/show_bug.cgi?id=17564 | PR17564 ]], D45065, D45108 Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45107 llvm-svn: 329198
* [AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CIDmitry Preobrazhensky2018-04-041-0/+4
| | | | | | | | | See bug 36958: https://bugs.llvm.org/show_bug.cgi?id=36958 Differential Revision: https://reviews.llvm.org/D45099 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329197
* [SLPVectorizer][X86] Regenerate some tests. NFCISimon Pilgrim2018-04-045-74/+187
| | | | llvm-svn: 329196
* [X86][Btver2] Strip unnecessary check prefixes from resources testsSimon Pilgrim2018-04-0411-11/+11
| | | | llvm-svn: 329192
* Revert r329179 (and follow-up unsuccessful fix attempts 329184, 329186); it ↵Nico Weber2018-04-048-1897/+5
| | | | | | doesn't build. llvm-svn: 329190
* [AMDGPU][MC] Added support of 3-element addresses for MIMG instructionsDmitry Preobrazhensky2018-04-041-0/+63
| | | | | | | | | See bug 35999: https://bugs.llvm.org/show_bug.cgi?id=35999 Differential Revision: https://reviews.llvm.org/D45084 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329187
* [CodeGen] Generate DWARF v5 Accelerator TablesPavel Labath2018-04-048-5/+1897
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a DwarfAccelTableEmitter class, which generates an accelerator table, as specified in DWARF v5 standard. At the moment it only generates a DIE offset column and (if we are indexing more than one compile unit) a CU column. Indexing type units is not currently supported, as we don't even have the ability to generate DWARF v5-compatible compile units. The implementation is not data-source agnostic like the one generating apple tables. This was not necessary as we currently only have one user of this code, and without a second user it was not obvious to me how to best abstract this. (The difference between these tables and the apple ones is that they need a lot more metadata about the debug info they are indexing). The generation is triggered by the --accel-tables argument, which supersedes the --dwarf-accel-tables arg -- the latter was a simple on-off switch, but not we can choose between two kinds of accelerator tables we can generate. This is tested by parsing the generated tables with llvm-dwarfdump and the DWARFVerifier, and I've also checked that GNU readelf is able to make sense of the tables. Differential Revision: https://reviews.llvm.org/D43286 llvm-svn: 329179
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