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* Check register class matching instead of width of type matchingEric Christopher2011-07-141-0/+13
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Add 256-bit load/store recognition and matching in several places.Bruno Cardoso Lopes2011-07-141-0/+24
| | | | llvm-svn: 135171
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-142-44/+58
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* ARM ISB assembly parsing tests.Jim Grosbach2011-07-142-2/+10
| | | | llvm-svn: 135158
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-141-1/+1
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Add a testcase for r135123.Eric Christopher2011-07-141-0/+14
| | | | | | Part of rdar://9761830 llvm-svn: 135133
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-141-0/+20
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
* ARM tests for EOR instruction parsing and encoding.Jim Grosbach2011-07-141-0/+57
| | | | llvm-svn: 135119
* Remove duplicate tests.Jim Grosbach2011-07-141-24/+0
| | | | llvm-svn: 135117
* ARM Assembler support for DSB instruction.Jim Grosbach2011-07-141-0/+31
| | | | | | Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
* ARM Assembler support for DMB instruction.Jim Grosbach2011-07-132-24/+32
| | | | | | | | Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
* ARM Assembler support for DBG instruction.Jim Grosbach2011-07-132-0/+19
| | | | | | Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
* We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.Bruno Cardoso Lopes2011-07-131-0/+116
| | | | llvm-svn: 135099
* ARM parsing and encoding tests for CMN/CMP.Jim Grosbach2011-07-131-0/+59
| | | | llvm-svn: 135098
* Shuffle ARM assembly tests a bit.Jim Grosbach2011-07-132-10/+22
| | | | llvm-svn: 135095
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-132-0/+27
| | | | llvm-svn: 135092
* Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A moreBruno Cardoso Lopes2011-07-131-0/+45
| | | | | | | general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
* Make sure we don't combine a large displacement and a frame index in the ↵Eli Friedman2011-07-131-0/+20
| | | | | | | | same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. <rdar://problem/9763308> llvm-svn: 135084
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-132-15/+15
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Testcases for ARM assembly BX/BXJ instructions.Jim Grosbach2011-07-131-2/+24
| | | | llvm-svn: 135078
* Testcases for ARM assembly BLX/BL instructions.Jim Grosbach2011-07-131-0/+17
| | | | llvm-svn: 135072
* Range checking for 16-bit immediates in ARM assembly.Jim Grosbach2011-07-132-4/+8
| | | | llvm-svn: 135071
* Change test case, one that actually failed before my commit.Evan Cheng2011-07-131-1/+6
| | | | llvm-svn: 135064
* Add tests for ARM parsing of 'BKPT' instruction.Jim Grosbach2011-07-131-0/+9
| | | | llvm-svn: 135063
* Fix copy-pasto.Jim Grosbach2011-07-131-1/+1
| | | | llvm-svn: 135062
* Add tests for ARM parsing of 'BIC' instruction.Jim Grosbach2011-07-131-0/+58
| | | | llvm-svn: 135061
* Add some FIXMEs.Jim Grosbach2011-07-131-0/+16
| | | | | | | Keeping the instructions in alphabetical order, just like in the ARM ARM. Adding FIXMEs for skipped instructions when adding tests out of order. llvm-svn: 135060
* It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is ↵Evan Cheng2011-07-131-2/+19
| | | | | | another use of sqrt. rdar://9763193 llvm-svn: 135058
* Add tests for ARM parsing of 'AND' instruction.Jim Grosbach2011-07-131-0/+58
| | | | llvm-svn: 135056
* Improve ARM assembly parsing diagnostics a bit.Jim Grosbach2011-07-131-0/+43
| | | | | | | | | Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
* Add tests for ARM parsing of 'ADD' instructionJim Grosbach2011-07-131-0/+63
| | | | llvm-svn: 135053
* Destination register operand is optional for ADC and SBC ARM.Jim Grosbach2011-07-131-0/+36
| | | | llvm-svn: 135052
* Flesh out ARM Parser support for shifted-register operands.Jim Grosbach2011-07-131-0/+48
| | | | | | | Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
* AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, ↵Bruno Cardoso Lopes2011-07-131-0/+116
| | | | | | vxorps, vxorpd llvm-svn: 135023
* Improve codegen for select's:Evan Cheng2011-07-135-115/+36
| | | | | | | | | | | | | | | | | | | | if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
* Add check for predicate w/o S bit.Jim Grosbach2011-07-121-0/+2
| | | | llvm-svn: 134987
* Improve test cases from r134746.Jim Grosbach2011-07-122-5/+21
| | | | | | | Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
* Comment correction.Andrew Trick2011-07-121-2/+3
| | | | llvm-svn: 134958
* Fix recognition of ARM 'adcs' mnemonic.Jim Grosbach2011-07-111-0/+31
| | | | | | The 'CS' is not a predication suffix in this case. llvm-svn: 134903
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-119-23/+22
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See ↵NAKAMURA Takumi2011-07-111-1/+1
| | | | | | also r134814 (test/CodeGen/X86/vector.ll). llvm-svn: 134900
* Add a missing test for r134882.Cameron Zwarich2011-07-111-0/+8
| | | | llvm-svn: 134889
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+2
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Don't duplicate the work done by a gep into a "bitcast" if the gep hasRafael Espindola2011-07-111-0/+16
| | | | | | | | more than one use. Fixes PR10322. llvm-svn: 134883
* Move the loads after the calls so that the fix forRafael Espindola2011-07-091-48/+48
| | | | | | | PR10292 doesn't show that the loads don't alias the allocas. llvm-svn: 134852
* Use CHECK-NEXT.Rafael Espindola2011-07-091-259/+260
| | | | llvm-svn: 134850
* Remove tests for APIs that were removed.Nick Lewycky2011-07-093-131/+2
| | | | llvm-svn: 134842
* Land the long talked about "type system rewrite" patch. ThisChris Lattner2011-07-0941-231/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patch brings numerous advantages to LLVM. One way to look at it is through diffstat: 109 files changed, 3005 insertions(+), 5906 deletions(-) Removing almost 3K lines of code is a good thing. Other advantages include: 1. Value::getType() is a simple load that can be CSE'd, not a mutating union-find operation. 2. Types a uniqued and never move once created, defining away PATypeHolder. 3. Structs can be "named" now, and their name is part of the identity that uniques them. This means that the compiler doesn't merge them structurally which makes the IR much less confusing. 4. Now that there is no way to get a cycle in a type graph without a named struct type, "upreferences" go away. 5. Type refinement is completely gone, which should make LTO much MUCH faster in some common cases with C++ code. 6. Types are now generally immutable, so we can use "Type *" instead "const Type *" everywhere. Downsides of this patch are that it removes some functions from the C API, so people using those will have to upgrade to (not yet added) new API. "LLVM 3.0" is the right time to do this. There are still some cleanups pending after this, this patch is large enough as-is. llvm-svn: 134829
* more tests not making the jump into the brave new world.Chris Lattner2011-07-0916-1522/+0
| | | | llvm-svn: 134820
* remove some crufy old tests that aren't adding much valueChris Lattner2011-07-0910-194/+0
| | | | llvm-svn: 134819
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