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* Parse the TPI (type information) stream of PDB files.Zachary Turner2016-05-031-0/+9
| | | | | | | | | | | | | | | This parses the TPI stream (stream 2) from the PDB file. This stream contains some header information followed by a series of codeview records. There is some additional complexity here in that alongside this stream of codeview records is a serialized hash table in order to efficiently query the types. We parse the necessary bookkeeping information to allow us to reconstruct the hash table, but we do not actually construct it yet as there are still a few things that need to be understood first. Differential Revision: http://reviews.llvm.org/D19840 Reviewed By: ruiu, rnk llvm-svn: 268343
* ThinLTO: do not import function whose linkage prevents inlining.Mehdi Amini2016-05-033-2/+12
| | | | | | | | | | | There is not point in importing a "weak" or a "linkonce" function since we won't be able to inline it anyway. We already had a targeted check for WeakAny, this is using the same check on GlobalValue as the inline, i.e. isMayBeOverriddenLinkage() From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268341
* Moved test case for r268323 to DebugInfo/X86 to unbreak aarch64.Wolfgang Pieb2016-05-031-0/+0
| | | | llvm-svn: 268339
* [MC] Create unique .pdata sections for every .text sectionReid Kleckner2016-05-022-5/+157
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds a unique ID to the COFF section uniquing map, similar to the one we have for ELF. The unique id is not currently exposed via the assembler because we don't have a use case for it yet. Users generally create .pdata with the .seh_* family of directives, and the assembler internally needs to produce .pdata and .xdata sections corresponding to the code section. The association between .text sections and the assembler-created .xdata and .pdata sections is maintained as an ID field of MCSectionCOFF. The CFI-related sections are created with the given unique ID, so if more code is added to the same text section, we can find and reuse the CFI sections that were already created. Reviewers: majnemer, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19376 llvm-svn: 268331
* [MachineBlockPlacement] Let the target optimize the branches at the end.Quentin Colombet2016-05-021-4/+4
| | | | | | | | | | | | | | | After the layout of the basic blocks is set, the target may be able to get rid of unconditional branches to fallthrough blocks that the generic code does not catch. This happens any time TargetInstrInfo::AnalyzeBranch is not able to analyze all the branches involved in the terminators sequence, while still understanding a few of them. In such situation, AnalyzeBranch can directly modify the branches if it has been instructed to do so. This patch takes advantage of that. llvm-svn: 268328
* [X86] Model FAULTING_LOAD_OP as a terminator and branch.Quentin Colombet2016-05-021-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This operation may branch to the handler block and we do not want it to happen anywhere within the basic block. Moreover, by marking it "terminator and branch" the machine verifier does not wrongly assume (because of AnalyzeBranch not knowing better) the branch is analyzable. Indeed, the target was seeing only the unconditional branch and not the faulting load op and thought it was a simple unconditional block. The machine verifier was complaining because of that and moreover, other optimizations could have done wrong transformation! In the process, simplify the representation of the handler block in the faulting load op. Now, we directly reference the handler block instead of using a label. This has the benefits of: 1. MC knows how to issue a label for a BB, so leave that to it. 2. Accessing the target BB from its label is painful, whereas it is direct from a MBB operand. Note: The 2 bytes offset in implicit-null-check.ll comes from the fact the unconditional jumps are not removed anymore, as the whole terminator sequence is not analyzable anymore. Will fix it in a subsequence commit. llvm-svn: 268327
* DebugInfo: Avoid propagating incorrect debug locations in SelectionDAG via CSE.Wolfgang Pieb2016-05-021-0/+100
| | | | | | | | | | | | | | | | | | Summary: When SelectionDAG performs CSE it is possible that the context's source location is different from that of the selected node. This can lead to incorrect line number records. We update the debug location to the one that occurs earlier in the instruction sequence. This fixes PR21006. Reviewers: echristo, sdmitrouk Subscribers: jevinskie, asl, llvm-commits Differential Revision: http://reviews.llvm.org/D12094 llvm-svn: 268323
* Revert "ThinLTO: do not import function whose linkage prevents inlining."Mehdi Amini2016-05-022-10/+0
| | | | | | | This reverts commit r268315, the tests are not passing. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268317
* ThinLTO: do not import function whose linkage prevents inlining.Mehdi Amini2016-05-022-0/+10
| | | | | | | | | | | There is not point in importing a "weak" or a "linkonce" function since we won't be able to inline it anyway. We already had a targeted check for WeakAny, this is using the same check on GlobalValue as the inline, i.e. isMayBeOverriddenLinkage() From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268315
* Fix llvm-size to exit with non zero when it can’t open a file.Kevin Enderby2016-05-021-1/+1
| | | | | | rdar://26027819 llvm-svn: 268313
* Don't try to create thin bsd archives.Rafael Espindola2016-05-021-0/+3
| | | | | | Not such variant has been specified yet. llvm-svn: 268305
* [dsymutil] Create the temporary files in the system temp directory.Frederic Riss2016-05-021-3/+1
| | | | | | | | | | llvm-dsymutil used to create the temporary files in the output directory. This works fine except when the output directory contains a '%' char, which is then replaced by llvm::sys::fs::createUniqueFile() generating an invalid path. Just use the default temp dir for those files. llvm-svn: 268304
* Thread Expected<...> up from libObject’s getType() for symbols to allow ↵Kevin Enderby2016-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | llvm-objdump to produce a good error message. Produce another specific error message for a malformed Mach-O file when a symbol’s section index is more than the number of sections. The existing test case in test/Object/macho-invalid.test for macho-invalid-section-index-getSectionRawName now reports the error with the message indicating that a symbol at a specific index has a bad section index and that bad section index value. Again converting interfaces to Expected<> from ErrorOr<> does involve touching a number of places. Where the existing code reported the error with a string message or an error code it was converted to do the same. Also there some were bugs in the existing code that did not deal with the old ErrorOr<> return values.  So now with Expected<> since they must be checked and the error handled, I added a TODO and a comment: "// TODO: Actually report errors helpfully" and a call something like consumeError(NameOrErr.takeError()) so the buggy code will not crash since needed to deal with the Error. llvm-svn: 268298
* AMDGPU: Custom lower v2i32 loads and storesMatt Arsenault2016-05-021-1/+98
| | | | | | | This will allow us to split up 64-bit private accesses when necessary. llvm-svn: 268296
* AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratchTom Stellard2016-05-021-1/+1
| | | | | | | | | We were using v_readlane_b32 with the lane set to zero, but this won't work if thread 0 is not active. Differential Revision: http://reviews.llvm.org/D19745 llvm-svn: 268295
* AMDGPU: Make i64 loads/stores promote to v2i32Matt Arsenault2016-05-024-18/+14
| | | | | | | | | | | | Now that unaligned access expansion should not attempt to produce i64 accesses, we can remove the hack in PreprocessISelDAG where this is done. This allows splitting i64 private accesses while allowing the new add nodes indexing the vector components can be folded with the base pointer arithmetic. llvm-svn: 268293
* [X86][AVX2] Added 128-bit wide shuffle testSimon Pilgrim2016-05-021-0/+14
| | | | | | Demonstrate missing 128-bit wide shuffle combine support llvm-svn: 268290
* Revert "[SimplifyCFG] Extend TryToSimplifyUncondBranchFromEmptyBlock for ↵Reid Kleckner2016-05-021-232/+0
| | | | | | | | | | | empty block including lifetime intrinsics" This reverts commit r268254. This change causes assertion failures while building Chromium. Reduced test case coming soon. llvm-svn: 268288
* ARM: fix handling of SUB immediates in peephole opt.Tim Northover2016-05-022-0/+119
| | | | | | | | | | | We were negating an immediate that was going to be used in a SUBri form unnecessarily. Since ADD/SUB are very similar we *can* do that, but we have to change the SUB to an ADD at the same time. This also applies to ADD, and allows us to handle a slightly larger range of immediates for those two operations. rdar://25992245 llvm-svn: 268276
* [NVPTX] Fix sign/zero-extending ldg/ldu instruction selectionJustin Holewinski2016-05-021-0/+34
| | | | | | | | | | | | | | | | | Summary: We don't have sign-/zero-extending ldg/ldu instructions defined, so we need to emulate them with explicit CVTs. We were originally handling the i8 case, but not any other cases. Fixes PR26185 Reviewers: jingyue, jlebar Subscribers: jholewinski Differential Revision: http://reviews.llvm.org/D19615 llvm-svn: 268272
* Parse PDB Name Hash TableZachary Turner2016-05-021-0/+15
| | | | | | | | | | | | | PDB has a lot of similar data structures. We already have code for parsing a Name Map, but PDB seems to have a different but very similar structure that is a hash table. This is the beginning of code needed in order to parse the name hash table, but it is not yet complete. It parses the basic metadata of the hash table, the bucket array, and the names buffer, but doesn't use any of these fields yet as the data structure requires a non-trivial amount of work to understand. llvm-svn: 268268
* AMDGPU/SI: Use the hazard recognizer to break SMEM soft clausesTom Stellard2016-05-023-39/+37
| | | | | | | | | | | | | | | Summary: Add support for detecting hazards in SMEM soft clauses, so that we only break the clauses when necessary, either by adding s_nop or re-ordering other alu instructions. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18870 llvm-svn: 268260
* AMDGPU: llvm.SI.fs.constant is a source of divergenceNicolai Haehnle2016-05-021-0/+22
| | | | | | | | | | | | | | | | Summary: This intrinsic is used to get flat-shaded fragment shader inputs. Those are uniform across a primitive, but a fragment shader wave may process pixels from multiple primitives (as indicated by the prim_mask), and so that's where divergence can arise. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19747 llvm-svn: 268259
* [WebAssembly] Rename memory_size intrinsic to current_memoryDerek Schuff2016-05-022-10/+10
| | | | | | This follows the recent renaming in the wasm spec. llvm-svn: 268255
* [SimplifyCFG] Extend TryToSimplifyUncondBranchFromEmptyBlock for empty block ↵Hans Wennborg2016-05-021-0/+232
| | | | | | | | | | | | | | | | | | including lifetime intrinsics Make it possible that TryToSimplifyUncondBranchFromEmptyBlock merges empty basic block including lifetime intrinsics as well as phi nodes and unconditional branch into its successor or predecessor(s). If successor of empty block has single predecessor, all contents including lifetime intrinsics are sinked into the successor. Otherwise, they are hoisted into its predecessor(s) and then merged into the predecessor(s). Patch by Josh Yoon <josh.yoon@samsung.com>! Differential Revision: http://reviews.llvm.org/D19257 llvm-svn: 268254
* Move createReversePostOrderFunctionAttrsPass right after the inliner is doneMehdi Amini2016-05-021-0/+3
| | | | | | | | | | This is where it was originally, until LoopVersioningLICM was inserted before in r259986, I don't believe it was on purpose. Differential Revision: http://reviews.llvm.org/D19809 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268252
* Add llvm-pdbdump to the tool substitutions list in lit. NFC.Pete Cooper2016-05-021-0/+1
| | | | | | | | | This adds llvm-pdbdump to the list of tools which get printed with the full path in verbose mode. This makes it easier to take the whole run line from verbose output and run it again without prepending with the builds bin directory. llvm-svn: 268250
* Remove extra whitespace. NFC.Chad Rosier2016-05-021-4/+4
| | | | llvm-svn: 268248
* AMDGPU/SI: Use hazard recognizer to detect DPP hazardsTom Stellard2016-05-021-2/+6
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18603 llvm-svn: 268247
* remove blank linesSanjay Patel2016-05-021-8/+1
| | | | llvm-svn: 268246
* [InstCombine] regenerate checksSanjay Patel2016-05-021-342/+493
| | | | llvm-svn: 268245
* [InstCombine] regenerate checksSanjay Patel2016-05-021-81/+73
| | | | llvm-svn: 268244
* [InstCombine] regenerate checksSanjay Patel2016-05-021-69/+103
| | | | llvm-svn: 268242
* [InstCombine] regenerate checksSanjay Patel2016-05-021-131/+183
| | | | llvm-svn: 268241
* [InstCombine] regenerate checksSanjay Patel2016-05-021-33/+43
| | | | llvm-svn: 268239
* [InstCombine] regenerate checksSanjay Patel2016-05-021-500/+674
| | | | llvm-svn: 268232
* Enable the X86 call frame optimization for the 64-bit targets that allow it.David L Kreitzer2016-05-021-0/+193
| | | | | | | | Fixes PR27241. Differential Revision: http://reviews.llvm.org/D19688 llvm-svn: 268227
* [SystemZ] Temporarily disable codegen test int-add-12.ll.Jonas Paulsson2016-05-021-1/+1
| | | | | | This checks for AGSI transformation, which is temporarily disabled. llvm-svn: 268219
* [llvm-readobj] Dump hash as part of -version-info.Davide Italiano2016-05-021-0/+3
| | | | llvm-svn: 268210
* [GlobalDCE] Modernize. Use FileCheck instead of grep.Davide Italiano2016-05-016-7/+15
| | | | llvm-svn: 268207
* [InstCombine][SSE] Added support to VPERMD/VPERMPS to shuffle combine to ↵Simon Pilgrim2016-05-011-5/+5
| | | | | | accept UNDEF elements. llvm-svn: 268206
* Dropped FIXME commentSimon Pilgrim2016-05-011-1/+1
| | | | llvm-svn: 268205
* [InstCombine][SSE] Added support to VPERMILVAR to shuffle combine to accept ↵Simon Pilgrim2016-05-011-8/+8
| | | | | | UNDEF elements. llvm-svn: 268204
* [InstCombine][AVX] Fixed PERMILVAR identity tests and added additional ↵Simon Pilgrim2016-05-011-13/+47
| | | | | | decode tests llvm-svn: 268203
* [InstCombine][SSE] Added support to PSHUFB to shuffle combine to accept ↵Simon Pilgrim2016-05-011-6/+4
| | | | | | UNDEF elements. llvm-svn: 268202
* [InstCombine][SSE] Regenerate MOVSX/MOVZX testsSimon Pilgrim2016-05-012-114/+116
| | | | llvm-svn: 268201
* [AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While ↵Craig Topper2016-05-013-210/+210
| | | | | | there fix the execution domain for VPACKSSDW/VPACKUSDW. llvm-svn: 268200
* [InstCombine][AVX2] Combine VPERMD/VPERMPS intrinsics with constant masks to ↵Simon Pilgrim2016-05-011-15/+13
| | | | | | shufflevector. llvm-svn: 268199
* getelementptr instruction, support index vector of EVT.Igor Breger2016-05-011-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D19775 llvm-svn: 268195
* Change AVX512 braodcastsd/ss patterns interaction with spilling . New ↵Igor Breger2016-05-013-0/+231
| | | | | | | | implementation take a scalar register and generate a vector without COPY_TO_REGCLASS (turn it into a VR128 register ) .The issue is that during register allocation we may spill a scalar value using 128-bit loads and stores, wasting cache bandwidth. Differential Revision: http://reviews.llvm.org/D19579 llvm-svn: 268190
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