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* SLPVectorizer: When sorting by domination for CSE don't assert on ↵Benjamin Kramer2014-05-091-0/+30
| | | | | | | | | | | | unreachable code. There is no total ordering if the CFG is disconnected. We don't care if we catch all CSE opportunities in dead code either so just exclude ignore them in the assert. PR19646 llvm-svn: 208461
* Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"Reid Kleckner2014-05-091-69/+0
| | | | | | | | | | | | | | This reverts commit r200561. This calling convention was an attempt to match the MSVC C++ ABI for methods that return structures by value. This solution didn't scale, because it would have required splitting every CC available on Windows into two: one for methods and one for free functions. Now that we can put sret on the second arg (r208453), and Clang does that (r208458), revert this hack. llvm-svn: 208459
* Allow sret on the second parameter as well as the firstReid Kleckner2014-05-094-9/+91
| | | | | | | | | | | | | | | | | | | | | | | | | MSVC always places the implicit sret parameter after the implicit this parameter of instance methods. We used to handle this for x86_thiscallcc by allocating the sret parameter on the stack and leaving the this pointer in ecx, but that doesn't handle alternative calling conventions like cdecl, stdcall, fastcall, or the win64 convention. Instead, change the verifier to allow sret on the second parameter. This also requires changing the Mips and X86 backends to return the argument with the sret parameter, instead of assuming that the sret parameter comes first. The Sparc backend also returns sret parameters in a register, but I wasn't able to update it to handle secondary sret parameters. It currently calls report_fatal_error if you feed it an sret in the second parameter. Reviewers: rafael.espindola, majnemer Differential Revision: http://reviews.llvm.org/D3617 llvm-svn: 208453
* Fix ARM intrinsics-overflow.ll test on WindowsReid Kleckner2014-05-091-1/+1
| | | | | | | Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. llvm-svn: 208448
* Don't crash on redefinitions.Rafael Espindola2014-05-091-0/+7
| | | | | | | | One error we were not deleting the alias or putting it in the Module. The end result is that there was an use left of the aliasee when the module was deleted. llvm-svn: 208447
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-091-0/+57
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* Add ExtractValue instruction to SimplifyCFG's ComputeSpeculationCostLouis Gerbarg2014-05-091-0/+22
| | | | | | | | | | | | | Since ExtractValue is not included in ComputeSpeculationCost CFGs containing ExtractValueInsts cannot be simplified. In particular this interacts with InstCombineCompare's tendency to insert add.with.overflow intrinsics for certain idiomatic math operations, preventing optimization. This patch adds ExtractValue to the ComputeSpeculationCost. Test case included rdar://14853450 llvm-svn: 208434
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-0/+14
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-091-0/+18
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+19
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-1/+1
| | | | llvm-svn: 208429
* Attempt to pacify the bots - this commit requires asserts.James Molloy2014-05-091-0/+1
| | | | llvm-svn: 208424
* [mips] Marked up instructions added in MIPS-IV and tested that IAS for ↵Daniel Sanders2014-05-095-0/+207
| | | | | | | | | | | | | | | | | | | | | -mcpu=mips[123] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-IV that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. Depends on D3676 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3677 llvm-svn: 208414
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-092-0/+257
| | | | | | | | | | When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must be passed in a block of consecutive floating-point registers, or on the stack. This means that unused floating-point registers cannot be back-filled with part of an HFA, however this can currently happen. This patch, along with the corresponding clang patch (http://reviews.llvm.org/D3083) prevents this. llvm-svn: 208413
* [yaml2obj] Follow-up to the r208228 and r208406. Remove duplicated YAMLSimon Atanasyan2014-05-091-3/+0
| | | | | | map keys. llvm-svn: 208412
* [mips] Marked up instructions added in MIPS-III and tested that IAS for ↵Daniel Sanders2014-05-094-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
* Mark yaml2obj-elf-x86-rel.yaml as XFAIL:vg_leak for now. This has two pairs ↵NAKAMURA Takumi2014-05-091-0/+1
| | | | | | of duplicate hashes. llvm-svn: 208406
* [mips][mips64r6] Add experimental support for MIPS32r6 and MIPS64r6Daniel Sanders2014-05-092-0/+18
| | | | | | | | | | | | | | | | | | Summary: Adds MIPS32r6/MIPS64r6 and checks the compatibility requirements for these processors. I've also included comments to describe removed and re-encoded instructions, along with placeholder def's for the new instructions but there are no functional changes to codegen at this point. Reviewers: jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3622 llvm-svn: 208399
* [mips] Added missing daddu test to the valid instruction tests.Daniel Sanders2014-05-095-0/+5
| | | | | | | | | | | | Summary: Depends on D3673 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3674 llvm-svn: 208398
* [mips] Added missing dsra -> dsrav and sra -> srav aliases.Daniel Sanders2014-05-099-0/+14
| | | | | | | | | | | | Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
* test/TableGen: Remove XFAIL:vg_leak out of 3 tests corresponding to r208293.NAKAMURA Takumi2014-05-093-3/+0
| | | | llvm-svn: 208393
* ARM: support PIC on Windows on ARMSaleem Abdulrasool2014-05-091-0/+16
| | | | | | | | Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. llvm-svn: 208385
* Optimize shufflevector that copies an i64/f64 and zeros the rest.Filipe Cabecinhas2014-05-082-0/+16
| | | | | | | | | | | | | | Summary: Also ran clang-format on the function. The code added is the last else if block. Reviewers: nadav, craig.topper, delena Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3518 llvm-svn: 208372
* test/CodeGen: Check that the correct register is used in a storeJustin Bogner2014-05-081-3/+3
| | | | | | | | | This tightens up r208351 to ensure that a store is fed with the correct value. Thanks to Quentin Colombet for spotting this! llvm-svn: 208368
* [InstCombine] Some cleanup in optimization of redundant insertvalue ↵Michael Zolotukhin2014-05-081-0/+11
| | | | | | | | instructions. And one more test added. llvm-svn: 208355
* Make a CodeGen test more robust against vector register selectionJustin Bogner2014-05-081-20/+19
| | | | llvm-svn: 208351
* add testcase for r208237: do not collect undef termsSebastian Pop2014-05-081-0/+38
| | | | llvm-svn: 208347
* [X86] Add target specific combine rules to fold SSE2/AVX2 packed arithmetic ↵Andrea Di Biagio2014-05-082-0/+104
| | | | | | | | | | | | | | | | | | | | shift intrinsics. This patch teaches the backend how to combine packed SSE2/AVX2 arithmetic shift intrinsics. The rules are: - Always fold a packed arithmetic shift by zero to its first operand; - Convert a packed arithmetic shift intrinsic dag node into a ISD::SRA only if the shift count is known to be smaller than the vector element size. This patch also teaches to function 'getTargetVShiftByConstNode' how fold target specific vector shifts by zero. Added two new tests to verify that the DAGCombiner is able to fold sequences of SSE2/AVX2 packed arithmetic shift calls. llvm-svn: 208342
* test: fix test on WindowsSaleem Abdulrasool2014-05-081-3/+2
| | | | | | | | When building on Windows, the default target is Windows. Windows on ARM does not support ARM mode compilation, resulting in test failures. Simply specify a triple to ensure that we are testing the correct behaviour. llvm-svn: 208340
* Mark test/TableGen/listconcat.td as XFAIL:vg_leak. llvm-tblgen is ignorant ↵NAKAMURA Takumi2014-05-081-0/+1
| | | | | | of vg_leak. llvm-svn: 208337
* [mips] Correct tests that are meant to test valid assembly. They were ↵Daniel Sanders2014-05-0816-2339/+2345
| | | | | | | | | | | | | | | | | | | | | | | | | | | actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
* ARM big endian function argument passingChristian Pirker2014-05-088-129/+382
| | | | llvm-svn: 208316
* [mips] Implement l[wd]c3, and s[wd]c3.Daniel Sanders2014-05-089-28/+9
| | | | | | | | | | | | | | | | | | | | | Summary: These instructions were added in MIPS-I, and MIPS-II but were removed in MIPS-III. Interestingly, GAS continues to accept them when assembling for MIPS-III. For the moment, these instructions will follow GAS and accept them for MIPS-III and newer but this will be tightened up when the invalid-*.s tests are added. Depends on D3647 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3648 llvm-svn: 208311
* Revert test commit. Removed blank line.Dario Domizioli2014-05-081-1/+0
| | | | llvm-svn: 208308
* [ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for ↵James Molloy2014-05-081-0/+9
| | | | | | | | big endian calls. SelectionDAG already knows about this, but fast-isel was ignorant. llvm-svn: 208307
* [mips] Marked up instructions added in MIPS-II and tested that IAS for ↵Daniel Sanders2014-05-082-0/+37
| | | | | | | | | | | | | | | | | | | -mcpu=mips1 does not accept them Summary: A small number of instructions are rejected with the wrong error message. These have been placed in a separate test for now. There seems to be some parsing quirk that triggers when these instructions are disabled. Depends on D3571 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3647 llvm-svn: 208305
* [mips] Implement tlbp, tlbr, tlbwi, and tlbwrDaniel Sanders2014-05-0818-36/+36
| | | | | | | | | | Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3571 llvm-svn: 208301
* Test commit. Added blank line.Dario Domizioli2014-05-081-0/+1
| | | | llvm-svn: 208298
* ARM64: make sure FastISel emits SSA MachineInstrsTim Northover2014-05-081-8/+19
| | | | | | We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
* [asan] Preserve flags in asm instrumentation.Evgeniy Stepanov2014-05-083-36/+36
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 208296
* Move late partial-unrolling thresholds into the processor definitionsHal Finkel2014-05-082-12/+12
| | | | | | | | | | | | | | | | | | | | | | The old method used by X86TTI to determine partial-unrolling thresholds was messy (because it worked by testing target features), and also would not correctly identify the target CPU if certain target features were disabled. After some discussions on IRC with Chandler et al., it was decided that the processor scheduling models were the right containers for this information (because it is often tied to special uop dispatch-buffer sizes). This does represent a small functionality change: - For generic x86-64 (which uses the SB model and, thus, will get some unrolling). - For AMD cores (because they still currently use the SB scheduling model) - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump the default threshold to 50; we're working on a test case for this). Otherwise, nothing has changed for any other targets. The logic, however, has been moved into BasicTTI, so other targets may now also opt-in to this functionality simply by setting LoopMicroOpBufferSize in their processor model definitions. llvm-svn: 208289
* AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ↵Hao Liu2014-05-081-0/+5077
| | | | | | ARM64 backend. llvm-svn: 208284
* test: fix silly typoSaleem Abdulrasool2014-05-081-1/+1
| | | | | | Oh silly Darwin and your case insensitive file system. llvm-svn: 208274
* ARM: support FK_SecRel_2 relocations on WoASaleem Abdulrasool2014-05-081-14/+24
| | | | | | | | This adds FK_SecRel_2 relocation support to ARM. This enables the building of object files for armv7-windows-msvc which enables CodeView line tables for debugging as opposed to armv7-windows-itanium which currently uses DWARF. llvm-svn: 208273
* Lower certain build_vectors to insertps instructionsFilipe Cabecinhas2014-05-081-0/+256
| | | | | | | | | | | | | | | | | | | | | | Summary: Vectors built with zeros and elements in the same order as another (source) vector are optimized to be built using a single insertps instruction. Also optimize when we move one element in a vector to a different place in that vector while zeroing out some of the other elements. Further optimizations are possible, described in TODO comments. I will be implementing at least some of them in the near future. Added some tests for different cases where this optimization triggers. Reviewers: nadav, delena, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3521 llvm-svn: 208271
* IR: Don't allow non-default visibility on local linkageDuncan P. N. Exon Smith2014-05-0720-22/+169
| | | | | | | | | | | | | | | | | Visibilities of `hidden` and `protected` are meaningless for symbols with local linkage. - Change the assembler to reject non-default visibility on symbols with local linkage. - Change the bitcode reader to auto-upgrade `hidden` and `protected` to `default` when the linkage is local. - Update LangRef. <rdar://problem/16141113> llvm-svn: 208263
* [X86] Add a test case for r208252.Quentin Colombet2014-05-071-0/+30
| | | | | | | | | | | | | | | | | | | | | | | Prior to r208252, the FMA 231 family was marked as isCommutable. However the memory variants of this family are not commutable. Therefore, we did not implemented the findCommutedOpIndices for those variants and missed that the default implementation (more or less: commute indices 1 and 2) was firing behind our back. As a result, as demonstrated in the test case before the fix, we were transforming a = b * c + a into a = a * c + b. I.e., before r208252 we were generating for this test case: vmovaps %xmm0, %xmm1 vmoss (%rsi), %xmm0 vfmadd231ss (%rdi), %xmm1, %xmm0 Instead of: vmoss (%rsi), %xmm1 vfmadd231ss (%rdi), %xmm1, %xmm0 <rdar://problem/16800495> llvm-svn: 208260
* [Test] Remove c-index-test from the list of substitutionsAdam Nemet2014-05-071-1/+0
| | | | | | | | | | | All the tests are under the clang tests and none should be under llvm moving forward. The topic was discussed in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140428/214905.html llvm-svn: 208234
* split delinearization pass in 3 stepsSebastian Pop2014-05-0712-108/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To compute the dimensions of the array in a unique way, we split the delinearization analysis in three steps: - find parametric terms in all memory access functions - compute the array dimensions from the set of terms - compute the delinearized access functions for each dimension The first step is executed on all the memory access functions such that we gather all the patterns in which an array is accessed. The second step reduces all this information in a unique description of the sizes of the array. The third step is delinearizing each memory access function following the common description of the shape of the array computed in step 2. This rewrite of the delinearization pass also solves a problem we had with the previous implementation: because the previous algorithm was by induction on the structure of the SCEV, it would not correctly recognize the shape of the array when the memory access was not following the nesting of the loops: for example, see polly/test/ScopInfo/multidim_only_ivs_3d_reverse.ll ; void foo(long n, long m, long o, double A[n][m][o]) { ; ; for (long i = 0; i < n; i++) ; for (long j = 0; j < m; j++) ; for (long k = 0; k < o; k++) ; A[i][k][j] = 1.0; Starting with this patch we no longer delinearize access functions that do not contain parameters, for example in test/Analysis/DependenceAnalysis/GCD.ll ;; for (long int i = 0; i < 100; i++) ;; for (long int j = 0; j < 100; j++) { ;; A[2*i - 4*j] = i; ;; *B++ = A[6*i + 8*j]; these accesses will not be delinearized as the upper bound of the loops are constants, and their access functions do not contain SCEVUnknown parameters. llvm-svn: 208232
* [yaml2obj] Support ELF x86 relocations.Simon Atanasyan2014-05-071-0/+43
| | | | llvm-svn: 208228
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