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* Temp. labels number may not match for all configurations.Devang Patel2010-05-271-1/+1
| | | | llvm-svn: 104858
* inlined function's arguments need a label to mark the start point because ↵Devang Patel2010-05-271-0/+49
| | | | | | they are not directly attached to current function. llvm-svn: 104848
* Support for nested functions/classes in debug output. Radar 7424645.Stuart Hastings2010-05-271-1/+3
| | | | llvm-svn: 104841
* rename test to represent meaningful dateGabor Greif2010-05-271-0/+0
| | | | llvm-svn: 104831
* Add a test for llvm-gcc svn r104726.Bob Wilson2010-05-271-0/+12
| | | | llvm-svn: 104805
* Add a quick test of relocations.Eric Christopher2010-05-271-0/+174
| | | | llvm-svn: 104794
* Simplify. Eliminate unneeded debug_loc entry.Devang Patel2010-05-262-3/+3
| | | | llvm-svn: 104785
* Reinstate checking of stackrestore, with checking for both ReadDan Gohman2010-05-261-0/+3
| | | | | | and Write, and add a comment explaining this. llvm-svn: 104756
* Implement checking of the tail keyword.Dan Gohman2010-05-261-0/+12
| | | | llvm-svn: 104744
* Update debug info when live-in reg is copied into a vreg.Devang Patel2010-05-261-0/+66
| | | | llvm-svn: 104732
* Fix the x86 move to/from segment register instructions.Kevin Enderby2010-05-261-0/+29
| | | | llvm-svn: 104731
* Testcase for 104624/104619/PR7191/8023512.Dale Johannesen2010-05-261-0/+16
| | | | | | Reduced from one provided by Duncan Sands, thanks! llvm-svn: 104710
* First cut at supporting .debug_loc section. Devang Patel2010-05-251-0/+239
| | | | | | This is used to track variable information. llvm-svn: 104649
* Properly promote operands when optimizing a single-character memcmp.Benjamin Kramer2010-05-251-1/+13
| | | | llvm-svn: 104648
* Add support for initialized global data for darwin tls. Update commentsEric Christopher2010-05-251-87/+125
| | | | | | and testcases accordingly. llvm-svn: 104635
* Changed the encoding of X86 floating point stack operations where both operandsKevin Enderby2010-05-251-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. llvm-svn: 104634
* Removing test; Chris thinks it's better to have theDale Johannesen2010-05-251-2718/+0
| | | | | | bug go untested than have a testcase this large. So be it. llvm-svn: 104632
* MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.Daniel Dunbar2010-05-251-0/+34
| | | | llvm-svn: 104626
* Fix another variant of PR 7191. Also add a testcaseDale Johannesen2010-05-251-0/+2718
| | | | | | | | Mon Ping provided; unfortunately bugpoint failed to reduce it, but I think it's important to have a test for this in the suite. 8023512. llvm-svn: 104624
* MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.Daniel Dunbar2010-05-251-0/+25
| | | | llvm-svn: 104622
* The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is requiredKevin Enderby2010-05-251-0/+5
| | | | | | for the 64-bit version of the Bit Test instruction. llvm-svn: 104621
* Make sure aeskeygenassist uses an unsigned immediate field.Eric Christopher2010-05-251-2/+7
| | | | | | Fixes rdar://8017638 llvm-svn: 104617
* Fix an mmx movd encoding.Dan Gohman2010-05-241-0/+32
| | | | llvm-svn: 104552
* MC/X86: Add aliases for CMOVcc variants.Kevin Enderby2010-05-241-0/+129
| | | | llvm-svn: 104549
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-241-0/+9
| | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. llvm-svn: 104531
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-241-0/+2
| | | | llvm-svn: 104518
* MC/X86: Subdivide immediates a bit more, so that we properly recognize ↵Daniel Dunbar2010-05-221-0/+105
| | | | | | | | | | | immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
* MC/X86: Add alias for setz, setnz, jz, jnz.Daniel Dunbar2010-05-221-1/+18
| | | | llvm-svn: 104435
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-222-2/+29
| | | | llvm-svn: 104421
* This test is darwin only. Make it so(tm).Eric Christopher2010-05-221-1/+1
| | | | llvm-svn: 104418
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-223-2/+47
| | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. llvm-svn: 104415
* Add full bss data support for darwin tls variables.Eric Christopher2010-05-221-0/+19
| | | | llvm-svn: 104414
* Added retl for 32-bit x86 and added retq for 64-bit x86.Kevin Enderby2010-05-212-0/+10
| | | | llvm-svn: 104394
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-211-7/+7
| | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. llvm-svn: 104380
* now that fp reg kill insertion stuff happens as a separateChris Lattner2010-05-211-0/+25
| | | | | | | | | | | | | | | | | | pass after isel instead of being interlaced with it, we can trust that all the code for a function has been isel'd before it is run. The practical impact of this is that we can scan for machine instr phis instead of doing a fuzzy match on the LLVM BB for phi nodes. Doing the fuzzy match required knowing when isel would produce an fp reg stack phi which was gross. It was also wrong in cases where select got lowered to a branch tree because cmovs aren't available (PR6828). Just do the scan on machine phis which is simpler, faster and more correct. This fixes PR6828. llvm-svn: 104333
* Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen2010-05-211-0/+45
| | | | | | | | | | | | | definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. llvm-svn: 104321
* Fix i64->f64 conversion, x86-64, -no-sse. A bitDale Johannesen2010-05-211-0/+12
| | | | | | | tricky since there's a 3rd 64-bit type, MMX vectors. PR 7135. llvm-svn: 104308
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-218-14/+14
| | | | | | point instructions (and is not using soft float). llvm-svn: 104307
* MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with ↵Daniel Dunbar2010-05-201-0/+20
| | | | | | movq. llvm-svn: 104275
* When canonicalizing icmp operand order to put the loop invariantDan Gohman2010-05-202-230/+256
| | | | | | | | | | | | operand on the left, the interesting operand is on the right. This fixes a bug where LSR was failing to recognize ICmpZero uses, which led it to be unable to reverse the induction variable in the attached testcase. Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test is extremely fragile and hard to meaningfully update. llvm-svn: 104262
* Handle Neon v2f64 and v2i64 vector shuffles as register copies.Bob Wilson2010-05-201-0/+7
| | | | | | This fixes the remaining issue with pr7167. llvm-svn: 104257
* Fix assembly parsing and encoding of the pushf and popf family ofDan Gohman2010-05-203-0/+29
| | | | | | instructions. llvm-svn: 104231
* Define the x86 pause instruction.Dan Gohman2010-05-202-0/+9
| | | | llvm-svn: 104204
* Fix the sfence instruction to use MRM_F8 instead of MRM7r, since itDan Gohman2010-05-201-0/+3
| | | | | | | doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. llvm-svn: 104203
* Match "4" or "8" depending upon if it's 32- or 64-bit.Bill Wendling2010-05-201-2/+2
| | | | llvm-svn: 104196
* Once more, with feeling.Eric Christopher2010-05-201-0/+1
| | | | llvm-svn: 104190
* Teach LSR how to cope better with unrolled loops on targets whereDan Gohman2010-05-191-0/+386
| | | | | | | | the addressing modes don't make this trivially easy. This allows it to avoid falling into the less precise heuristics in more cases. llvm-svn: 104186
* fix rdar://7986634 - match instruction opcodes case insensitively.Chris Lattner2010-05-191-0/+5
| | | | llvm-svn: 104183
* Testcase for r104181.Bill Wendling2010-05-191-0/+33
| | | | llvm-svn: 104182
* A more combo tls testcase.Eric Christopher2010-05-191-0/+232
| | | | llvm-svn: 104163
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