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* [X86] Remove llvm.x86.bit.scan.{forward,reverse}.32David Majnemer2016-06-131-23/+0
| | | | | | | The need for these intrinsics has been obviated by r272564 which reimplements their functionality using generic IR. llvm-svn: 272566
* Add triple to input file.Rafael Espindola2016-06-131-0/+1
| | | | | | Patch by H.J. Lu. llvm-svn: 272563
* AMDGPU/SI: Set INDEX_STRIDE for scratch coalescingMarek Olsak2016-06-134-10/+10
| | | | | | | | | | | | | | | | | Summary: Mesa and other users must set this to enable coalescing: - STRIDE = 0 - SWIZZLE_ENABLE = 1 This makes one particular compute shader 8x faster. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21136 llvm-svn: 272556
* [SystemZ] Enable index register memory constraints for inline ASMUlrich Weigand2016-06-133-8/+95
| | | | | | | | | | | | | | | | This enables use of the 'R' and 'T' memory constraints for inline ASM operands on SystemZ, which allow an index register as well as an immediate displacement. This patch includes corresponding documentation and test case updates. As with the last patch of this kind, I moved the 'm' constraint to the most general case, which is now 'T' (base + 20-bit signed displacement + index register). Author: colpell Differential Revision: http://reviews.llvm.org/D21239 llvm-svn: 272547
* [ARM] Reverting r272544 because clang patch needsRanjeet Singh2016-06-131-8/+0
| | | | | | | to go in as soon as llvm patch has gone in because tests will start breaking in Clang. llvm-svn: 272546
* [ARM] Add mrrc/mrrc2 co-processor intrinsicsRanjeet Singh2016-06-131-0/+8
| | | | | | | | | | | | | MRRC/MRRC2 instruction writes to two registers. The intrinsic definition returns a single uint64_t to represent the write, this is a compact way of representing a write to two 32 bit registers, the alternative might have been two return a struct of 2 uint32_t's but this isn't as nice. Differential Revision: llvm-svn: 272544
* This patch fixes handling long double type when it isStrahinja Petrovic2016-06-131-0/+24
| | | | | | constant in soft float mode on PowerPC 32 architecture. llvm-svn: 272543
* [X86][SSE4A] Renamed tests to correspond with the the instruction with being ↵Simon Pilgrim2016-06-131-18/+18
| | | | | | tested llvm-svn: 272542
* [AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and ↵Craig Topper2016-06-138-219/+217
| | | | | | autoupgrade them to selects and shufflevector. llvm-svn: 272527
* [x86, SSE] change patterns for CMPP to float types to allow matching with ↵Sanjay Patel2016-06-121-49/+2
| | | | | | | | | | | | | | | | | | | | | | | | | SSE1 (PR28044) This patch is intended to solve: https://llvm.org/bugs/show_bug.cgi?id=28044 By changing the definition of X86ISD::CMPP to use float types, we allow it to be created and pass legalization for an SSE1-only target where v4i32 is not legal. The motivational trail for this change includes: https://llvm.org/bugs/show_bug.cgi?id=28001 and eventually makes this trigger: http://reviews.llvm.org/D21190 Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86 intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86 intrinsics, a big pile of generic optimizations can trigger. Differential Revision: http://reviews.llvm.org/D21235 llvm-svn: 272511
* [X86] Remove sse2 pshufd/pshuflw/pshufhw intrinsics and upgrade them to ↵Craig Topper2016-06-123-52/+40
| | | | | | shufflevector. llvm-svn: 272510
* [X86][BMI] Added fast-isel tests for BMI1 intrinsicsSimon Pilgrim2016-06-122-0/+491
| | | | | | A lot of the codegen is pretty awful for these as they are mostly implemented as generic bit twiddling ops llvm-svn: 272508
* [PM] Port DeadArgumentElimination to the new PMSean Silva2016-06-121-1/+1
| | | | | | | | | The approach taken here follows r267631. deadarghaX0r should be easy to port when the time comes to add new-PM support to bugpoint. llvm-svn: 272507
* [PM] Port ReversePostOrderFunctionAttrs to the new PMSean Silva2016-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Below are my super rough notes when porting. They can probably serve as a basic guide for porting other passes to the new PM. As I port more passes I'll expand and generalize this and make a proper docs/HowToPortToNewPassManager.rst document. There is also missing documentation for general concepts and API's in the new PM which will require some documentation. Once there is proper documentation in place we can put up a list of passes that have to be ported and game-ify/crowdsource the rest of the porting (at least of the middle end; the backend is still unclear). I will however be taking personal responsibility for ensuring that the LLD/ELF LTO pipeline is ported in a timely fashion. The remaining passes to be ported are (do something like `git grep "<the string in the bullet point below>"` to find the pass): General Scalar: [ ] Simplify the CFG [ ] Jump Threading [ ] MemCpy Optimization [ ] Promote Memory to Register [ ] MergedLoadStoreMotion [ ] Lazy Value Information Analysis General IPO: [ ] Dead Argument Elimination [ ] Deduce function attributes in RPO Loop stuff / vectorization stuff: [ ] Alignment from assumptions [ ] Canonicalize natural loops [ ] Delete dead loops [ ] Loop Access Analysis [ ] Loop Invariant Code Motion [ ] Loop Vectorization [ ] SLP Vectorizer [ ] Unroll loops Devirtualization / CFI: [ ] Cross-DSO CFI [ ] Whole program devirtualization [ ] Lower bitset metadata CGSCC passes: [ ] Function Integration/Inlining [ ] Remove unused exception handling info [ ] Promote 'by reference' arguments to scalars Please let me know if you are interested in working on any of the passes in the above list (e.g. reply to the post-commit thread for this patch). I'll probably be tackling "General Scalar" and "General IPO" first FWIW. Steps as I port "Deduce function attributes in RPO" --------------------------------------------------- (note: if you are doing any work based on these notes, please leave a note in the post-commit review thread for this commit with any improvements / suggestions / incompleteness you ran into!) Note: "Deduce function attributes in RPO" is a module pass. 1. Do preparatory refactoring. Do preparatory factoring. In this case all I had to do was to pull out a static helper (r272503). (TODO: give more advice here e.g. if pass holds state or something) 2. Rename the old pass class. llvm/lib/Transforms/IPO/FunctionAttrs.cpp Rename class ReversePostOrderFunctionAttrs -> ReversePostOrderFunctionAttrsLegacyPass in preparation for adding a class ReversePostOrderFunctionAttrs as the pass in the new PM. (edit: actually wait what? The new class name will be ReversePostOrderFunctionAttrsPass, so it doesn't conflict. So this step is sort of useless churn). llvm/include/llvm/InitializePasses.h llvm/lib/LTO/LTOCodeGenerator.cpp llvm/lib/Transforms/IPO/IPO.cpp llvm/lib/Transforms/IPO/FunctionAttrs.cpp Rename initializeReversePostOrderFunctionAttrsPass -> initializeReversePostOrderFunctionAttrsLegacyPassPass (note that the "PassPass" thing falls out of `s/ReversePostOrderFunctionAttrs/ReversePostOrderFunctionAttrsLegacyPass/`) Note that the INITIALIZE_PASS macro is what creates this identifier name, so renaming the class requires this renaming too. Note that createReversePostOrderFunctionAttrsPass does not need to be renamed since its name is not generated from the class name. 3. Add the new PM pass class. In the new PM all passes need to have their declaration in a header somewhere, so you will often need to add a header. In this case llvm/include/llvm/Transforms/IPO/FunctionAttrs.h is already there because PostOrderFunctionAttrsPass was already ported. The file-level comment from the .cpp file can be used as the file-level comment for the new header. You may want to tweak the wording slightly from "this file implements" to "this file provides" or similar. Add declaration for the new PM pass in this header: class ReversePostOrderFunctionAttrsPass : public PassInfoMixin<ReversePostOrderFunctionAttrsPass> { public: PreservedAnalyses run(Module &M, AnalysisManager<Module> &AM); }; Its name should end with `Pass` for consistency (note that this doesn't collide with the names of most old PM passes). E.g. call it `<name of the old PM pass>Pass`. Also, move the doxygen comment from the old PM pass to the declaration of this class in the header. Also, include the declaration for the new PM class `llvm/Transforms/IPO/FunctionAttrs.h` at the top of the file (in this case, it was already done when the other pass in this file was ported). Now define the `run` method for the new class. The main things here are: a) Use AM.getResult<...>(M) to get results instead of `getAnalysis<...>()` b) If the old PM pass would have returned "false" (i.e. `Changed == false`), then you should return PreservedAnalyses::all(); c) In the old PM getAnalysisUsage method, observe the calls `AU.addPreserved<...>();`. In the case `Changed == true`, for each preserved analysis you should do call `PA.preserve<...>()` on a PreservedAnalyses object and return it. E.g.: PreservedAnalyses PA; PA.preserve<CallGraphAnalysis>(); return PA; Note that calls to skipModule/skipFunction are not supported in the new PM currently, so optnone and optimization bisect support do not work. You can just drop those calls for now. 4. Add the pass to the new PM pass registry to make it available in opt. In llvm/lib/Passes/PassBuilder.cpp add a #include for your header. `#include "llvm/Transforms/IPO/FunctionAttrs.h"` In this case there is already an include (from when PostOrderFunctionAttrsPass was ported). Add your pass to llvm/lib/Passes/PassRegistry.def In this case, I added `MODULE_PASS("rpo-functionattrs", ReversePostOrderFunctionAttrsPass())` The string is from the `INITIALIZE_PASS*` macros used in the old pass manager. Then choose a test that uses the pass and use the new PM `-passes=...` to run it. E.g. in this case there is a test that does: ; RUN: opt < %s -basicaa -functionattrs -rpo-functionattrs -S | FileCheck %s I have added the line: ; RUN: opt < %s -aa-pipeline=basic-aa -passes='require<targetlibinfo>,cgscc(function-attrs),rpo-functionattrs' -S | FileCheck %s The `-aa-pipeline=basic-aa` and `require<targetlibinfo>,cgscc(function-attrs)` are what is needed to run functionattrs in the new PM (note that in the new PM "functionattrs" becomes "function-attrs" for some reason). This is just pulled from `readattrs.ll` which contains the change from when functionattrs was ported to the new PM. Adding rpo-functionattrs causes the pass that was just ported to run. llvm-svn: 272505
* Make sure we have a Add/Remove/Has function for various thing that can have ↵Amaury Sechet2016-06-121-4/+5
| | | | | | | | | | | | | | attribute. Summary: This also deprecated the get attribute function familly. Reviewers: Wallbraker, whitequark, joker.eph, echristo, rafael, jyknight Subscribers: axw, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19181 llvm-svn: 272504
* [MergedLoadStoreMotion] Use correct helper for load hoist safety.Eli Friedman2016-06-121-2/+3
| | | | | | | | | It isn't legal to hoist a load past a call which might not return; even if it doesn't throw, it could, for example, call exit(). Fixes http://llvm.org/PR27953. llvm-svn: 272495
* [X86] Move tests for llvm.x86.avx.vpermil.* intrinsics to a -upgrade test ↵Craig Topper2016-06-122-68/+48
| | | | | | since they are autoupgraded to shufflevector. llvm-svn: 272494
* [LICM] Make isGuaranteedToExecute more accurate.Eli Friedman2016-06-116-12/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Make isGuaranteedToExecute use the isGuaranteedToTransferExecutionToSuccessor helper, and make that helper a bit more accurate. There's a potential performance impact here from assuming that arbitrary calls might not return. This probably has little impact on loads and stores to a pointer because most things alias analysis can reason about are dereferenceable anyway. The other impacts, like less aggressive hoisting of sdiv by a variable and less aggressive hoisting around volatile memory operations, are unlikely to matter for real code. This also impacts SCEV, which uses the same helper. It's a minor improvement there because we can tell that, for example, memcpy always returns normally. Strictly speaking, it's also introducing a bug, but it's not any worse than everywhere else we assume readonly functions terminate. Fixes http://llvm.org/PR27857. Reviewers: hfinkel, reames, chandlerc, sanjoy Subscribers: broune, llvm-commits Differential Revision: http://reviews.llvm.org/D21167 llvm-svn: 272489
* [X86] Updated test checks script to generalise LCPI symbol refsSimon Pilgrim2016-06-118-57/+57
| | | | | | | | The script now replace '.LCPI888_8' style asm symbols with the {{\.LCPI.*}} re pattern - this helps stop hardcoded symbols in 32-bit x86 tests changing with every edit of the file Refreshed some tests to demonstrate the new check llvm-svn: 272488
* [CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targetsSimon Pilgrim2016-06-112-292/+67
| | | | | | To account for the fast PSHUFB implementation now available llvm-svn: 272484
* [X86][SSSE3] Added PSHUFB LUT implementation of BITREVERSESimon Pilgrim2016-06-111-946/+380
| | | | | | PSHUFB can speed up BITREVERSE of byte vectors by performing LUT on the low/high nibbles separately and ORing the results. Wider integer vector types are already BSWAP'd beforehand so also make use of this approach. llvm-svn: 272477
* [AVX512] Re-generate v8i64 shuffle test now that we use pshufd for some cases.Craig Topper2016-06-111-13/+7
| | | | llvm-svn: 272474
* [AVX512] Lower v8i64 and v16i32 to pshufd when possible.Craig Topper2016-06-113-14/+33
| | | | llvm-svn: 272473
* [X86][SSE] Added PSLLDQ/PSRLDQ as a target shuffle typeSimon Pilgrim2016-06-113-16/+7
| | | | | | Ensure that PALIGNR/PSLLDQ/PSRLDQ are byte vectors so that they can be correctly decoded for target shuffle combining llvm-svn: 272471
* [X86][AVX2] Added PSLLDQ/PSRLDQ shuffle combining testsSimon Pilgrim2016-06-111-0/+22
| | | | llvm-svn: 272469
* [AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This ↵Craig Topper2016-06-111-1/+29
| | | | | | allows us to create 512-bit PSHUFLW/PSHUFHW. llvm-svn: 272450
* [esan|cfrag] Handle complex GEP instr in the cfrag toolQin Zhao2016-06-101-0/+38
| | | | | | | | | | | | | | | | Summary: Iterates all (except the first and the last) operands within each GEP instruction for instrumentation. Adds test struct_field_gep.ll. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, bruening, llvm-commits Differential Revision: http://reviews.llvm.org/D21242 llvm-svn: 272442
* [IRTranslator] Support the translation of or.Quentin Colombet2016-06-101-0/+23
| | | | | | Now or instructions get translated into G_OR. llvm-svn: 272433
* [x86] enable bitcasted fabs/fneg transformsSanjay Patel2016-06-101-4/+2
| | | | | | | The vector cases don't change because we already have folds in X86ISelLowering to look through and remove bitcasts. llvm-svn: 272427
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-104-0/+583
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocationsTom Stellard2016-06-101-2/+4
| | | | | | | | | | | | | | | Summary: We need to set the fixup type to FK_Data_4 for the SCRATCH_RSRC_DWORD[01] symbols, since these require absolute relocations, and fixup_si_rodata is for relative relocations. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21153 llvm-svn: 272417
* Move CodeGen test from Generic to X86 specific directoryMehdi Amini2016-06-101-0/+0
| | | | llvm-svn: 272416
* Interprocedural Register Allocation (IPRA): add a Transformation PassMehdi Amini2016-06-101-0/+32
| | | | | | | | | | | | Adds a MachineFunctionPass that scans the body to find calls, and update the register mask with the one saved by the RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21180 llvm-svn: 272414
* [x86] add test for PR28044Sanjay Patel2016-06-101-0/+62
| | | | llvm-svn: 272411
* test: split test into two filesSaleem Abdulrasool2016-06-102-38/+39
| | | | | | | Split up the test cases into two inputs as per post-commit review comments from Renato. NFC. llvm-svn: 272408
* [X86] Add costs for SSE zext/sext to v4i64 to TTIMichael Kuperstein2016-06-101-0/+79
| | | | | | | | | The costs are somewhat hand-wavy, but should be much closer to the truth than what we get from BasicTTI. Differential Revision: http://reviews.llvm.org/D21156 llvm-svn: 272406
* Interprocedural Register Allocation (IPRA) AnalysisMehdi Amini2016-06-102-0/+32
| | | | | | | | | | | | | | | | | | | | | | | Add an option to enable the analysis of MachineFunction register usage to extract the list of clobbered registers. When enabled, the CodeGen order is changed to be bottom up on the Call Graph. The analysis is split in two parts, RegUsageInfoCollector is the MachineFunction Pass that runs post-RA and collect the list of clobbered registers to produce a register mask. An immutable pass, RegisterUsageInfo, stores the RegMask produced by RegUsageInfoCollector, and keep them available. A future tranformation pass will use this information to update every call-sites after instruction selection. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D20769 llvm-svn: 272403
* [x86] fix test attributes and autogenerate checksSanjay Patel2016-06-101-37/+50
| | | | llvm-svn: 272398
* [x86] add missing tests for fcmp ueq/oneSanjay Patel2016-06-101-0/+212
| | | | | | | | | | | | Somehow, the codegen logic for these sequences has gone completely untested until now (note the 2 compare instructions generated per test). There's also an *Intel* AVX optimization opportunity exposed in these cases and the existing tests. Intel's (but not AMD's) AVX spec shows that extra FP predicates were added, so a single comparison should always be sufficient, and operand commutation should never be necessary. llvm-svn: 272397
* [x86] regenerate checksSanjay Patel2016-06-101-184/+309
| | | | llvm-svn: 272396
* Reapply "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-101-0/+42
| | | | | | | | This reapplies commit r272385 with a fix. The build was failing when compiled with gcc, but not with clang. With the fix, we now get the data layout from the current TTI implementation, which will hopefully solve the issue. llvm-svn: 272395
* [X86][SSE] Added target shuffle combine tests for byte shift/rotates ↵Simon Pilgrim2016-06-101-0/+50
| | | | | | (PSLLDQ/PSRLDQ/PALIGNR) llvm-svn: 272392
* Revert "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-101-42/+0
| | | | | | | This reverts commit r272385. This commit broke the build. I'm temporarily reverting to investigate. llvm-svn: 272391
* [TTI] Refine default cost for interleaved load groups with gapsMatthew Simpson2016-06-101-0/+42
| | | | | | | | | | | | This patch refines the default cost for interleaved load groups having gaps. If a load group has gaps, the legalized instructions corresponding to the unused elements will be dead. Thus, we don't need to account for them in the cost model. Instead, we only need to account for the fraction of legalized loads that will actually be used. Differential Revision: http://reviews.llvm.org/D20873 llvm-svn: 272385
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning ↵Sam Kolton2016-06-101-6/+14
| | | | | | | | | | | | | | | | | | in AMDGPUOperand. Summary: sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported. Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier. Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers. Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...). Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20968 llvm-svn: 272384
* [X86][AVX512] Added VPSLLDQ/VPSRLDQ memory fold testsSimon Pilgrim2016-06-101-12/+44
| | | | | | | | | | Memory operand is new for AVX512 (SSE/AVX2 didn't support it). Also dropped the 'mask' from the tests (VPSLLDQ/VPSRLDQ don't support masked operations). Regenerated VPALIGNR test now that the shuffle comments work llvm-svn: 272383
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-101-0/+4
| | | | llvm-svn: 272371
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-105-53/+53
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* [esan|cfrag] Add the struct field offset array in StructInfoQin Zhao2016-06-101-2/+37
| | | | | | | | | | | | | | | Summary: Adds the struct field offset array in struct StructInfo. Updates test struct_field_count_basic.ll. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21192 llvm-svn: 272362
* [LiveRangeEdit] Add a test case for r272314.Quentin Colombet2016-06-101-0/+268
| | | | | | | | | | The test case is not great espicially because it is still cumbersome to run the regalloc pass with run-pass. (We miss a bunch of initiliazier to be properly implemented.) Related to llvm.org/PR27983 llvm-svn: 272360
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