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* [X86] Add AVX 256-bit load and stores to fast isel.Craig Topper2016-06-021-9/+9
| | | | | | | | I'm not sure why this was missing for so long. This also exposed that we were picking floating point 256-bit VMOVNTPS for some integer types in normal isel for AVX1 even though VMOVNTDQ is available. In practice it doesn't matter due to the execution dependency fix pass, but it required extra isel patterns. Fixing that in a follow up commit. llvm-svn: 271481
* [AVX512] Remove masked load intrinsics. Clang now emits generic masked load ↵Craig Topper2016-06-028-564/+564
| | | | | | | | intrinsics instead. The intrinsics will be autoupgraded to the same generic masked loads. llvm-svn: 271478
* make icall pass name consistent /NFCXinliang David Li2016-06-022-4/+4
| | | | llvm-svn: 271467
* Avoid a load for local functions.Rafael Espindola2016-06-011-0/+10
| | | | llvm-svn: 271437
* [x86, AVX2] regenerate checksSanjay Patel2016-06-011-4/+10
| | | | llvm-svn: 271434
* [MemorySSA] Port to new pass managerGeoff Berry2016-06-0116-16/+32
| | | | | | | | | | | | | | | | | Add support for the new pass manager to MemorySSA pass. Change MemorySSA to be computed eagerly upon construction. Change MemorySSAWalker to be owned by the MemorySSA object that creates it. Reviewers: dberlin, george.burgess.iv Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19664 llvm-svn: 271432
* [DAG] Improve legalization of INSERT_SUBVECTORMichael Kuperstein2016-06-011-112/+33
| | | | | | | | | When the index is known to be constant 0, insert directly into the the low half, instead of spilling, performing the insert in-memory, and reloading. Differential Revision: http://reviews.llvm.org/D20763 llvm-svn: 271428
* [PPC64] Fix SUBFC8 Defs listKeno Fischer2016-06-011-0/+143
| | | | | | | | | | | | | Fix PR27943 "Bad machine code: Using an undefined physical register". SUBFC8 implicitly defines the CR0 register, but this was omitted in the instruction definition. Patch by Jameson Nash <jameson@juliacomputing.com> Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D20802 llvm-svn: 271425
* Revert "Claim NoAlias if two GEPs index different fields of the same struct"Daniel Berlin2016-06-012-113/+81
| | | | | | This reverts commit 2d5d6493f43eb68493a3852b8c226ac9fafdc7eb. llvm-svn: 271422
* [CFLAA] Recognize builtin allocation functions.George Burgess IV2016-06-011-0/+30
| | | | | | | | | | | This patch extends CFLAA to recognize allocation functions such as malloc, free, etc, so we can treat them more aggressively. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D20776 llvm-svn: 271421
* Claim NoAlias if two GEPs index different fields of the same structDaniel Berlin2016-06-012-81/+113
| | | | | | | | | | | | | | Patch by Taewook Oh Summary: Patch for Bug 27478. Make BasicAliasAnalysis claims NoAlias if two GEPs index different fields of the same structure. Reviewers: hfinkel, dberlin Subscribers: dberlin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20665 llvm-svn: 271415
* Better fix for PR27903.Than McIntosh2016-06-011-57/+54
| | | | | | | | | | | | | | | | | Summary: Re-enable lifetime-start-on-first-use for stack coloring, but explicitly disable it for slots with more than one start or end lifetime marker. Bug: 27903 Reviewers: wmi, tejohnson, qcolombet, gbiv Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20739 llvm-svn: 271412
* [LV] For some IVs, use vector phis instead of widening in the loop bodyMichael Kuperstein2016-06-018-20/+85
| | | | | | | | | | | | | Previously, whenever we needed a vector IV, we would create it on the fly, by splatting the scalar IV and adding a step vector. Instead, we can create a real vector IV. This tends to save a couple of instructions per iteration. This only changes the behavior for the most basic case - integer primary IVs with a constant step. Differential Revision: http://reviews.llvm.org/D20315 llvm-svn: 271410
* [codeview] Translate basic DITypes to CV type recordsReid Kleckner2016-06-012-31/+431
| | | | | | | | | | | | | | | Summary: This is meant to be the tiniest step towards DIType to CV type index translation that I could come up with. Whenever translation fails, we use type index zero, which is the unknown type. Reviewers: aaboud, zturner Subscribers: llvm-commits, amccarth Differential Revision: http://reviews.llvm.org/D20840 llvm-svn: 271408
* Reduce dependence on pointee types when deducing dereferenceabilitySanjoy Das2016-06-011-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Change some of the internal interfaces in Loads.cpp to keep track of the number of bytes we're trying to prove dereferenceable using an explicit `Size` parameter. Before this, the `Size` parameter was implicitly inferred from the pointee type of the pointer whose dereferenceability we were trying to prove, causing us to be conservative around bitcasts. This was unfortunate since bitcast instructions are no-ops and should never break optimizations. With an explicit `Size` parameter, we're more precise (as shown in the test cases), and the code is simpler. We should eventually move towards a `DerefQuery` struct that groups together a base pointer, an offset, a size and an alignment; but this patch is a first step. Reviewers: apilipenko, dblaikie, hfinkel, reames Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20764 llvm-svn: 271406
* [IR] Disallow loading and storing unsized typesSanjoy Das2016-06-011-0/+24
| | | | | | | | | | | | | | | | Summary: It isn't clear what is the operational meaning of loading or storing an unsized types, since it cannot be lowered into something meaningful. Since there does not seem to be any practical need for it either, make such loads and stores illegal IR. Reviewers: majnemer, chandlerc Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20846 llvm-svn: 271402
* [X86][SSE] Added non-temporal store tests for all 512-bit vector typesSimon Pilgrim2016-06-011-57/+224
| | | | llvm-svn: 271393
* [X86][SSE] Added non-temporal store tests for all 256-bit vector typesSimon Pilgrim2016-06-011-0/+185
| | | | | | Also added KNL AVX-512 checks llvm-svn: 271391
* [X86][SSE] Added non-temporal store tests for all 128-bit integer vector typesSimon Pilgrim2016-06-011-0/+45
| | | | llvm-svn: 271389
* Adding back-end support to two bit scanning intrinsicsMichael Zuckerman2016-06-011-0/+23
| | | | | | | | | | | | | | Adding LLVM back-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse. Their functionality is as described in Intel intrinsics guide: https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370 Commit on behalf of Omer Paparo Bivas Differential Revision: http://reviews.llvm.org/D19915 llvm-svn: 271386
* [ARM] Add additional matching for UBFX instructionsOliver Stannard2016-06-011-0/+16
| | | | | | | | | | | This adds an additional matcher to select UBFX(..) from SRL(AND(..)) in ARMISelDAGToDAG to help with code size. Patch by David Green. Differential Revision: http://reviews.llvm.org/D20667 llvm-svn: 271384
* [Sparc] Allow passing of empty structs.Chris Dewhurst2016-06-011-0/+51
| | | | | | | | Passing an empty struct as a function call argument is now supported. unit tests for various scenarios added. llvm-svn: 271374
* Revert r271362 "[AVX512] Remove masked load intrinsics. Clang now emits ↵Craig Topper2016-06-012-8/+10
| | | | | | | | generic masked load intrinsics instead." Looks like something isn't quite right still. Also forgot to move the test cases to an autoupgrade test. llvm-svn: 271363
* [AVX512] Remove masked load intrinsics. Clang now emits generic masked load ↵Craig Topper2016-06-012-10/+8
| | | | | | | | intrinsics instead. The intrinsics will be autoupgraded to the same generic masked loads. llvm-svn: 271362
* IR: Allow multiple global metadata attachments with the same type.Peter Collingbourne2016-06-012-3/+8
| | | | | | | | | | This will be necessary to allow the global merge pass to attach multiple debug info metadata nodes to global variables once we reverse the edge from DIGlobalVariable to GlobalVariable. Differential Revision: http://reviews.llvm.org/D20414 llvm-svn: 271358
* Add support for metadata attachments for global variables.Peter Collingbourne2016-05-311-5/+14
| | | | | | | | | | This patch adds an IR, assembly and bitcode representation for metadata attachments for globals. Future patches will port existing features to use these new attachments. Differential Revision: http://reviews.llvm.org/D20074 llvm-svn: 271348
* CodeGen: Refactor renameDisconnectedComponents() as a passMatthias Braun2016-05-311-0/+30
| | | | | | | | | | | | | | | | | | Refactor LiveIntervals::renameDisconnectedComponents() to be a pass. Also change the name to "RenameIndependentSubregs": - renameDisconnectedComponents() worked on a MachineFunction at a time so it is a natural candidate for a machine function pass. - The algorithm is testable with a .mir test now. - This also fixes a problem where the lazy renaming as part of the MachineScheduler introduced IMPLICIT_DEF instructions after the number of a nodes in a region were counted leading to a mismatch. Differential Revision: http://reviews.llvm.org/D20507 llvm-svn: 271345
* [X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid ↵Kevin B. Smith2016-05-311-0/+32
| | | | | | | | falsely marking whole 32 bit register as live. Differential Revision: http://reviews.llvm.org/D20649 llvm-svn: 271341
* ARM: Improve/fix comment in recently added test.Matthias Braun2016-05-311-2/+2
| | | | llvm-svn: 271340
* ARM: Do not attempt to modify register class of physregs.Matthias Braun2016-05-311-0/+11
| | | | | | | Physregs have no associated register class, do not attempt to modify it in Thumb2InstrInfo::storeRegToStackSlot()/loadFromStackSlot(). llvm-svn: 271339
* [SLP] Pass in correct alignment when query memory access costGuozhi Wei2016-05-312-0/+31
| | | | | | | | | | This patch fixes bug https://llvm.org/bugs/show_bug.cgi?id=27897. When query memory access cost, current SLP always passes in alignment value of 1 (unaligned), so it gets a very high cost of scalar memory access, and wrongly vectorize memory loads in the test case. It can be fixed by simply giving correct alignment. llvm-svn: 271333
* Change llvm-objdump, llvm-nm and llvm-size when reporting an object file errorKevin Enderby2016-05-315-0/+13
| | | | | | | | | | | | | | | | | | | when the object is from a slice of a Mach-O Universal Binary use something like "foo.o (for architecture i386)" as part of the error message when expected. Also fixed places in these tools that were ignoring object file errors from MachOUniversalBinary::getAsObjectFile() when the code moved on to see if the slice was an archive. To do this MachOUniversalBinary::getAsObjectFile() and MachOUniversalBinary::getObjectForArch() were changed from returning ErrorOr<...> to Expected<...> then that was threaded up to its users. Converting these interfaces to Expected<> from ErrorOr<> does involve touching a number of places. To contain the changes for now the use of errorToErrorCode() is still used in two places yet to be fully converted. llvm-svn: 271332
* [CFLAA] Don't link GEP pointers to GEP indices.George Burgess IV2016-05-311-0/+14
| | | | | | | | | | | | | | | | | Code like the following is considered broken, and doesn't need to be supported by our AA magicks: void getFoo(int *P) { int *PAlias = (int *)((char *)NULL + (uintptr_t)P); } This patch makes CFLAA drop support for code like this. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D20775 llvm-svn: 271322
* [CodeGen] Promote FMINNAN/FMAXNAN like other binops.Ahmed Bougacha2016-05-311-0/+34
| | | | | | | | We think it's OK to generate half fminnan because it's legal for the transform-to type (f32; r245196). However, PromoteFloatRes was missing the case; simply promote like the other binops, including minnum. llvm-svn: 271317
* [codeview] Improve readability of type record assemblyReid Kleckner2016-05-311-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the method MCStreamer::EmitBinaryData, which is usually an alias for EmitBytes. In the MCAsmStreamer case, it is overridden to emit hex dump output like this: .byte 0x0e, 0x00, 0x08, 0x10 .byte 0x03, 0x00, 0x00, 0x00 .byte 0x00, 0x00, 0x00, 0x00 .byte 0x00, 0x10, 0x00, 0x00 Also, when verbose asm comments are enabled, this patch prints the dump output for each comment before its record, like this: # ArgList (0x1000) { # TypeLeafKind: LF_ARGLIST (0x1201) # NumArgs: 0 # Arguments [ # ] # } .byte 0x06, 0x00, 0x01, 0x12 .byte 0x00, 0x00, 0x00, 0x00 This should make debugging easier and testing more convenient. Reviewers: aaboud Subscribers: majnemer, zturner, amccarth, aaboud, llvm-commits Differential Revision: http://reviews.llvm.org/D20711 llvm-svn: 271313
* Delete AArch64II::MO_CONSTPOOL.Rafael Espindola2016-05-312-28/+2
| | | | | | | | A constant pool holding the address of a variable in equivalent to a got entry. It produces exactly the same instruction sequence as a got use and unlike a got use this is not uniqued by the linker. llvm-svn: 271311
* [mips] Remove tests which should have been deleted.Simon Dardis2016-05-312-38/+0
| | | | | | | The two xfail tests for mis32r6 & mips64r6 were supposed to be removed in r271301. llvm-svn: 271306
* [mips] Enforce compact branch register restrictionsSimon Dardis2016-05-314-20/+52
| | | | | | | | | | | | | | | Enforce compact branch register restrictions such as the use of the zero register, both operands being the same register. Emit clear error in such cases as the issue is subtle. For bovc and bnvc, silently fixup such cases when emitting objects directly, like LLVM started doing in rL269899. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D20475 llvm-svn: 271301
* [obj2yaml][yaml2obj] Support for reading and dumping the MachO export trieChris Bieneman2016-05-311-0/+191
| | | | | | The MachO export trie is a serially encoded trie keyed by symbol name. This code parses the trie and preserves the structure so that it can be dumped again. llvm-svn: 271300
* Fix a crash in MergeFunctions related to ordering of weak/strong functionsErik Eckstein2016-05-311-0/+47
| | | | | | | | | | | The assumption, made in insert() that weak functions are always inserted after strong functions, is only true in the first round of adding functions. In subsequent rounds this is no longer guaranteed , because we might remove a strong function from the tree (because it's modified) and add it later, where an equivalent weak function already exists in the tree. This change removes the assert in insert() and explicitly enforces a weak->strong order. This also removes the need of two separate loops in runOnModule(). llvm-svn: 271299
* [esan|cfrag] Create the skeleton of cfrag variable for the runtimeQin Zhao2016-05-312-3/+5
| | | | | | | | | | | | | | | | | Summary: Creates a global variable containing preliminary information for the cache-fragmentation tool runtime. Passes a pointer to the variable (null if no variable is created) to the compilation unit init and exit routines in the runtime. Reviewers: aizatsky, bruening Subscribers: filcab, kubabrecka, bruening, kcc, vitalybuka, eugenis, llvm-commits, zhaoqin Differential Revision: http://reviews.llvm.org/D20541 llvm-svn: 271298
* Add a use of shouldAssumeDSOLocal to ARM.Rafael Espindola2016-05-311-0/+18
| | | | | | Now this code path knows about position independent executables. llvm-svn: 271290
* [ARM] Add backend support for load/store intrinsics.Ranjeet Singh2016-05-313-7/+61
| | | | | | | | | | Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
* [X86][SSE] Add load-folding patterns for (V)CVTDQ2PD (PR27291)Simon Pilgrim2016-05-311-4/+2
| | | | | | Added patterns for (V)CVTDQ2PD -> 2f64 loading from a 64-bit source. llvm-svn: 271269
* [mips] bnec/beqc register constraint fixSimon Dardis2016-05-311-0/+55
| | | | | | | | | | | beqc and bnec cannot have $rs == $rt. Inhibit compact branch creation if that would occur. Reviewers: vkalintiris, dsanders Differential Revision: http://reviews.llvm.org/D20624 llvm-svn: 271260
* [AVX512] Fix intrinsic vcvtps2ph lowering.Igor Breger2016-05-312-9/+33
| | | | | | Differential Revision: http://reviews.llvm.org/D20788 llvm-svn: 271255
* Fix intrinsic vbroadcast{i32|f32}x2 lowering.Igor Breger2016-05-312-8/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D20780 llvm-svn: 271254
* [AVX512] Remove masked store intrinsics. Clang now emits generic masked ↵Craig Topper2016-05-318-440/+447
| | | | | | | | store intrinsics instead. The intrinsics will be autoupgraded to the same generic masked stores. llvm-svn: 271245
* X86: permit using SjLj EH on x86 targets as an optionSaleem Abdulrasool2016-05-311-0/+72
| | | | | | | | | | | This adds support to the backed to actually support SjLj EH as an exception model. This is *NOT* the default model, and requires explicitly opting into it from the frontend. GCC supports this model and for MinGW can still be enabled via the `--using-sjlj-exceptions` options. Addresses PR27749! llvm-svn: 271244
* [X86] Remove SSE/AVX unaligned store intrinsics as clang no longer uses ↵Craig Topper2016-05-309-231/+173
| | | | | | them. Auto upgrade to native unaligned store instructions. llvm-svn: 271236
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