summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* Unbreak test relying on debug output after r321540.Benjamin Kramer2017-12-281-0/+2
| | | | llvm-svn: 321541
* [X86] When lowering extending loads from v2i1/v4i1, if we have VLX, use a ↵Craig Topper2017-12-283-24/+13
| | | | | | | | | | | | narrower extend. Previously we used an extend from v8i1 to v8i32/v8i64. Then extracted to the final width. But if we have VLX we should extract first. This way we don't end up with an overly large extend. This allows us to use vcmpeq to make all ones for the sign extend when DQI isn't available. Otherwise we get a VPTERNLOG. If we make v2i1/v4i1 legal like proposed in D41560, we could always do this and rely on the lowering of the extend to widen when necessary. llvm-svn: 321538
* [WinEH] Don't emit state stores or EH thunks for available_externally functionsReid Kleckner2017-12-281-0/+28
| | | | | | | | | | The exception handler thunk needs to reference the LSDA of the parent function, which won't be emitted if it's available_externally. Fixes PR35736. ThinLTO ends up producing available_externally functions that use _CxxFrameHandler3. llvm-svn: 321532
* Revert r321377, it causes regression to https://reviews.llvm.org/P8055.Guozhi Wei2017-12-281-231/+0
| | | | llvm-svn: 321528
* Fix tests after move to utohexstr.Benjamin Kramer2017-12-286-14/+14
| | | | llvm-svn: 321527
* [X86][PREFETCH]: Adding full coverage of MC encoding for the PREFETCH isa ↵Gadi Haber2017-12-282-0/+339
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the PREFETCH isa sets for both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41161 Change-Id: Icdc8c5fb68c414de7d2cfdb50da1cc6763d9932a llvm-svn: 321524
* [RewriteStatepoints] Fix incorrect assertionMax Kazantsev2017-12-281-0/+38
| | | | | | | | | | | | | | | | | | | | `RewriteStatepointsForGC` iterates over function blocks and their predecessors in order of declaration. One of outcomes of this is that callsites are placed in arbitrary order which has nothing to do with travelsar order. On the other hand, function `recomputeLiveInValues` asserts that bases are added to `Info.PointerToBase` before their deried pointers are updated. But if call sites are processed in order different from RPOT, this is not necessarily true. We cannot guarantee that the base was placed there before every pointer derived from it. All we can guarantee is that this base was marked as known base by this point. This patch replaces the fact that we assert from checking that the base was added to the map with assert that the base was marked as known base. Differential Revision: https://reviews.llvm.org/D41593 llvm-svn: 321517
* [X86][SSE] Use PMADDWD for v4i32 multiplies with 17 or more leading zerosSimon Pilgrim2017-12-282-40/+22
| | | | | | | | | | If there are 17 or more leading zeros to the v4i32 elements, then we can use PMADD for the integer multiply when PMULLD is unavailable or slow. The 17 bits need to be zero as the PMADDWD performs a v8i16 signed-mul-extend + pairwise-add - the upper 16 so we're adding a zero pair and the 17th bit so we don't incorrectly sign extend. Differential Revision: https://reviews.llvm.org/D41484 llvm-svn: 321516
* [InstCombine] Check for isa<Instruction> before using cast<>Simon Pilgrim2017-12-281-0/+13
| | | | | | | | Protects against casts from constexpr etc. Reduced from oss-fuzz #4788 test case llvm-svn: 321515
* Revert "[memcpyopt] Teach memcpyopt to optimize across basic blocks"Reid Kleckner2017-12-284-243/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts r321138. It seems there are still underlying issues with memdep. PR35519 seems to still be present if debug info is enabled. We end up losing a memcpy. Somehow during store to memset merging, we insert the memset after the memcpy or fail to update the memdep analysis to account for the newly inserted memset of a pair. Reduced test case: #include <assert.h> #include <stdio.h> #include <string> #include <utility> #include <vector> void do_push_back( std::vector<std::pair<std::string, std::vector<std::string>>>* crls) { crls->push_back(std::make_pair(std::string(), std::vector<std::string>())); } int __attribute__((optnone)) main() { // Put some data in the vector and then remove it so we take the push_back // fast path. std::vector<std::pair<std::string, std::vector<std::string>>> crl_set; crl_set.push_back({"asdf", {}}); crl_set.pop_back(); printf("first word in vector storage: %p\n", *(void**)crl_set.data()); // Do the push_back which may fail to initialize the data. do_push_back(&crl_set); auto* first = &crl_set.back().first; printf("first word in vector storage (should be zero): %p\n", *(void**)crl_set.data()); assert(first->empty()); puts("ok"); } Compile with libc++, enable optimizations, and enable debug info: $ clang++ -stdlib=libc++ -g -O2 t.cpp -o t.exe -Wl,-rpath=llvm/build/lib This program will assert with this change. llvm-svn: 321510
* [InstCombine] add tests for min/max folds (PR35717); NFCSanjay Patel2017-12-271-0/+155
| | | | llvm-svn: 321500
* [llvm-readobj] Support -needed-libs option for COFF filesPetr Hosek2017-12-272-0/+5
| | | | | | | | This implements the -needed-libs option in the COFF dumper. Differential Revision: https://reviews.llvm.org/D41529 llvm-svn: 321498
* A special test to demonstrate debug logging for asm matcher.Andrew V. Tischenko2017-12-271-0/+52
| | | | llvm-svn: 321497
* [X86] Reimplement r321437 using custom lowering instead of as a DAG combine.Craig Topper2017-12-271-2/+2
| | | | | | | | My original implementation ran as a DAG combine post type legalization, but it turns out we don't run that DAG combine step if type legalization didn't change anything. Attempts to make the combine run before type legalization as well hit other issues. So just do it in LowerMUL where we can catch more cases. llvm-svn: 321496
* [AArch64] Change order of candidate FMLS patternsMatthew Simpson2017-12-271-4/+83
| | | | | | | | | | | | | | | | | | | | | r319980 added new patterns to the machine combiner for transforming (fsub (fmul x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source operand is an fmul are transformed. We previously only matched the case where the second source operand of an fsub was an fmul, transforming (fsub z (fmul x y)) into (fmls z x y). Now, if we have an fsub where both source operands are fmuls, both of the above patterns are applicable. However, the order in which we add the patterns to the list of candidates determines the transformation that takes place, since only the first pattern that matches will be used. This patch changes the order these two patterns are added to the list of candidates such that we prefer the case where the second source operand is an fmul (the fmls case), rather than the other one (the fmla/fneg case). When both source operands are fmuls, this ordering results in fewer instructions. Differential Revision: https://reviews.llvm.org/D41587 llvm-svn: 321491
* [X86] Fix vmul combine for AVX1 targets.Benjamin Kramer2017-12-271-0/+44
| | | | | | v8i32 is legal von AVX1, but it doesn't have pmuludq for it. llvm-svn: 321490
* [InstCombine] Gracefully handle out of range extractelement indicesSimon Pilgrim2017-12-271-0/+11
| | | | | | | | InstSimplify is responsible for handling these, but we shouldn't just assert here. Reduced from oss-fuzz #4808 test case llvm-svn: 321489
* [DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases.Simon Pilgrim2017-12-271-0/+35
| | | | | | | | For example, float operations may fail to constant fold under certain circumstances (inf/nan/denormal creation etc.) Reduced from oss-fuzz #4802 test case llvm-svn: 321488
* [Lint] Don't warn about noalias argument aliasing if other argument is byvalMikael Holmen2017-12-271-0/+48
| | | | | | | | | | | | | | | | | Summary: When using byval, the data is effectively copied as part of the call anyway, so we aren't actually passing the pointer and thus there is no reason to issue a warning. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40118 llvm-svn: 321478
* [X86][RD]: Adding full coverage of MC encoding for RD isa sets.<NFC>Gadi Haber2017-12-279-0/+98
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover RDPMC, RDRAND, RDRAND, RDSEED, RDTSCP, DWRFSGS isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenk Differential Revision: https://reviews.llvm.org/D41328 Change-Id: Ie97b397546e6b1ed180c6abd7b41fccb136d2b82 llvm-svn: 321476
* [SCEV] Do not insert if it is already in cacheSerguei Katkov2017-12-271-0/+72
| | | | | | | | | | | | | | | | | | | This is fix for the crash caused by ScalarEvolution::getTruncateExpr. It expects that if it checked the condition that SCEV is not in UniqueSCEVs cache in the beginning that it will not be there inside this method. However during recursion and transformation/simplification for sub expression, it is possible that these modifications will end up with the same SCEV as we started from. So we must always check whether SCEV is in cache and do not insert item if it is already there. Reviewers: sanjoy, mkazantsev, craig.topper Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41380 llvm-svn: 321472
* [instcombine] add powi(x, 2) -> x * xPhilip Reames2017-12-271-0/+5
| | | | llvm-svn: 321468
* [Unroll][DebugInfo] Propagate loop body's debug location to epilog preheaderZhaoshi Zheng2017-12-262-2/+132
| | | | | | | NewExit and epilog PreHeader should has the same debug loc as the original loop body, instead of original loop exit. llvm-svn: 321465
* [DAGCombine] visitANDLike - ensure APInt is is in range for ↵Simon Pilgrim2017-12-261-0/+13
| | | | | | | | getSExtValue/getZExtValue Reduced from oss-fuzz #4782 test case llvm-svn: 321464
* [X86] Regenerate test using update_llc_test_checks.py.Craig Topper2017-12-261-34/+128
| | | | llvm-svn: 321462
* [InstCombine] fix miscompile of frem with 0.0 operand (PR34870)Sanjay Patel2017-12-261-2/+3
| | | | | | | We might want to select NAN here or do this transform with fast-math, but this should at least fix the miscompile. llvm-svn: 321461
* [InstCombine] add test for frem with 0.0 (PR34870); NFCSanjay Patel2017-12-261-0/+13
| | | | llvm-svn: 321460
* It's a fix for Bug 35741 - can't use comments after x86 prefixes.Andrew V. Tischenko2017-12-261-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D41579 llvm-svn: 321459
* [ValueTracking] ignore FP signed-zero when detecting a casted-to-integer ↵Sanjay Patel2017-12-261-5/+18
| | | | | | | | | | | | | | | | | fmin/fmax pattern This is a preliminary step for the patch discussed in D41136 (and denoted here with the FIXME comment). When we match an FP min/max that is cast to integer, any intermediate difference between +0.0 or -0.0 should be muted in the result by the conversion (either fptosi or fptoui) of the result. Thus, we can enable 'nsz' for the purpose of matching fmin/fmax. Note that there's probably room to generalize this more, possibly by fixing the current calls to the weak version of isKnownNonZero() in matchSelectPattern() to the more powerful recursive version. Differential Revision: https://reviews.llvm.org/D41333 llvm-svn: 321456
* [DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge ↵Simon Pilgrim2017-12-261-0/+24
| | | | | | | | (add X, 1), 2) for i1 Reduced from oss-fuzz #4773 test case llvm-svn: 321455
* [InstSimplify] Check for in range extraction index before calling ↵Simon Pilgrim2017-12-261-0/+13
| | | | | | | | APInt::getZExtValue() Reduced from oss-fuzz #4768 test case llvm-svn: 321454
* [X86] Pass itins.rr/itins.rm through properly for some instructions.Craig Topper2017-12-261-26/+6
| | | | llvm-svn: 321452
* [X86] Use SSE_INTMUL_ITINS_P for the AVX-512 MUL instructions to match their ↵Craig Topper2017-12-261-4/+4
| | | | | | SSE/AVX counterparts. llvm-svn: 321451
* [ThinLTO] Don't import functions with noinline attributeEugene Leviant2017-12-252-0/+34
| | | | | | Differential revision: https://reviews.llvm.org/D41489 llvm-svn: 321443
* [MC] - Disallow invalid section groups declarations.George Rimar2017-12-251-0/+14
| | | | | | | | | | | | This fixes parseGroup() so that it always sets error condition on error. Previously it was not done, because parseIdentifier looks never do that, assuming that caller should do it if he wants to. So previously cases from test were silently accepted and produced broken output. Differential revision: https://reviews.llvm.org/D41559 llvm-svn: 321439
* [SafepointIRVerifier] Allow non-dereferencing uses of unrelocated or ↵Max Kazantsev2017-12-253-8/+129
| | | | | | | | | | | | | | | | | | poisoned PHI nodes PHI that has at least one unrelocated input cannot cause any issues by itself, though its uses should be carefully verified. With this patch PHIs are allowed to have any inputs but when all inputs are unrelocated the PHI is marked as unrelocated and if not all inputs are unrelocated then the PHI is marked as poisoned. Poisoned pointers can be used only in three ways: to derive new pointers, in PHIs or in comparisons against constants that are exclusively derived from null. Patch by Daniil Suchkov! Differential Revision: https://reviews.llvm.org/D41006 llvm-svn: 321438
* [X86] Add a DAG combines to turn vXi64 muls into VPMULDQ/VPMULUDQ if the ↵Craig Topper2017-12-252-56/+20
| | | | | | | | | | upper bits are all sign bits or zeros. Normally we catch this during lowering, but vXi64 mul is considered legal when we have AVX512DQ. This DAG combine allows us to avoid PMULLQ with AVX512DQ if we can prove its unnecessary. PMULLQ is 3 uops that take 4 cycles each. While pmuldq/pmuludq is only one 4 cycle uop. llvm-svn: 321437
* [X86] Add avx512vl and avx512dq command lines to combine-pmuldq.ll to ↵Craig Topper2017-12-251-31/+101
| | | | | | | | demonstrate where we fail to use pmuldq/pmuludq and use to pmullq instead. It's nice that pmullq exists, but it has higher latency and probably lower throughput than pmuldq/pmuludq. We should prefer those if we can. llvm-svn: 321436
* [X86][AVX] Add AVX1/AVX2 vmul testsSimon Pilgrim2017-12-241-939/+2056
| | | | llvm-svn: 321426
* [X86][X87] Mark pseudo memory fold instructions as load/sideeffects ↵Simon Pilgrim2017-12-241-1/+1
| | | | | | | | (PR21160, PR34080, PR34454). Match regular x87 memory fold instructions with load/sideeffects tags, to prevent the schedulers from re-ordering them across the fnstcw/fldcw sequences for truncating stores while they are still pseudo during the stack conversion pass. llvm-svn: 321424
* [X86][X87] Renamed CHECK prefix, its not actually broken anymore just ↵Simon Pilgrim2017-12-241-39/+39
| | | | | | scheduled differently llvm-svn: 321423
* [X86][X87] Add another test case mentioned on PR34080Simon Pilgrim2017-12-241-0/+136
| | | | | | Did my best to reduce this, but the X87 scheduling bug is hard to hit at the best of times... llvm-svn: 321422
* [X86] Fix (v2f64 (s/uint_to_fp (v2i1))) to avoid scalarization without AVX512DQ.Craig Topper2017-12-242-38/+26
| | | | | | Previously we extended v2i1 to v2f64 and then tried to use cvtuqq2pd/cvtqq2pd, but that only works with avx512dq. So we ended up scalarizing it. Now we widen to v4i1 first and extend to v4i32. llvm-svn: 321420
* [MC] - Teach llvm-mc to handle comdats whose names are numbers.George Rimar2017-12-241-0/+28
| | | | | | | | | | | | | | | Currently llvm-mc ignores COMDATs whose names are numbers, for example following code: .section .foo,"G",@progbits,123,comdat would produce no COMDATs at all. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D41552 llvm-svn: 321419
* [DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some ↵Craig Topper2017-12-241-2/+0
| | | | | | | | other combines a chance to run. This moves the combine for turning ANDs into shuffle with zero out of SimplifyVBinOps and places it only in visitAND below the reassociate handling. This fixes the specific case I noticed where we failed to combine two ands with constants. llvm-svn: 321417
* [X86] Teach WidenMaskArithmetic to handle any constant buildvector on the ↵Craig Topper2017-12-242-21/+112
| | | | | | RHS not just all zeros/ones. llvm-svn: 321415
* [SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext ↵Craig Topper2017-12-234-30/+22
| | | | | | of constant build vectors. llvm-svn: 321414
* [CallSiteSplitting] Remove isOrHeader restriction.Florian Hahn2017-12-232-0/+157
| | | | | | | | | | | By following the single predecessors of the predecessors of the call site, we do not need to restrict the control flow. Reviewed By: junbuml, davide Differential Revision: https://reviews.llvm.org/D40729 llvm-svn: 321413
* [X86] Remove type restrictions from WidenMaskArithmetic.Craig Topper2017-12-233-87/+34
| | | | | | This can help AVX-512 code where mask types are legal allowing us to remove extends and truncates to/from mask types. llvm-svn: 321408
* [WebAssembly] MC: Fix for address taken aliasesSam Clegg2017-12-221-28/+118
| | | | | | | | | | | | | | Previously, taking the address for an alias would result in: "Symbol not found in table index space" Increase test coverage for weak aliases. This code should be more efficient too as it avoids building the `IsAddressTaken` set. Differential Revision: https://reviews.llvm.org/D41510 llvm-svn: 321384
OpenPOWER on IntegriCloud