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* [Hexagon] Adding allocframe, post-increment circular immediate stores, ↵Colin LeMahieu2014-12-291-1/+34
| | | | | | post-increment circular register stores, and bit reversed post-increment stores. llvm-svn: 224957
* [Hexagon] Adding post-increment register form stores and register-immediate ↵Colin LeMahieu2014-12-293-2/+84
| | | | | | form stores with tests. llvm-svn: 224952
* [Hexagon] Replacing the remaining postincrement stores with versions that ↵Colin LeMahieu2014-12-291-1/+40
| | | | | | have encoding bits. llvm-svn: 224951
* Convert test to FileCheck. NFC.Rafael Espindola2014-12-291-876/+877
| | | | llvm-svn: 224950
* [Hexagon] Renaming old multiclass for removal. Adding post-increment store ↵Colin LeMahieu2014-12-291-0/+14
| | | | | | classes and instruction defs. llvm-svn: 224949
* Add segmented stack support for DragonFlyBSD.Rafael Espindola2014-12-291-0/+108
| | | | | | Patch by Michael Neumann. llvm-svn: 224936
* llvm/test/CodeGen/X86/fast-isel-call-bool.ll: Add explicit ↵NAKAMURA Takumi2014-12-281-1/+1
| | | | | | -mtriple=x86_64-unknown to satisfy x64. llvm-svn: 224907
* [X86][ISel] Fix a regression I introduced in r224884Keno Fischer2014-12-282-2/+14
| | | | | | | | | | | | | The else case ResultReg was not checked for validity. To my surprise, this case was not hit in any of the existing test cases. This includes a new test cases that tests this path. Also drop the `target triple` declaration from the original test as suggested by H.J. Lu, because apparently with it the test won't be run on Linux llvm-svn: 224901
* [X86] Add missing memory variants to AVX false dependency breakingMichael Kuperstein2014-12-282-62/+73
| | | | | | | | Adds missing memory instruction variants to AVX false dependency breaking handling. (SSE was handled in r224246) Differential Revision: http://reviews.llvm.org/D6780 llvm-svn: 224900
* [CodeGenPrepare] Teach when it is profitable to speculate calls to ↵Andrea Di Biagio2014-12-281-0/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | @llvm.cttz/ctlz. If the control flow is modelling an if-statement where the only instruction in the 'then' basic block (excluding the terminator) is a call to cttz/ctlz, CodeGenPrepare can try to speculate the cttz/ctlz call and simplify the control flow graph. Example: \code entry: %cmp = icmp eq i64 %val, 0 br i1 %cmp, label %end.bb, label %then.bb then.bb: %c = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) br label %end.bb end.bb: %cond = phi i64 [ %c, %then.bb ], [ 64, %entry] \code In this example, basic block %then.bb is taken if value %val is not zero. Also, the phi node in %end.bb would propagate the size-of in bits of %val only if %val is equal to zero. With this patch, CodeGenPrepare will try to hoist the call to cttz from %then.bb into basic block %entry only if cttz is cheap to speculate for the target. Added two new hooks in TargetLowering.h to let targets customize the behavior (i.e. decide whether it is cheap or not to speculate calls to cttz/ctlz). The two new methods are 'isCheapToSpeculateCtlz' and 'isCheapToSpeculateCttz'. By default, both methods return 'false'. On X86, method 'isCheapToSpeculateCtlz' returns true only if the target has LZCNT. Method 'isCheapToSpeculateCttz' only returns true if the target has BMI. Differential Revision: http://reviews.llvm.org/D6728 llvm-svn: 224899
* Scalarizer for masked load and store intrinsics.Elena Demikhovsky2014-12-281-0/+15
| | | | | | | | Masked vector intrinsics are a part of common LLVM IR, but they are really supported on AVX2 and AVX-512 targets. I added a code that translates masked intrinsic for all other targets. The masked vector intrinsic is converted to a chain of scalar operations inside conditional basic blocks. http://reviews.llvm.org/D6436 llvm-svn: 224897
* PowerPC: CTR shouldn't fire if a TLS call is in the loopDavid Majnemer2014-12-271-1/+24
| | | | | | | | | | | | | | | Determining the address of a TLS variable results in a function call in certain TLS models. This means that a simple ICmpInst might actually result in invalidating the CTR register. In such cases, do not attempt to rely on the CTR register for loop optimization purposes. This fixes PR22034. Differential Revision: http://reviews.llvm.org/D6786 llvm-svn: 224890
* [FastIsel][X86] Fix invalid register replacement for bool argsKeno Fischer2014-12-271-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Consider the following IR: %3 = load i8* undef %4 = trunc i8 %3 to i1 %5 = call %jl_value_t.0* @foo(..., i1 %4, ...) ret %jl_value_t.0* %5 Bools (that are the result of direct truncs) are lowered as whatever the argument to the trunc was and a "and 1", causing the part of the MBB responsible for this argument to look something like this: %vreg8<def,tied1> = AND8ri %vreg7<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg8,%vreg7 Later, when the load is lowered, it will insert %vreg15<def> = MOV8rm %vreg14, 1, %noreg, 0, %noreg; mem:LD1[undef] GR8:%vreg15 GR64:%vreg14 but remember to (at the end of isel) replace vreg7 by vreg15. Now for the bug. In fast isel lowering, we mistakenly mark vreg8 as the result of the load instead of the trunc. This adds a fixup to have vreg8 replaced by whatever the result of the load is as well, so we end up with %vreg15<def,tied1> = AND8ri %vreg15<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg15 which is an SSA violation and causes problems later down the road. This fixes PR21557. Test Plan: Test test case from PR21557 is added to the test suite. Reviewers: ributzka Reviewed By: ributzka Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6245 llvm-svn: 224884
* Convert test to llvm-readobj. NFC.Rafael Espindola2014-12-261-318/+361
| | | | llvm-svn: 224872
* [Hexagon] Adding auto-incrementing loads with and without byte reversal.Colin LeMahieu2014-12-261-0/+24
| | | | llvm-svn: 224871
* [Hexagon] Adding locked loads.Colin LeMahieu2014-12-261-0/+4
| | | | llvm-svn: 224870
* [Hexagon] Adding deallocframe and circular addressing loads.Colin LeMahieu2014-12-261-0/+39
| | | | llvm-svn: 224869
* [Hexagon] Adding remaining post-increment instruction variants. Removing ↵Colin LeMahieu2014-12-261-0/+36
| | | | | | unused classes. llvm-svn: 224868
* [Hexagon] Adding post-increment unsigned byte loads.Colin LeMahieu2014-12-261-10/+22
| | | | llvm-svn: 224867
* [Hexagon] Adding post-increment signed byte loads with tests.Colin LeMahieu2014-12-261-0/+17
| | | | llvm-svn: 224866
* Use llvm-readobj. NFC.Rafael Espindola2014-12-261-238/+162
| | | | llvm-svn: 224864
* [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble ↵Craig Topper2014-12-261-0/+2
| | | | | | references to them. llvm-svn: 224862
* [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. ↵Craig Topper2014-12-261-0/+9
| | | | | | Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
* Band-aid fix for PR22032: don't emit DWARF debug info if AddressSanitizer is ↵Timur Iskhodzhanov2014-12-261-0/+3
| | | | | | enabled on Windows llvm-svn: 224860
* No need to run llvm-as. NFC.Rafael Espindola2014-12-261-5/+4
| | | | llvm-svn: 224859
* InstCombine: Infer nuw for multipliesDavid Majnemer2014-12-262-6/+18
| | | | | | | A multiply cannot unsigned wrap if there are bitwidth, or more, leading zero bits between the two operands. llvm-svn: 224849
* InstCombe: Infer nsw for multipliesDavid Majnemer2014-12-261-0/+12
| | | | | | | We already utilize this logic for reducing overflow intrinsics, it makes sense to reuse it for normal multiplies as well. llvm-svn: 224847
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-262-10/+9
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* [PowerPC] [FastISel] i1 constants must be zero extendedHal Finkel2014-12-251-0/+27
| | | | | | | | | | | When materializing constant i1 values, they must be zero extended. We represent i1 values as [0, 1], not [0, -1], in i32 registers. As it turns out, this code path was dead for i1 values prior to r216006 (which is why this did not manifest in miscompiles until recently). Fixes -O0 self-hosting on PPC64/Linux. llvm-svn: 224842
* Masked Load/Store - Changed the order of parameters in intrinsics.Elena Demikhovsky2014-12-251-39/+49
| | | | | | | No functional changes. The documentation is coming. llvm-svn: 224829
* CodeGen: Error on redefinitions instead of assertingDavid Majnemer2014-12-242-0/+18
| | | | | | | It's possible to have a prior definition of a symbol in module asm. Raise an error instead of crashing. llvm-svn: 224828
* CodeGen: Allow aliases to be overridden by variablesDavid Majnemer2014-12-241-0/+11
| | | | llvm-svn: 224827
* MC: Label definitions are permitted after .set directivesDavid Majnemer2014-12-242-0/+25
| | | | | | | | | .set directives may be overridden by other .set directives as well as label definitions. This fixes PR22019. llvm-svn: 224811
* IAS: correct debug line info for asm macrosSaleem Abdulrasool2014-12-241-0/+20
| | | | | | | | | | | | | | | | | Correct the line information generation for preprocessed assembly. Although we tracked the source information for the macro instantiation, we failed to account for the fact that we were instantiating a macro, which is populated into a new buffer and that the line information would be relative to the definition rather than the actual instantiation location. This could cause the line number associated with the statement to be very high due to wrapping of the difference calculated for the preprocessor line information emitted into the stream. Properly calculate the line for the macro instantiation, referencing the line where the macro is actually used as GCC/gas do. The test case uses x86, though the same problem exists on any other target using the LLVM IAS. llvm-svn: 224810
* MC: Don't emit .no_dead_strip on targets which don't support itDavid Majnemer2014-12-241-1/+3
| | | | llvm-svn: 224808
* [OCaml] PR21901: Update tests.Peter Zotov2014-12-241-2/+2
| | | | | | This finishes the fix partially applied by r224782. llvm-svn: 224802
* [OCaml] Expose Llvm_executionengine.get_{global_value,function}_address.Peter Zotov2014-12-241-2/+9
| | | | | | | | | Patch by Ramkumar Ramachandra <artagnon@gmail.com>. Also remove Llvm_executionengine.get_pointer_to_global, as it is actually deprecated and didn't appear in a stable release. llvm-svn: 224801
* Debug Info: In symmetry to DW_TAG_pointer_type, do not emit the byte sizeAdrian Prantl2014-12-241-0/+44
| | | | | | | of a DW_TAG_ptr_to_member_type. This restores the behavior from before r224780-r224781. llvm-svn: 224799
* Add printing the LC_THREAD load commands with llvm-objdump’s -private-headers.Kevin Enderby2014-12-232-0/+16
| | | | llvm-svn: 224792
* [asan] change the coverage collection scheme so that we can easily emit ↵Kostya Serebryany2014-12-233-9/+9
| | | | | | coverage for the entire process as a single bit set, and if coverage_bitset=1 actually emit that bitset llvm-svn: 224789
* [PowerPC] Ensure that the TOC reload directly follows bctrl on PPC64Hal Finkel2014-12-231-1/+18
| | | | | | | | | | | | | | | | On non-Darwin PPC64, the TOC reload needs to come directly after the bctrl instruction (for indirect calls) because the 'bctrl/ld 2, 40(1)' instruction sequence is interpreted by the unwinding code in libgcc. To make sure these occur as a pair, as with other pairings interpreted by the linker, fuse the two instructions into one instruction (for code generation only). In the future, we might wish to do this by emitting CFI directives instead, but this solution is simpler, and mirrors what GCC does. Additional discussion on this point is contained in the PR. Fixes PR22015. llvm-svn: 224788
* [Hexagon] Adding doubleword load.Colin LeMahieu2014-12-231-0/+10
| | | | llvm-svn: 224787
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-232-2/+14
| | | | llvm-svn: 224786
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-234-0/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* Reverting 224775 until mayLoad flag is addressed.Colin LeMahieu2014-12-232-14/+2
| | | | llvm-svn: 224783
* Finish removing DestroySource.Rafael Espindola2014-12-231-1/+1
| | | | | | Fixes pr21901. llvm-svn: 224782
* [Hexagon] Adding word loads.Colin LeMahieu2014-12-232-2/+14
| | | | llvm-svn: 224775
* [Hexagon] Adding signed halfword loads.Colin LeMahieu2014-12-231-0/+14
| | | | llvm-svn: 224774
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-234-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* [ValueTracking] Move GlobalAlias handling to be after the max depth check in ↵Michael Kuperstein2014-12-231-0/+24
| | | | | | | | | | | | computeKnownBits() GlobalAlias handling used to be after GlobalValue handling, which meant it was, in practice, dead code. r220165 moved GlobalAlias handling to be before GlobalValue handling, but also moved it to be before the max depth check, causing an assert due to a recursion depth limit violation. This moves GlobalAlias handling forward to where it's safe, and changes the GlobalValue handling to only look at GlobalObjects. Differential Revision: http://reviews.llvm.org/D6758 llvm-svn: 224765
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