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* [AMDGPU] Fix pointer info for pseudo source for r600Yaxun Liu2017-11-104-87/+88
| | | | | | | | | | | The pointer info for pseudo source for r600 is not correct when alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz. This patch fixes that. Differential Revision: https://reviews.llvm.org/D39670 llvm-svn: 317861
* [ThinLTO] Fix missing call graph edges for calls with bitcasts.Volodymyr Sapsai2017-11-101-0/+31
| | | | | | | | | | | | | | | | | | This change doesn't fix the root cause of the miscompile PR34966 as the root cause is in the linker ld64. This change makes call graph more complete allowing to have better module imports/exports. rdar://problem/35344706 Reviewers: tejohnson Reviewed By: tejohnson Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39356 llvm-svn: 317853
* [SimplifyCFG] Fix a test case.Easwaran Raman2017-11-091-1/+2
| | | | | | | This was first committed in r317845, but had the order of branch weights wrong and didn't properly check the output. llvm-svn: 317848
* Add a wrapper function to set branch weights metadata.Easwaran Raman2017-11-091-0/+39
| | | | | | | | | | | | | | Summary: This wrapper checks if there is at least one non-zero weight before setting the metadata. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39872 llvm-svn: 317845
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-092-22/+26
| | | | llvm-svn: 317841
* Fix out-of-order stepping behavior in programs with hoisted constants.Paul Robinson2017-11-092-0/+96
| | | | | | | | | | | | | | | | | | When the Constant Hoisting pass moves expensive constants into a common block, it would assign a debug location equal to the last use of that constant. While this is certainly intuitive, it places the constant in an out-of-order location, according to the debug location information. This produces out-of-order stepping when debugging programs affected by this pass. This patch creates in-order stepping behavior by merging the debug locations for hoisted constants, and the new insertion point. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D38088 llvm-svn: 317827
* Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).Adrian Prantl2017-11-091-0/+64
| | | | | | rdar://problem/27139077 llvm-svn: 317825
* [SLP] Fix PR23510: Try to find best possible vectorizable stores.Alexey Bataev2017-11-091-15/+10
| | | | | | | | | | | | | | | | | | Summary: The analysis of the store sequence goes in straight order - from the first store to the last. Bu the best opportunity for vectorization will happen if we're going to use reverse order - from last store to the first. It may be best because usually users have some initialization part + further processing and this first initialization may confuse SLP vectorizer. Reviewers: RKSimon, hfinkel, mkuper, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39606 llvm-svn: 317821
* [Reassociate] auto-generate test checks; NFCSanjay Patel2017-11-094-47/+60
| | | | llvm-svn: 317819
* [Reassociate] don't name values "tmp"; NFCISanjay Patel2017-11-098-253/+279
| | | | | | | | | | The toxic stew of created values named 'tmp' and tests that already have values named 'tmp' and CHECK lines looking for values named 'tmp' causes bad things to happen in our test line auto-generation scripts because it wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to avoid that. llvm-svn: 317818
* revert r317809 - [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-14/+4
| | | | | | | The reassociate pass generates named values such as "%tmp2" which trips up the script's regex's because the script uses a 'TMP' prefix for unnamed values (%2). llvm-svn: 317810
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-4/+14
| | | | llvm-svn: 317809
* [SystemZ] Add support for the "o" inline asm constraintUlrich Weigand2017-11-091-0/+10
| | | | | | | | | We don't really need any special handling of "offsettable" memory addresses, but since some existing code uses inline asm statements with the "o" constraint, add support for this constraint for compatibility purposes. llvm-svn: 317807
* [Reassociate] regenerate test checks; NFCSanjay Patel2017-11-091-66/+73
| | | | llvm-svn: 317806
* [Reassociate] add check lines; NFCSanjay Patel2017-11-091-1/+11
| | | | llvm-svn: 317805
* [Reassociate] add tests with 'reassoc' FMF and regenerate checks; NFCSanjay Patel2017-11-091-84/+254
| | | | llvm-svn: 317804
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-092-9/+34
| | | | | | | | | | | | | | Correct the definition of 'j' as being unavailable for microMIPS32R6 and provide the 'b' assembly idiom for codegen purposes for microMIPS32r3. Provide the necessary 'br' pattern for microMIPS32R6 as it now longer incorrectly uses the 'j' instruction. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39741 llvm-svn: 317801
* [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.pyAlex Bradbury2017-11-091-38/+58
| | | | | | | No real change, but makes it marginally easier to merge the remainder of the out-of-tree patches. llvm-svn: 317796
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-093-0/+162
| | | | llvm-svn: 317791
* Reapply: Allow yaml2obj to order implicit sections for ELFDave Lee2017-11-092-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change allows yaml input to control the order of implicitly added sections (`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a placeholder section of the given name to the Sections field. This change is to support changes in D39582, where it is desirable to control the location of the `.dynsym` section. This reapplied version fixes: 1. use of a function call within an assert 2. failing lld test which has an unnamed section 3. incorrect section count when given an unnamed section Additionally, one more test to cover the unnamed section failure. Reviewers: compnerd, jakehehrlich Reviewed By: jakehehrlich Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39749 llvm-svn: 317789
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-092-0/+36
| | | | llvm-svn: 317788
* Sched model improving on btver2: JFPU01 resource, vtestp* for xmm.Andrew V. Tischenko2017-11-092-16/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D39802 llvm-svn: 317785
* Add -print-schedule scheduling comments to inline asm.Andrew V. Tischenko2017-11-092-156/+156
| | | | | | Differential Revision: https://reviews.llvm.org/D39728 llvm-svn: 317782
* [X86] Make X86ISD::FMADDS3 isel patterns commutable.Craig Topper2017-11-091-0/+95
| | | | | | This was missed when FMADDS3 was split from X86ISD::FMADDS3_RND. llvm-svn: 317769
* [GVN PRE] Patch the source for Phi node in PRESerguei Katkov2017-11-092-0/+88
| | | | | | | | | | | | | | | | | | | We must patch all existing incoming values of Phi node, otherwise it is possible that we can see poison where program does not expect to see it. This is the similar what GVN does. The added test test/Transforms/GVN/PRE/pre-jt-add.ll shows an example of wrong optimization done by jump threading due to GVN PRE did not patch existing incoming value. Reviewers: mkazantsev, wmi, dberlin, davide Reviewed By: dberlin Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D39637 llvm-svn: 317768
* [llvm-cov] Fix more -path-equivalence test bugsVedant Kumar2017-11-093-1/+1
| | | | llvm-svn: 317764
* [llvm-cov] Fix a -path-equivalence bug in a testVedant Kumar2017-11-091-2/+2
| | | | llvm-svn: 317763
* [llvm-cov] Don't render empty region marker linesVedant Kumar2017-11-091-1/+1
| | | | | | | This fixes an issue where llvm-cov prints an empty line, thinking it needs to display region markers, when it actually doesn't. llvm-svn: 317762
* [Coverage] Use the wrapped segment when a line has entry segmentsVedant Kumar2017-11-0917-92/+57
| | | | | | | | | We've worked around bugs in the frontend by ignoring the count from wrapped segments when a line has at least one region entry segment. Those frontend bugs are now fixed, so it's time to regenerate the checked-in covmapping files and remove the workaround. llvm-svn: 317761
* AMDGPU: Merge BUFFER_STORE_DWORD_OFFEN/OFFSET into x2, x4Marek Olsak2017-11-092-6/+77
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only 56 shaders (out of 48486) are affected. Totals from affected shaders (changed stats only): SGPRS: 2420 -> 2460 (1.65 %) Spilled VGPRs: 94 -> 112 (19.15 %) Scratch size: 524 -> 528 (0.76 %) dwords per thread Code Size: 187400 -> 184992 (-1.28 %) bytes One DiRT Showdown shader spills 6 more VGPRs. One Grid Autosport shader spills 12 more VGPRs. The other 54 shaders only have a decrease in code size. (I'm ignoring the SGPR noise) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39012 llvm-svn: 317755
* AMDGPU: Lower buffer store and atomic intrinsics manuallyMarek Olsak2017-11-096-0/+44
| | | | | | | | | | | | | | Summary: Without this, SIMemoryLegalizer inserts s_waitcnt vmcnt(0) before every buffer store and atomic instruction. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D39060 llvm-svn: 317754
* AMDGPU: Merge BUFFER_LOAD_DWORD_OFFSET into x2, x4Marek Olsak2017-11-092-6/+36
| | | | | | | | | | | | Summary: Only 3 (out of 48486) shaders are affected. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D38951 llvm-svn: 317753
* AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4Marek Olsak2017-11-092-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: -9.9% code size decrease in affected shaders. Totals (changed stats only): SGPRS: 2151462 -> 2170646 (0.89 %) VGPRS: 1634612 -> 1640288 (0.35 %) Spilled SGPRs: 8942 -> 8940 (-0.02 %) Code Size: 52940672 -> 51727288 (-2.29 %) bytes Max Waves: 373066 -> 371718 (-0.36 %) Totals from affected shaders: SGPRS: 283520 -> 302704 (6.77 %) VGPRS: 227632 -> 233308 (2.49 %) Spilled SGPRs: 3966 -> 3964 (-0.05 %) Code Size: 12203080 -> 10989696 (-9.94 %) bytes Max Waves: 44070 -> 42722 (-3.06 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38950 llvm-svn: 317752
* AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4Marek Olsak2017-11-091-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only constant offsets (*_IMM opcodes) are merged. It reuses code for LDS load/store merging. It relies on the scheduler to group loads. The results are mixed, I think they are mostly positive. Most shaders are affected, so here are total stats only: SGPRS: 2072198 -> 2151462 (3.83 %) VGPRS: 1628024 -> 1634612 (0.40 %) Spilled SGPRs: 7883 -> 8942 (13.43 %) Spilled VGPRs: 97 -> 101 (4.12 %) Scratch size: 1488 -> 1492 (0.27 %) dwords per thread Code Size: 60222620 -> 52940672 (-12.09 %) bytes Max Waves: 374337 -> 373066 (-0.34 %) There is 13.4% increase in SGPR spilling, DiRT Showdown spills a few more VGPRs (now 37), but 12% decrease in code size. These are the new stats for SGPR spilling. We already spill a lot SGPRs, so it's uncertain whether more spilling will make any difference since SGPRs are always spilled to VGPRs: SGPR SPILLING APPS Shaders SpillSGPR AvgPerSh alien_isolation 2938 100 0.0 batman_arkham_origins 589 6 0.0 bioshock-infinite 1769 4 0.0 borderlands2 3968 22 0.0 counter_strike_glob.. 1142 60 0.1 deus_ex_mankind_div.. 1410 79 0.1 dirt-showdown 533 4 0.0 dirt_rally 364 1163 3.2 divinity 1052 2 0.0 dota2 1747 7 0.0 f1-2015 776 1515 2.0 grid_autosport 1767 1505 0.9 hitman 1413 273 0.2 left_4_dead_2 1762 4 0.0 life_is_strange 1296 26 0.0 mad_max 358 96 0.3 metro_2033_redux 2670 60 0.0 payday2 1362 22 0.0 portal 474 3 0.0 saints_row_iv 1704 8 0.0 serious_sam_3_bfe 392 1348 3.4 shadow_of_mordor 1418 12 0.0 shadow_warrior 3956 239 0.1 talos_principle 324 1735 5.4 thea 172 17 0.1 tomb_raider 1449 215 0.1 total_war_warhammer 242 56 0.2 ue4_effects_cave 295 55 0.2 ue4_elemental 572 12 0.0 unigine_tropics 210 56 0.3 unigine_valley 278 152 0.5 victor_vran 1262 84 0.1 yofrankie 82 2 0.0 Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38949 llvm-svn: 317751
* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-091-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: -5.3% code size in affected shaders. Changed stats only: 48486 shaders in 30489 tests Totals: SGPRS: 2086406 -> 2072430 (-0.67 %) VGPRS: 1626872 -> 1627960 (0.07 %) Spilled SGPRs: 7865 -> 7912 (0.60 %) Code Size: 60978060 -> 60188764 (-1.29 %) bytes Max Waves: 374530 -> 374342 (-0.05 %) Totals from affected shaders: SGPRS: 299664 -> 285688 (-4.66 %) VGPRS: 233844 -> 234932 (0.47 %) Spilled SGPRs: 3959 -> 4006 (1.19 %) Code Size: 14905272 -> 14115976 (-5.30 %) bytes Max Waves: 46202 -> 46014 (-0.41 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38915 llvm-svn: 317750
* [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3 ↵Craig Topper2017-11-091-0/+22
| | | | | | | | nodes when doing FNEG combine. r317453 added new ISD nodes without rounding modes that were added to an existing if/else chain. But all the previous nodes handled there included a rounding mode. The final code after this if/else chain expected an extra operand that isn't present for the new nodes. llvm-svn: 317748
* [cfi-verify] Adds blacklist blame behaviour to cfi-verify.Mitch Phillips2017-11-093-3/+3
| | | | | | | | | | | | | | Adds the blacklist behaviour to llvm-cfi-verify. Now will calculate which lines caused expected failures in the blacklist and reports the number of affected indirect CF instructions for each blacklist entry. Also moved DWARF checking after instruction analysis to improve performance significantly - unrolling the inlining stack is expensive. Reviewers: vlad.tsyrklevich Subscribers: aprantl, pcc, kcc, llvm-commits Differential Revision: https://reviews.llvm.org/D39750 llvm-svn: 317743
* [X86] Preserve memory refs when folding loads into divides.Craig Topper2017-11-081-1/+29
| | | | | | This is similar to what we already do for multiplies. Without this we can't unfold and hoist an invariant load. llvm-svn: 317732
* Let replaceVTableHolder accept any type.Adrian Prantl2017-11-082-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | | In Rust, a trait can be implemented for any type, and if a trait object pointer is used for the type, then a virtual table will be emitted for that trait/type combination. We would like debuggers to be able to inspect trait objects, which requires finding the concrete type associated with a given vtable. This patch changes LLVM so that any type can be passed to replaceVTableHolder. This allows the Rust compiler to emit the needed debug info -- associating a vtable with the concrete type for which it was emitted. This is a DWARF extension: DWARF only specifies the meaning of DW_AT_containing_type in one specific situation. This style of DWARF extension is routine, though, and LLVM already has one such case for DW_AT_containing_type. Patch by Tom Tromey! Differential Revision: https://reviews.llvm.org/D39503 llvm-svn: 317730
* Add an @llvm.sideeffect intrinsicDan Gohman2017-11-0816-0/+377
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements Chandler's idea [0] for supporting languages that require support for infinite loops with side effects, such as Rust, providing part of a solution to bug 965 [1]. Specifically, it adds an `llvm.sideeffect()` intrinsic, which has no actual effect, but which appears to optimization passes to have obscure side effects, such that they don't optimize away loops containing it. It also teaches several optimization passes to ignore this intrinsic, so that it doesn't significantly impact optimization in most cases. As discussed on llvm-dev [2], this patch is the first of two major parts. The second part, to change LLVM's semantics to have defined behavior on infinite loops by default, with a function attribute for opting into potential-undefined-behavior, will be implemented and posted for review in a separate patch. [0] http://lists.llvm.org/pipermail/llvm-dev/2015-July/088103.html [1] https://bugs.llvm.org/show_bug.cgi?id=965 [2] http://lists.llvm.org/pipermail/llvm-dev/2017-October/118632.html Differential Revision: https://reviews.llvm.org/D38336 llvm-svn: 317729
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-0887-1215/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts r317579, originally committed as r317100. There is a design issue with marking CFI instructions duplicatable. Not all targets support the CFIInstrInserter pass, and targets like Darwin can't cope with duplicated prologue setup CFI instructions. The compact unwind info emission fails. When the following code is compiled for arm64 on Mac at -O3, the CFI instructions end up getting tail duplicated, which causes compact unwind info emission to fail: int a, c, d, e, f, g, h, i, j, k, l, m; void n(int o, int *b) { if (g) f = 0; for (; f < o; f++) { m = a; if (l > j * k > i) j = i = k = d; h = b[c] - e; } } We get assembly that looks like this: ; BB#1: ; %if.then Lloh3: adrp x9, _f@GOTPAGE Lloh4: ldr x9, [x9, _f@GOTPAGEOFF] mov w8, wzr Lloh5: str wzr, [x9] stp x20, x19, [sp, #-16]! ; 8-byte Folded Spill .cfi_def_cfa_offset 16 .cfi_offset w19, -8 .cfi_offset w20, -16 cmp w8, w0 b.lt LBB0_3 b LBB0_7 LBB0_2: ; %entry.if.end_crit_edge Lloh6: adrp x8, _f@GOTPAGE Lloh7: ldr x8, [x8, _f@GOTPAGEOFF] Lloh8: ldr w8, [x8] stp x20, x19, [sp, #-16]! ; 8-byte Folded Spill .cfi_def_cfa_offset 16 .cfi_offset w19, -8 .cfi_offset w20, -16 cmp w8, w0 b.ge LBB0_7 LBB0_3: ; %for.body.lr.ph Note the multiple .cfi_def* directives. Compact unwind info emission can't handle that. llvm-svn: 317726
* Make sure an error is always handled.Rafael Espindola2017-11-081-0/+11
| | | | llvm-svn: 317724
* [WebAssembly] Add a test for inline-asm "m" constraints.Dan Gohman2017-11-081-0/+13
| | | | llvm-svn: 317711
* [WebAssembly] Call signExtend to get sign extended registerDan Gohman2017-11-081-0/+22
| | | | | | | | Patch by Jatin Bhateja! Differential Revision: https://reviews.llvm.org/D39529 llvm-svn: 317710
* Un-XFAIL a test after the bugfix in r317702.Adrian Prantl2017-11-081-5/+0
| | | | llvm-svn: 317708
* [WebAssembly] Revise the strategy for inline asm.Dan Gohman2017-11-081-23/+33
| | | | | | | | | | | | | | | | | | | | | | Previously, an "r" constraint would mean the compiler provides a value on WebAssembly's operand stack. This was tricky to use properly, particularly since it isn't possible to declare a new local from within an inline asm string. With this patch, "r" provides the value in a WebAssembly local, and the local index is provided to the inline asm string. This requires inline asm to use get_local and set_local to read the register. This does potentially result in larger code size, however inline asm should hopefully be quite rare in WebAssembly. This also means that the "m" constraint can no longer be supported, as WebAssembly has nothing like a "memory operand" that includes an implicit get_local. This fixes PR34599 for the wasm32-unknown-unknown-wasm target (though not for the ELF target). llvm-svn: 317707
* Handle inlined variables in SelectionDAGBuilder::EmitFuncArgumentDbgValue().Adrian Prantl2017-11-082-2/+143
| | | | | | | | | | | | | | | | | In 2010 a commit with no testcase and no further explanation explicitly disabled the handling of inlined variables in EmitFuncArgumentDbgValue(). I don't think there is a good reason for this any more and re-enabling this adds debug locations for variables associated with an LLVM function argument in functions that are inlined into the first basic block. The only downside of doing this is that we may insert a DBG_VALUE before the inlined scope, but (1) this could be filtered out later, and (2) LiveDebugValues will not propagate it into subsequent basic blocks if they don't dominate the variable's lexical scope, so this seems like a small price to pay. rdar://problem/26228128 llvm-svn: 317702
* [X86] Add some initial scheduling tests for generic x86 instructionsSimon Pilgrim2017-11-082-0/+1085
| | | | | | | | These will be using inline asm to ensure we have coverage that we're unlikely to get from lowering of basic ir. Currently waiting for D39728 to land to add support for scheduler comments for inline asm. llvm-svn: 317698
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+83
| | | | | | | | | Note that this is just enough for simple function call examples to generate working code. Support for varargs etc follows in future patches. Differential Revision: https://reviews.llvm.org/D29936 llvm-svn: 317691
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+121
| | | | | | | | | | | | | | | | | | | | A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690
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