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* Add 3DNow! intrinsics.Michael J. Spencer2011-04-151-0/+297
| | | | llvm-svn: 129551
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-152-0/+16
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-0/+56
| | | | llvm-svn: 129548
* Add an instcombine for constructs like a | -(b != c); a select is moreEli Friedman2011-04-141-0/+19
| | | | | | | canonical, and generally leads to better code. Found while looking at an article about saturating arithmetic. llvm-svn: 129545
* Fix an infinite alternation in JumpThreading where two transforms would ↵Owen Anderson2011-04-141-0/+31
| | | | | | | | | | repeatedly undo each other. The solution is to perform more aggressive constant folding to make one of the edges just folded away rather than trying to thread it. Fixes <rdar://problem/9284786>. Discovered with CSmith. llvm-svn: 129538
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-144-0/+33
| | | | | | operations. llvm-svn: 129531
* tests: Remove a FrontendC test which is no longer valid.Daniel Dunbar2011-04-141-11/+0
| | | | llvm-svn: 129519
* Change ELF systems to use CFI for producing the EH tables. This reduces theRafael Espindola2011-04-143-15/+4
| | | | | | size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129518
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-145-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-1428-108/+99
| | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-1431-152/+161
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Vectors with different number of elements of the same element type can haveMon P Wang2011-04-131-0/+46
| | | | | | | | the same allocation size but different primitive sizes(e.g., <3xi32> and <4xi32>). When ScalarRepl promotes them, it can't use a bit cast but should use a shuffle vector instead. llvm-svn: 129472
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-132-2/+13
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-0/+18
| | | | llvm-svn: 129468
* Fix a regression caused by r102515 where explicit alignment on globals isCameron Zwarich2011-04-132-5/+5
| | | | | | | ignored. There was a test to catch this, but it was just blindly updated in a large change. This fixes another part of <rdar://problem/9275290>. llvm-svn: 129466
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-132-0/+20
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Fix an obvious problem with an alignment computation. AsmPrinter actually doesCameron Zwarich2011-04-131-0/+2
| | | | | | | the max itself, so it is not easy to write a test case for this, but I added a test case that would fail if the code in AsmPrinter were removed. llvm-svn: 129432
* If a global variable has a specified alignment that is less than the preferredCameron Zwarich2011-04-131-0/+9
| | | | | | | alignment for its type, use the minimum of the specified alignment and the ABI alignment. This fixes <rdar://problem/9275290>. llvm-svn: 129428
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-136-27/+25
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Reapply r129401 with patch for clang.Bill Wendling2011-04-132-2/+14
| | | | llvm-svn: 129419
* Temporarily revert r129408 to see if it brings the bots back.Eric Christopher2011-04-131-15/+0
| | | | llvm-svn: 129417
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-121-0/+15
| | | | | | | | registers for fast allocation. Fixes rdar://9207598 llvm-svn: 129408
* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-122-14/+2
| | | | llvm-svn: 129403
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-122-2/+14
| | | | | | | | | Now that we have a first-class way to represent unaligned loads, the unaligned load intrinsics are superfluous. First part of <rdar://problem/8460511>. llvm-svn: 129401
* Fix compiler command line used by lit.py when working with NMakeOscar Fuentes2011-04-121-2/+20
| | | | | | | | generators. It may improve robustness when testing from VS too. Based on a patch by David Neto! llvm-svn: 129398
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+10
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-122-4/+6
| | | | llvm-svn: 129385
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-122-6/+4
| | | | | | | | | | | | UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129383
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-1/+13
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-121-0/+10
| | | | | | Ld/St Multiple. llvm-svn: 129365
* Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.Rafael Espindola2011-04-121-0/+41
| | | | llvm-svn: 129362
* Implement .cfi_same_value.Rafael Espindola2011-04-121-0/+42
| | | | llvm-svn: 129361
* Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich2011-04-121-1/+1
| | | | | | | stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. llvm-svn: 129345
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
| | | | llvm-svn: 129327
* Match case for invalid constant error messages and add a newEric Christopher2011-04-121-1/+4
| | | | | | test for invalid hexadecimals. llvm-svn: 129326
* A8.6.16 BJohnny Chen2011-04-121-0/+10
| | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325
* Fix reassociate to use a worklist instead of recursing when newDan Gohman2011-04-121-0/+24
| | | | | | | | | reassociation opportunities are exposed. This fixes a bug where the nested reassociation expects to be the IR to be consistent, but it isn't, because the outer reassociation has disconnected some of the operands. rdar://9167457 llvm-svn: 129324
* Test for invalid constant expr addition - bad octal constant.Eric Christopher2011-04-121-13/+5
| | | | llvm-svn: 129323
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* remove the StructRetPromotion pass. It is unused, not maintained andChris Lattner2011-04-115-87/+0
| | | | | | | has some bugs. If this is interesting functionality, it should be reimplemented in the argpromotion pass. llvm-svn: 129314
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-112-15/+9
| | | | llvm-svn: 129311
* Implement cfi_rel_offsetRafael Espindola2011-04-111-0/+49
| | | | llvm-svn: 129306
* Add test for previous commit.Rafael Espindola2011-04-111-0/+46
| | | | llvm-svn: 129304
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-0/+6
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng2011-04-111-0/+34
| | | | | | more copies. rdar://9266679 llvm-svn: 129297
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