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* [RewriteStatepointsForGC] Fix a relocation bug w.r.t values defined by ↵Philip Reames2015-03-041-0/+33
| | | | | | | | | | | | | | | invoke instructions RewriteStatepointsForGC pass emits an alloca for each GC pointer which will be relocated. It then inserts stores after def and all relocations, and inserts loads before each use as well. In the end, mem2reg is used to update IR with relocations in SSA form. However, there is a problem with inserting stores for values defined by invoke instructions. The code didn't expect a def was a terminator instruction, and inserting instructions after these terminators resulted in malformed IR. This patch fixes this problem by handling invoke instructions as a special case. If the def is an invoke instruction, the store will be inserted at the beginning of the normal destination block. Since return value from invoke instruction does not dominate the unwind destination block, no action is needed there. Patch by: Chen Li Differential Revision: http://reviews.llvm.org/D7923 llvm-svn: 231183
* Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.Juergen Ributzka2015-03-042-7/+18
| | | | | | | | | | | The intrinsic is no longer generated by the front-end. Remove the intrinsic and auto-upgrade it to a vector shuffle. Reviewed by Nadav This is related to rdar://problem/18742778. llvm-svn: 231182
* Update twoaddr-coalesce-3.ll to run on darwin and linux machines:Eric Christopher2015-03-031-4/+5
| | | | | | | a) Default relocation model differences, b) Different numbers of # in comments llvm-svn: 231178
* [sanitizer/coverage] Add AFL-style coverage counters (search heuristic for ↵Kostya Serebryany2015-03-031-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | fuzzing). Introduce -mllvm -sanitizer-coverage-8bit-counters=1 which adds imprecise thread-unfriendly 8-bit coverage counters. The run-time library maps these 8-bit counters to 8-bit bitsets in the same way AFL (http://lcamtuf.coredump.cx/afl/technical_details.txt) does: counter values are divided into 8 ranges and based on the counter value one of the bits in the bitset is set. The AFL ranges are used here: 1, 2, 3, 4-7, 8-15, 16-31, 32-127, 128+. These counters provide a search heuristic for single-threaded coverage-guided fuzzers, we do not expect them to be useful for other purposes. Depending on the value of -fsanitize-coverage=[123] flag, these counters will be added to the function entry blocks (=1), every basic block (=2), or every edge (=3). Use these counters as an optional search heuristic in the Fuzzer library. Add a test where this heuristic is critical. llvm-svn: 231166
* WinEH: Remove vestigial EH objectReid Kleckner2015-03-035-10/+0
| | | | | | | | Ultimately, we'll need to leave something behind to indicate which alloca will hold the exception, but we can figure that out when it comes time to emit the __CxxFrameHandler3 catch handler table. llvm-svn: 231164
* InstCombine: Ensure select condition types are identical before mergingDavid Majnemer2015-03-031-0/+10
| | | | | | | | | | Selection conditions may be vectors or scalars. Make sure InstCombine doesn't indiscriminately assume that a select which is value dependent on another select have identical select condition types. This fixes PR22773. llvm-svn: 231156
* Moving WinEH outlining tests to an architecture neutral locationAndrew Kaylor2015-03-037-0/+12
| | | | llvm-svn: 231155
* Fix a problem where the TwoAddressInstructionPass which generate redundant ↵Eric Christopher2015-03-031-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register moves in a loop. From: int M, total; void foo() { int i; for (i = 0; i < M; i++) { total = total + i / 2; } } This is the kernel loop: .LBB0_2: # %for.body =>This Inner Loop Header: Depth=1 movl %edx, %esi movl %ecx, %edx shrl $31, %edx addl %ecx, %edx sarl %edx addl %esi, %edx incl %ecx cmpl %eax, %ecx jl .LBB0_2 -------------------------- The first mov insn "movl %edx, %esi" could be removed if we change "addl %esi, %edx" to "addl %edx, %esi". The IR before TwoAddressInstructionPass is: BB#2: derived from LLVM BB %for.body Predecessors according to CFG: BB#1 BB#2 %vreg3<def> = COPY %vreg12<kill>; GR32:%vreg3,%vreg12 %vreg2<def> = COPY %vreg11<kill>; GR32:%vreg2,%vreg11 %vreg7<def,tied1> = SHR32ri %vreg3<tied0>, 31, %EFLAGS<imp-def,dead>; GR32:%vreg7,%vreg3 %vreg8<def,tied1> = ADD32rr %vreg3<tied0>, %vreg7<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg8,%vreg3,%vreg7 %vreg9<def,tied1> = SAR32r1 %vreg8<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg9,%vreg8 %vreg4<def,tied1> = ADD32rr %vreg9<kill,tied0>, %vreg2<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg4,%vreg9,%vreg2 %vreg5<def,tied1> = INC64_32r %vreg3<kill,tied0>, %EFLAGS<imp-def,dead>; GR32:%vreg5,%vreg3 CMP32rr %vreg5, %vreg0, %EFLAGS<imp-def>; GR32:%vreg5,%vreg0 %vreg11<def> = COPY %vreg4; GR32:%vreg11,%vreg4 %vreg12<def> = COPY %vreg5<kill>; GR32:%vreg12,%vreg5 JL_4 <BB#2>, %EFLAGS<imp-use,kill> Now TwoAddressInstructionPass will choose vreg9 to be tied with vreg4. However, it doesn't see that there is copy from vreg4 to vreg11 and another copy from vreg11 to vreg2 inside the loop body. To remove those copies, it is necessary to choose vreg2 to be tied with vreg4 instead of vreg9. This code pattern commonly appears when there is reduction operation in a loop. So check for a reversed copy chain and if we encounter one then we can commute the add instruction so we can avoid a copy. Patch by Wei Mi. http://reviews.llvm.org/D7806 llvm-svn: 231148
* Teach ComputeNumSignBits about signed divisions.Nadav Rotem2015-03-031-0/+23
| | | | | | | http://reviews.llvm.org/D8028 rdar://20023136 llvm-svn: 231140
* Correctly handle -pass-remarks in the gold plugin.Rafael Espindola2015-03-031-0/+17
| | | | llvm-svn: 231132
* [X86][ELF] Correct relocation for DWARF TLS referencesPaul Robinson2015-03-031-0/+6
| | | | | | | | | Previously we had only Linux using DTPOFF for these; all X86 ELF targets should. Fixes a side issue mentioned in PR21077. Differential Revision: http://reviews.llvm.org/D8011 llvm-svn: 231130
* Fix PR22762. When emitting a DWARF expression check whether this is theAdrian Prantl2015-03-031-0/+60
| | | | | | | | frame register before checking if there is a DWARF register number for it. Thanks to H.J. Lu for diagnosing this and providing the testcase! llvm-svn: 231121
* Outline cleanup handlers for native Windows C++ exception handlingAndrew Kaylor2015-03-036-14/+106
| | | | | | Differential Revision: http://reviews.llvm.org/D7865 llvm-svn: 231117
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-037-6/+556
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* Make llvm.eh.begincatch use an outparamReid Kleckner2015-03-037-83/+70
| | | | | | | | | | | | | | Ultimately, __CxxFrameHandler3 needs us to put a stack offset in a table, and it will take responsibility for copying the exception object into that slot. Modelling the exception object as an SSA value returned by begincatch isn't going to work in general, so make it use an output parameter. Reviewers: andrew.w.kaylor Differential Revision: http://reviews.llvm.org/D7920 llvm-svn: 231086
* [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).Chad Rosier2015-03-031-2/+1
| | | | | | This change only effects codegen when the constant is -3. llvm-svn: 231085
* DebugInfo: Move new hierarchy into placeDuncan P. N. Exon Smith2015-03-03373-6722/+6733
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the specialized metadata nodes for the new debug info hierarchy into place, finishing off PR22464. I've done bootstraps (and all that) and I'm confident this commit is NFC as far as DWARF output is concerned. Let me know if I'm wrong :). The code changes are fairly mechanical: - Bumped the "Debug Info Version". - `DIBuilder` now creates the appropriate subclass of `MDNode`. - Subclasses of DIDescriptor now expect to hold their "MD" counterparts (e.g., `DIBasicType` expects `MDBasicType`). - Deleted a ton of dead code in `AsmWriter.cpp` and `DebugInfo.cpp` for printing comments. - Big update to LangRef to describe the nodes in the new hierarchy. Feel free to make it better. Testcase changes are enormous. There's an accompanying clang commit on its way. If you have out-of-tree debug info testcases, I just broke your build. - `upgrade-specialized-nodes.sh` is attached to PR22564. I used it to update all the IR testcases. - Unfortunately I failed to find way to script the updates to CHECK lines, so I updated all of these by hand. This was fairly painful, since the old CHECKs are difficult to reason about. That's one of the benefits of the new hierarchy. This work isn't quite finished, BTW. The `DIDescriptor` subclasses are almost empty wrappers, but not quite: they still have loose casting checks (see the `RETURN_FROM_RAW()` macro). Once they're completely gutted, I'll rename the "MD" classes to "DI" and kill the wrappers. I also expect to make a few schema changes now that it's easier to reason about everything. llvm-svn: 231082
* Make llvm/test/Object/archive-format.test CRLF-tolerant.NAKAMURA Takumi2015-03-031-5/+4
| | | | llvm-svn: 231074
* During PHI elimination, split critical edges that move copies out of loops.Daniel Jasper2015-03-031-1/+38
| | | | | | | | | | | | | | | | | | | | This prevents the behavior observed in llvm.org/PR22369. I am not sure whether I am reading the code correctly, but the early exit based on isLiveOutPastPHIs() seems to make the wrong assumption that RegisterCoalescer won't be able to coalesce those copies later. This change hides the new behavior behind -no-phi-elim-live-out-early-exit as it currently breaks four tests: * Assertion in: CodeGen/Hexagon/hwloop-cleanup.ll * Worse code in: CodeGen/X86/coalescer-commute4.ll CodeGen/X86/phys_subreg_coalesce-2.ll CodeGen/X86/zlib-longest-match.ll The root cause here seems to be that the heuristic that determines the visitation order in RegisterCoalescer gets less lucky. llvm-svn: 231064
* Cleanup after r230934 per Dave's suggestions.Owen Anderson2015-03-031-2/+1
| | | | llvm-svn: 231056
* [X86] Special-case 2x CMOV when custom-inserting.Ahmed Bougacha2015-03-031-109/+71
| | | | | | | | | | | | | | | | | | This lets us avoid a few copies that are otherwise hard to get rid of. The way this is done is, the custom-inserter looks at the following instruction for another CMOV, and replaces both at the same time. A previous version used a new CMOV2 opcode, but the custom inserter is expected to be able to return a different basic block anyway, which means it's OK - though far from ideal - to alter that block's contents. Explicitly document that, in case it ever makes a difference. Alternatives welcome! Follow-up to r231045. rdar://19767934 Closes http://reviews.llvm.org/D8019 llvm-svn: 231046
* [X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).Ahmed Bougacha2015-03-032-10/+280
| | | | | | | | | | | | | | | | | | | Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
* Fix cppeh breakage due to racing commitsReid Kleckner2015-03-032-66/+66
| | | | llvm-svn: 231044
* LowerBitSets: Use byte arrays instead of bit sets to represent in-memory bit ↵Peter Collingbourne2015-03-031-19/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sets. By loading from indexed offsets into a byte array and applying a mask, a program can test bits from the bit set with a relatively short instruction sequence. For example, suppose we have 15 bit sets to lay out: A (16 bits), B (15 bits), C (14 bits), D (13 bits), E (12 bits), F (11 bits), G (10 bits), H (9 bits), I (7 bits), J (6 bits), K (5 bits), L (4 bits), M (3 bits), N (2 bits), O (1 bit) These bits can be laid out in a 16-byte array like this: Byte Offset 0123456789ABCDEF Bit 7 HHHHHHHHHIIIIIII 6 GGGGGGGGGGJJJJJJ 5 FFFFFFFFFFFKKKKK 4 EEEEEEEEEEEELLLL 3 DDDDDDDDDDDDDMMM 2 CCCCCCCCCCCCCCNN 1 BBBBBBBBBBBBBBBO 0 AAAAAAAAAAAAAAAA For example, to test bit X of A, we evaluate ((bits[X] & 1) != 0), or to test bit X of I, we evaluate ((bits[9 + X] & 0x80) != 0). This can be done in 1-2 machine instructions on x86, or 4-6 instructions on ARM. This uses the LPT multiprocessor scheduling algorithm to lay out the bits efficiently. Saves ~450KB of instructions in a recent build of Chromium. Differential Revision: http://reviews.llvm.org/D7954 llvm-svn: 231043
* Remap arguments and non-alloca values used by outlined C++ exception handlers.Andrew Kaylor2015-03-032-0/+445
| | | | | | Differential Revision: http://reviews.llvm.org/D7844 llvm-svn: 231042
* LoopIdiom: Give globals for memset_pattern16 private linkage.Benjamin Kramer2015-03-031-0/+7
| | | | | | | | There's really no reason to have them have entries in the symbol table anymore. Old versions of ld64 had some bugs in this area but those have been fixed long ago. llvm-svn: 231041
* WinEH: Run opt -instnamer over some cppeh tests and update CHECKsReid Kleckner2015-03-033-86/+86
| | | | | | | | | In the future, we should run the output of clang through instnamer to make it easier to manually edit test cases. No functionality change. llvm-svn: 231037
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 without the assertion in DebugLocEntry::finalize() because not all Machine registers can be lowered into DWARF register numbers and floating point constants cannot be expressed. llvm-svn: 231023
* Revert some changes that were made to fix PR20680.Sanjoy Das2015-03-023-19/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-lands change r230921. r230921 was reverted because it broke a clang test; a checkin fixing the clang test will be commited shortly. Summary: As far as I can tell, the real bug causing the issue was fixed in r230533. SCEVExpander should mark an increment operation as nuw or nsw only if it can *prove* that the operation does not overflow. There shouldn't be any situation where we have to do something different because of no-wrap flags generated by SCEVExpander. Revert "IndVarSimplify: Allow LFTR to fire more often" This reverts commit 1ade0f0faa98877b688e0b9da58e876052c1e04e (SVN: 222213). Revert "IndVarSimplify: Don't let LFTR compare against a poison value" This reverts commit c0f2b8b528d8a37b0a1522aae90af649d6357eb5 (SVN: 217102). Reviewers: majnemer, atrick, spatel Differential Revision: http://reviews.llvm.org/D7979 llvm-svn: 231018
* lit: Add 'cd' support to the internal shell and port some testsReid Kleckner2015-03-029-16/+3
| | | | | | | | | | | The internal shell was already threading around a 'cwd' parameter. We just have to make it mutable so that we can update it as the test script executes. If the shell ever grows support for environment variable substitution, we could also implement support for export. llvm-svn: 231017
* Revert "Refactor DebugLocDWARFExpression so it doesn't require access to the"Adrian Prantl2015-03-022-5/+5
| | | | | | This reverts commit 230975 to investigate buildbot breakage. llvm-svn: 231004
* Change SystemZ large tests to use the existing long_tests propertyDavid Blaikie2015-03-022-2/+6
| | | | | | | | | | (this is already used in Clang for a couple of tests) Reviewers: uweigand Differential Revision: http://reviews.llvm.org/D7965 llvm-svn: 230998
* Add r230655 back with a fix.Rafael Espindola2015-03-022-0/+8
| | | | | | | | | | | | | | | | | | | | The issue is that now we have a diag handler during optimizations and get forward every optimization remark, flooding stdout. The same filtering should probably be done with or without a custom handler, but for now just ignore remarks. Original message: gold-plugin: "Upgrade" debug info and handle its warnings. The gold plugin never calls MaterializeModule, so any old debug info was not deleted and could cause crashes. Now that it is being "upgraded", the plugin also has to handle warnings and create Modules with a nice id (it shows in the warning). llvm-svn: 230991
* Revert r230979, should apply to all X86 ELF.Paul Robinson2015-03-021-3/+0
| | | | llvm-svn: 230985
* [PS4] Correct relocation for DWARF TLS references.Paul Robinson2015-03-021-0/+3
| | | | llvm-svn: 230979
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 with a relaxed assertion in DebugLocEntry::finalize() that allows for empty DWARF expressions for constant FP values. llvm-svn: 230975
* AVX-512: Add assembly parser support for Rounding modeElena Demikhovsky2015-03-022-0/+62
| | | | | | By Asaf Badouh <asaf.badouh@intel.com> llvm-svn: 230962
* [mips] Optimize conditional moves where RHS is zero.Vasileios Kalintiris2015-03-021-175/+127
| | | | | | | | | | | | | Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 llvm-svn: 230956
* Teach the verifier to enforce that the alignment argument of memory ↵Owen Anderson2015-03-021-0/+9
| | | | | | intrinsics must be a power of 2. llvm-svn: 230941
* Teach DataLayout that alignments on basic types must be powers of two.Owen Anderson2015-03-022-0/+12
| | | | | | Fixes assertion failures/crashes on bad datalayout specifications. llvm-svn: 230940
* Teach DataLayout that ABI alignments for non-aggregate types must be non-zero.Owen Anderson2015-03-021-0/+6
| | | | | | | This manifested as assertions and/or crashes in later phases of optimization, depending on the build configuration. llvm-svn: 230939
* Teach DataLayout that pointer ABI and preferred alignments are required to ↵Owen Anderson2015-03-022-0/+12
| | | | | | | | be powers of two. Previously this resulted in asserts and/or crashes (depending on build configuration) at various phases in the optimizer. llvm-svn: 230938
* Teach DataLayout that zero-byte pointer sizes don't make sense.Owen Anderson2015-03-021-0/+6
| | | | | | | | Previously this would result in assertion failures or simply crashes at various points in the optimizer when trying to create types of zero bit width. llvm-svn: 230936
* Teach the LLParser to fail gracefully when it encounters an invalid label name.Owen Anderson2015-03-021-0/+11
| | | | | | Previous it would either assert in +Asserts, or crash in -Asserts. Found by fuzzing LLParser. llvm-svn: 230935
* Fix a crash in the LL parser where it failed to validate that the pointer ↵Owen Anderson2015-03-021-0/+11
| | | | | | | | operand of a GEP was valid. This manifested as an assertion failure in +Asserts builds, and a hard crash in -Asserts builds. Found by fuzzing the LL parser. llvm-svn: 230934
* [llvm-pdbdump] Many minor fixes and improvementsZachary Turner2015-03-025-3/+124
| | | | | | | | | | | | | | | | | A short list of some of the improvements: 1) Now supports -all command line argument, which implies many other command line arguments to simplify usage. 2) Now supports -no-compiler-generated command line argument to exclude compiler generated types. 3) Prints base class list. 4) -class-definitions implies -types. 5) Proper display of bitfields. 6) Can now distinguish between struct/class/interface/union. And a few other minor tweaks. llvm-svn: 230933
* Revert r230930, it caused PR22747.Nico Weber2015-03-022-5/+5
| | | | llvm-svn: 230932
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-022-5/+5
| | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. llvm-svn: 230930
* Revert r230921, "Revert some changes that were made to fix PR20680.", for now.NAKAMURA Takumi2015-03-023-11/+19
| | | | | | It caused a failure on clang/test/Misc/backend-optimization-failure.cpp . llvm-svn: 230929
* [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that ↵Craig Topper2015-03-021-0/+3
| | | | | | doesn't fit in 5-bits. Fixes PR22743. llvm-svn: 230924
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