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* [SeparateConstOffsetFromGEP] Preserve metadata when splitting GEPsMarek Olsak2018-01-311-0/+45
| | | | | | | | | | | | | | Summary: !amdgpu.uniform needs to be preserved for AMDGPU, otherwise bad things happen. Reviewers: arsenm, nhaehnle, jingyue, broune, majnemer, bjarke.roune, dblaikie Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D42744 llvm-svn: 323907
* [MachineOutliner] Freeze registers in new functionsGeoff Berry2018-01-311-1/+1
| | | | | | | | | | | | | | | Summary: Call MRI.freezeReservedRegs() on functions created during outlining so that calls to isReserved() by the verifier called after this pass won't assert. Reviewers: MatzeB, qcolombet, paquette Subscribers: mcrosier, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D42749 llvm-svn: 323905
* [WebAssembly] MC: Resolve aliases when creating provisional table entriesSam Clegg2018-01-311-4/+4
| | | | | | | | | | | | | | | | This change is useful for the upcoming addition of the symbol table (D41954) since in that world aliases for given function all share the same function index. This change does not effect lld because it essentially ignores the wasm "table". The table exists only to the wasm objects will validate and disassembly meaningfully. Patch by Nicholas Wilson! Differential Revision: https://reviews.llvm.org/D42095 llvm-svn: 323900
* [X86] Generate testl instruction through truncates.Amaury Sechet2018-01-312-8/+4
| | | | | | | | | | | | | | | Summary: This was introduced in D42646 but ended up being reverted because the original implementation was buggy. Depends on D42646 Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42741 llvm-svn: 323899
* [Analysis] Disable calls to *_finite and other glibc-only functions on Android.Chih-Hung Hsieh2018-01-311-0/+24
| | | | | | | | | | Since r322087, glibc's finite lib calls are generated when possible. However, they are not supported on Android. This change also disables other functions not available on Android. Differential Revision: http://reviews.llvm.org/D42668 llvm-svn: 323898
* [llvm-cov] Improvements for summary report generated in HTML format.Max Moroz2018-01-313-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds the following changes: 1) coverage numbers are aligned to the left and padded with spaces in order to provide better readability for percentage values, e.g.: ``` file1 | 89.13% (123 / 2323) | 100.00% (55 / 55) | 9.33% (14545 / 234234) file_asda | 1.78% ( 23 / 4323) | 32.31% (555 / 6555) | 67.89% (1545 / 2234) fileXXX | 100.00% (12323 / 12323) | 100.00% (555 / 555) | 100.00% (12345 / 12345) ``` 2) added "hover" attribute to CSS for highlighting table row under mouse cursor see screenshot attached to the phabricator review page {F5764813} 3) table title row and "totals" row now use bold text Reviewers: vsk, morehouse Reviewed By: vsk Subscribers: kcc, llvm-commits Differential Revision: https://reviews.llvm.org/D42093 llvm-svn: 323892
* [CodeGenPrepare] Improve source and dest alignments of memory intrinsics ↵Daniel Neilson2018-01-311-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | independently Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the CodeGenPrepare pass to be more aggressive in improving the source and destination alignments of memcpy/memmove/memset by exploiting our new ability to record independent alignments for each argument. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. ( rL323886 ) Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 323891
* [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorRegKrzysztof Parzyszek2018-01-311-0/+39
| | | | llvm-svn: 323889
* [X86] Avoid using high register trick for test instructionAmaury Sechet2018-01-312-8/+4
| | | | | | | | | | | | | Summary: It seems it's main effect is to create addition copies when values are inr register that do not support this trick, which increase register pressure and makes the code bigger. Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42646 llvm-svn: 323888
* [Hexagon] Only process bitcasts of vsplats when selecting const vectorsKrzysztof Parzyszek2018-01-311-0/+37
| | | | | | | | Selecting of constant HVX vectors involves some "manual processing", which mishandled an unrelated BITCAST operation causing a selection error. llvm-svn: 323887
* [Lint] Upgrade uses of MemoryIntrinic::getAlignment() to new API. (NFCI)Daniel Neilson2018-01-311-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change is part of step five in the series of changes to remove alignment argument from memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the Lint analysis to cease using the old getAlignment() API of MemoryIntrinsic in favour of getting source & dest specific alignments through the new API. Steps: Step 1) Remove alignment parameter and create alignment parameter attributes for memcpy/memmove/memset. ( rL322965, rC322964, rL322963 ) Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. ( rL323597 ) Step 3) Update Clang to use the new IRBuilder API. ( rC323617 ) Step 4) Update Polly to use the new IRBuilder API. ( rL323618 ) Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment() and [get|set]SourceAlignment() instead. Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reference http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html llvm-svn: 323886
* [DWARF] Allow duplication of tails with CFI instructionsPetar Jovanovic2018-01-312-2/+100
| | | | | | | | | | | | | | | | | | This commit came as a result for revert of patch r317579 (originally committed as r317100). The patch made CFI instructions duplicable, because their existence in the epilogue block was affecting the Tail duplication pass. However, duplicating blocks with CFI instructions was an issue for compact unwind info on Darwin, which is why the patch was reverted. This patch allows duplicating tails with CFI instructions, though they are not duplicable, by copying them 'manually'. Patch by Djordje Kovacevic. Differential Revision: https://reviews.llvm.org/D40979 llvm-svn: 323883
* [InstCombine] move related tests into the same file; NFCSanjay Patel2018-01-312-31/+31
| | | | llvm-svn: 323882
* [InstCombine] add tests to show limit of canEvaluate* ; NFCSanjay Patel2018-01-311-10/+65
| | | | llvm-svn: 323881
* [DAG] Prevent NodeId pruning of TokenFactors in Instruction Selection.Nirav Dave2018-01-311-0/+76
| | | | | | | | | | | | | | | | | | Summary: Instruction Selection preserves relative orders of all nodes save TokenFactors which we treat specially. As a result Node Ids for TokenFactors may violate the topological ordering and should not be considered as valid pruning candidates in predecessor search. Fixes PR35316. Reviewers: RKSimon, hfinkel Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D42701 llvm-svn: 323880
* Fix build error in r323870Marina Yatsina2018-01-311-0/+2
| | | | | Change-Id: I15a8b27764a4d817cfbe48836bf09dc6520934b7 llvm-svn: 323874
* [MachineCombiner] Add check for optimal pattern order.Florian Hahn2018-01-316-18/+18
| | | | | | | | | | | | | | | | | | | | | | In D41587, @mssimpso discovered that the order of some patterns for AArch64 was sub-optimal. I thought a bit about how we could avoid that case in the future. I do not think there is a need for evaluating all patterns for now. But this patch adds an extra (expensive) check, that evaluates the latencies of all patterns, and ensures that the latency saved decreases for subsequent patterns. This catches the sub-optimal order fixed in D41587, but I am not entirely happy with the check, as it only applies to sub-optimal patterns seen while building with EXPENSIVE_CHECKS on. It did not discover any other sub-optimal pattern ordering. Reviewers: Gerolf, spatel, mssimpso Reviewed By: Gerolf, mssimpso Differential Revision: https://reviews.llvm.org/D41766 llvm-svn: 323873
* Take into account the cost of local intervals when selecting split candidate.Marina Yatsina2018-01-313-112/+219
| | | | | | | | | | | | | When selecting a split candidate for region splitting, the register allocator tries to predict which candidate will have the cheapest spill cost. Global splitting may cause the creation of local intervals, and they might spill. This patch makes RA take into account the spill cost of local split intervals in use blocks (we already take into account the spill cost in through blocks). A flag ("-condsider-local-interval-cost") controls weather we do this advanced cost calculation (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D41585 Change-Id: Icccb8ad2dbf13124f5d97a18c67d95aa6be0d14d llvm-svn: 323870
* [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operationsPablo Barrio2018-01-314-5/+138
| | | | | | | | | | | | | | | | | | | Summary: Expressions of the form x < 0 ? 0 : x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before. Patch by Marten Svanfeldt. Reviewers: fhahn, pbarrio Reviewed By: pbarrio Subscribers: efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42574 llvm-svn: 323869
* Add a regression test for problems caused by D42646 . NFCAmaury Sechet2018-01-311-9/+90
| | | | llvm-svn: 323868
* [SystemZ] Check the bitwidth before calling isInt/isUInt.Jonas Paulsson2018-01-311-0/+25
| | | | | | | | | Since these methods will assert if the integer does not fit into 64 bits, it is necessary to do this check before calling them in supportedAddressingMode(). Review: Ulrich Weigand. llvm-svn: 323866
* [AggressiveInstCombine] Make TruncCombine class ignore unreachable basic blocks.Amjad Aboud2018-01-311-0/+48
| | | | | | | | | Because dead code may contain non-standard IR that causes infinite looping or crashes in underlying analysis. See PR36134 for more details. Differential Revision: https://reviews.llvm.org/D42683 llvm-svn: 323862
* [ARM] Armv8.2-A FP16 code generation (part 2/3)Sjoerd Meijer2018-01-311-9/+5
| | | | | | | | | | | | Half-precision arguments and return values are passed as if it were an int or float for ARM. This results in truncates and bitcasts to/from i16 and f16 values, which are legalized very early to stack stores/loads. When FullFP16 is enabled, we want to avoid codegen for these bitcasts as it is unnecessary and inefficient. Differential Revision: https://reviews.llvm.org/D42580 llvm-svn: 323861
* [PowerPC] Return true in enableMultipleCopyHints().Jonas Paulsson2018-01-314-52/+31
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Nemanja Ivanovic llvm-svn: 323858
* [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ ↵Roger Ferrer Ibanez2018-01-312-0/+113
| | | | | | | | | | | | | | | | | | | | | | GPR. In Thumb 1, with the new ADDCARRY / SUBCARRY the scheduler may need to do copies CPSR ↔ GPR but not all Thumb1 targets implement them. The schedule can attempt, before attempting a copy, to clone the instructions but it does not currently do that for nodes with input glue. In this patch we introduce a target-hook to let the hook decide if a glued machinenode is still eligible for copying. In this case these are ARM::tADCS and ARM::tSBCS . As a follow-up of this change we should actually implement the copies for the Thumb1 targets that do implement them and restrict the hook to the targets that can't really do such copy as these clones are not ideal. This change fixes PR35836. Differential Revision: https://reviews.llvm.org/D42051 llvm-svn: 323857
* Mark two tests REQUIRES: x86-registered-backendJustin Bogner2018-01-312-0/+2
| | | | | | | | These were introduced in r323783 and use an X86 triple. I'll follow up on the list to check if it would make more sense to remove the triple and mark them REQUIRES: default_triple instead. llvm-svn: 323847
* LTO: Drop comdats when converting definitions to declarations.Peter Collingbourne2018-01-311-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D42715 llvm-svn: 323844
* Revert r323559 due to EXPENSIVE_CHECKS regression.Eli Friedman2018-01-311-47/+0
| | | | | | | I have a fix for the issue (https://reviews.llvm.org/D42655) but it's taking a while to get reviewed, so reverting in the meantime. llvm-svn: 323841
* [X86] Add more madd reduction tests with wider vectors.Craig Topper2018-01-311-10/+508
| | | | | | We had no test case exercising 512-bit vpmaddwd usage. llvm-svn: 323840
* llvm-nm should show a symbol type of T for symbols in the ↵Kevin Enderby2018-01-313-0/+6
| | | | | | | | | | | | | | | (__TEXT_EXEC,__text) section. When a the Apple link editor builds a kext bundle file type and the value of the -miphoneos-version-min argument is significantly current (like 11.0) then the (__TEXT,__text) section is changed to the (__TEXT_EXEC,__text) section. So it would be nice for llvm-nm to show symbols in that section with a type of T instead of the generic type of S for some section other than text, data, etc. rdar://36262205 llvm-svn: 323836
* [RDF] Clear the renamable flag when copy propagating reserved registersKrzysztof Parzyszek2018-01-301-0/+19
| | | | llvm-svn: 323831
* LLParser: add an argument for overriding data layout and do not check alloca ↵Yaxun Liu2018-01-308-33/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | addr space Sometimes users do not specify data layout in LLVM assembly and let llc set the data layout by target triple after loading the LLVM assembly. Currently the parser checks alloca address space no matter whether the LLVM assembly contains data layout definition, which causes false alarm since the default data layout does not contain the correct alloca address space. The parser also calls verifier to check debug info and updating invalid debug info. Currently there is no way to let the verifier to check debug info only. If the verifier finds non-debug-info issues the parser will fail. For llc, the fix is to remove the check of alloca addr space in the parser and disable updating debug info, and defer the updating of debug info and verification to be after setting data layout of the IR by target. For other llvm tools, since they do not override data layout by target but instead can override data layout by a command line option, an argument for overriding data layout is added to the parser. In cases where data layout overriding is necessary for the parser, the data layout can be provided by command line. Differential Revision: https://reviews.llvm.org/D41832 llvm-svn: 323826
* [LLVM-C] Add Accessors For A Module's Source File NameRobert Widmann2018-01-301-0/+1
| | | | | | | | | | | | | | Summary: Also unblocks some cleanup in the echo-test. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: harlanhaskins, llvm-commits Differential Revision: https://reviews.llvm.org/D42618 llvm-svn: 323819
* [ThinLTO/gold] Write empty imports even for modules with symbolsVitaly Buka2018-01-301-12/+15
| | | | | | | | | | | | Summary: ThinLTO may skip object for other reasons, e.g. if there is no summary. Reviewers: pcc, eugenis Subscribers: mehdi_amini, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D42514 llvm-svn: 323818
* [AArch64] Expand testing of zero cycle zeroingEvandro Menezes2018-01-301-34/+29
| | | | | | | | Make sure that r321824 doesn't change zeroing. Differential revision: https://reviews.llvm.org/D42089 llvm-svn: 323816
* [SLP] Add extra test for extractelement shuffle, NFC.Alexey Bataev2018-01-301-0/+25
| | | | llvm-svn: 323815
* Teach ValueMapper to use ODR uniqued types when availableTeresa Johnson2018-01-302-0/+101
| | | | | | | | | | | | | | | | | Summary: This is exposed during ThinLTO compilation, when we import an alias by creating a clone of the aliasee. Without this fix the debug type is unnecessarily cloned and we get a duplicate, undoing the uniquing. Fixes PR36089. Reviewers: mehdi_amini, pcc Subscribers: eraman, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41669 llvm-svn: 323813
* [dsymutil] Enable -minimize feature.Jonas Devlieghere2018-01-302-0/+10
| | | | | | | | | | | | | Passing -minimize to dsymutil prevents the emission of .debug_inlines, .debug_pubnames, and .debug_pubtypes in favor of the Apple accelerator tables. The actual check in the DWARF linker was added in r323655. This patch simply enables it. Differential revision: https://reviews.llvm.org/D42688 llvm-svn: 323812
* [GlobalISel] Bail out on calls to dllimported functionsMartin Storsjo2018-01-301-1/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D42568 llvm-svn: 323811
* [AArch64] Properly handle dllimport of variables when using fast-iselMartin Storsjo2018-01-301-4/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D42567 llvm-svn: 323810
* [TableGen] Make sure !if is evaluated throughout class inheritance.Artem Belevich2018-01-301-0/+17
| | | | | | | | | | | | | | | | Without the patch !if() is only evaluated if it's used directly. If it's passed through more than one level of class inheritance, we end up with a reference to an anonymous record with unresolved references to the original arguments !if may have used. The root cause of the problem is that TernOpInit::isComplete() was always returning false and that prevented use of the folded value of !if() as an initializer for the record at the next level of inheritance. Differential Revision: https://reviews.llvm.org/D42695 llvm-svn: 323807
* [LoopStrengthReduce] add test to show potential macro-fusion-based diff ↵Sanjay Patel2018-01-301-0/+126
| | | | | | | | (PR35681); NFC This is the baseline output for the test proposed with D42607. llvm-svn: 323806
* [DWARF] Recommitting a test that was removed with r323564. Restricted to x86 ↵Wolfgang Pieb2018-01-301-0/+123
| | | | | | linux target. llvm-svn: 323804
* [Hexagon] Handle non-aligned offsets in globals in extender optimizationKrzysztof Parzyszek2018-01-301-0/+34
| | | | | | | | | | Instructions like memd(r0+##global+1) are legal as long as the entire address is properly aligned. Assuming that "global" is aligned at an 8-byte boundary, the expression "global+1" appears to be misaligned. Handle such cases in HexagonConstExtenders, and make sure that any non- extended offsets generated are still aligned accordingly. llvm-svn: 323799
* Revert: [Hexagon] Make sure that offset on globals matches alignment ↵Krzysztof Parzyszek2018-01-301-19/+20
| | | | | | | | | | | | | requirements This reverts r323562, since it wasn't actually necessary. Constant- extended offsets do not need to be aligned, as long as the effective address is aligned. Keep the testcase, with a modification which checks that such offsets are not unnecessarily avoided. llvm-svn: 323798
* [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOPSimon Pilgrim2018-01-301-6/+3
| | | | | | | | Similar to D42437, XOP supports variable shift for v16i8/v8i16/v4i32/v2i64 types. Differential Revision: https://reviews.llvm.org/D42526 llvm-svn: 323797
* [AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry2018-01-302-5/+5
| | | | | | | | | | | Mark more opcodes as hasExtraSrcRegAllocReq so that their operands will be marked as not renamable, to avoid copy forwarding violating the constraint that only one operand may use the constant bus. These changes fix a few mis-compiles when copy forwarding is enabled in MachineCopyPropagation by D41835 (and were reviewed as part of that change). llvm-svn: 323794
* [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr ↵Mark Searles2018-01-301-41/+0
| | | | | | | | | | | | | count in debug output." Patch caused a buildbot failure; arg; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17373/s\ teps/build_Lld/logs/stdio : /Users/buildslave/as-bldslv9/lld-x86_64-darwin13/llvm.src/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:1563:18: error: unused variable 'InstCnt' [-Werror,-Wunused-variable] static int32_t InstCnt = 0; " This reverts commit 4f4a7d61e306b67044d9f16bc2016fee806bc2cc. llvm-svn: 323791
* [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug ↵Mark Searles2018-01-301-0/+41
| | | | | | | | | | | | | | | output. -amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs This patch was pushed ( abb190fd51cd2f9a9eef08c024e109f7f7e909fc ), which caused a buildbot failure, reverted ( 6227480d74da507cf8e1b4bcaffbdb9fb875b4b8 ), and then updated to fix buildbot failures (this patch). Differential Revision: https://reviews.llvm.org/D40091 llvm-svn: 323788
* AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace.Changpeng Fang2018-01-302-0/+100
| | | | | | | | | | Reviewer: Dmitry (dp). Differential Revision: https://reviews.llvm.org/D42596 llvm-svn: 323785
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