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* [llvm-cov] Add one correction to r315960 (PR34962)Vedant Kumar2017-10-171-1/+1
| | | | | | | | | In r315960, I accidentally assumed that the first line segment is guaranteed to be the non-gap region entry segment (given that one is present). It can actually be any segment on the line, and the test I checked in demonstrates that. llvm-svn: 315963
* Try to make crlf portable to other printf implementationsReid Kleckner2017-10-172-1/+3
| | | | llvm-svn: 315961
* [llvm-cov] Remove workaround in line execution count calculation (PR34962)Vedant Kumar2017-10-163-0/+12
| | | | | | | | | | | | | Gap areas make it possible to correctly determine when to use counts from deferred regions. Before gap areas were introduced, llvm-cov needed to use a heuristic to do this: it ignored counts from segments that start, but do not end, on a line. This heuristic breaks down on a simple example (see PR34962). This patch removes the heuristic and picks counts from any region entry segment which isn't a gap area. llvm-svn: 315960
* Use the return value of UpdateNodeOperands(); in some cases, ↵Mark Searles2017-10-161-0/+95
| | | | | | | | UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats). Differential Revision: https://reviews.llvm.org/D38466 llvm-svn: 315957
* [X86][AVX] Add v4x64 vector shuffle test for <0,2,1,3> maskSimon Pilgrim2017-10-161-0/+42
| | | | llvm-svn: 315955
* Re-apply [AArch64][RegisterBankInfo] Use the statically computed mappings ↵Quentin Colombet2017-10-161-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for COPY This reverts commit r315823, thus re-applying r315781. Also make sure we don't use G_BITCAST mapping for non-generic registers. Non-generic registers don't have a type but do have a reg bank. Something the COPY mapping now how to deal with but the G_BITCAST mapping don't. -- Original Commit Message -- We use to resort on the generic implementation to get the mappings for COPYs. The generic implementation resorts on table lookup and dynamically allocated objects to get the valid mappings. Given we already know how to map G_BITCAST and have the static mappings for them, use that code path for COPY as well. This is much more efficient. Improve the compile time of RegBankSelect by up to 20%. Note: When we eventually generate all the mappings via TableGen, we wouldn't have to do that dance to shave compile time. The intent of this change was to make sure that moving to static structure really pays off. NFC. llvm-svn: 315947
* [AArch64][RegisterBankInfo] Add mapping support for G_BITCAST of s128Quentin Colombet2017-10-161-0/+27
| | | | | | Anything bigger than 64-bit just map to FPR. llvm-svn: 315946
* [AArch64][LegalizerInfo] Mark s128 G_BITCAST legalQuentin Colombet2017-10-161-0/+26
| | | | | | | We used to mark all G_BITCAST of 128-bit legal but only for vector types. Scalars of this size are just fine as well. llvm-svn: 315945
* Add !callees metadataMatthew Simpson2017-10-161-2/+2
| | | | | | | | | This patch adds a new kind of metadata that indicates the possible callees of indirect calls. Differential Revision: https://reviews.llvm.org/D37354 llvm-svn: 315944
* [MC] Lex CRLF as one tokenReid Kleckner2017-10-161-0/+5
| | | | | | | | | | This will prevent doubling of line endings when parsing assembly and emitting assembly. Otherwise we'd parse the directive, consume the end of statement, hit the next end of statement, and emit a fresh newline. llvm-svn: 315943
* [X86][3DNow] Add scheduling latency/throughput tests for 3DNow! instructionsSimon Pilgrim2017-10-161-0/+372
| | | | llvm-svn: 315942
* [X86][MMX] Add scheduling latency/throughput tests for MMX instructionsSimon Pilgrim2017-10-161-0/+6342
| | | | llvm-svn: 315939
* Add base relative relocation record that can be used for the following case ↵Tony Tye2017-10-161-0/+4
| | | | | | | | | | | | | | (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
* [AMDGPU] : revert r315908Alexander Timofeev2017-10-161-27/+0
| | | | llvm-svn: 315916
* [ObjCARC] Do not move a release that has the clang.imprecise_release tagAkira Hatanaka2017-10-161-0/+20
| | | | | | | | | | | | | | above PHI instructions. ARC optimizer has an optimization that moves a call to an ObjC runtime function above a phi instruction when the phi has a null operand and is an argument passed to the function call. This optimization should not kick in when the runtime function is an objc_release that releases an object with precise lifetime semantics. rdar://problem/34959669 llvm-svn: 315914
* [x86] add minmax tests with more predicate coverage; NFCSanjay Patel2017-10-161-0/+30
| | | | llvm-svn: 315913
* [AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the ↵Alexander Timofeev2017-10-161-0/+27
| | | | | | | | dead one Differential revision: https://reviews.llvm.org/D38754 llvm-svn: 315908
* Fix test name typo.Simon Pilgrim2017-10-161-5/+5
| | | | llvm-svn: 315907
* [X86][SSE] Added additional PACKUS shuffle testsSimon Pilgrim2017-10-163-0/+102
| | | | | | Mainly inspired by PR34773 llvm-svn: 315906
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-163-3/+11
| | | | | | | | | | | | Previously these instructions were marked codegen only and had an under-specified instruction description that did not record the fcc register. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D38847 llvm-svn: 315905
* [mips] Provide alternate predicates for constant synthesisStefan Maksimovic2017-10-161-0/+136
| | | | | | | Ordering of patterns should not be of importance anymore since the predicates used are mutually exclusive now. llvm-svn: 315901
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-165-21/+91
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [llvm-dwarfdump] - Teach tool to parse DW_CFA_GNU_args_size.George Rimar2017-10-161-0/+15
| | | | | | | | | Currently llvm-dwarfdump runs into llvm_unreachable when faces DW_CFA_GNU_args_size. Patch implements the support. Differential revision: https://reviews.llvm.org/D38879 llvm-svn: 315897
* Revert rL315894, "SLPVectorizer.cpp: Try to appease stage2-3 difference. ↵NAKAMURA Takumi2017-10-161-153/+0
| | | | | | (D38586)" llvm-svn: 315896
* Move folding of icmp with zero after checking for min/max idioms.Nikolai Bozhenov2017-10-161-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: The following transformation for cmp instruction: icmp smin(x, PositiveValue), 0 -> icmp x, 0 should only be done after checking for min/max to prevent infinite looping caused by a reverse canonicalization. That is why this transformation was moved to place after the mentioned check. Reviewers: spatel, efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38934 Patch by: Artur Gainullin <artur.gainullin@intel.com> llvm-svn: 315895
* SLPVectorizer.cpp: Try to appease stage2-3 difference. (D38586)NAKAMURA Takumi2017-10-161-0/+153
| | | | llvm-svn: 315894
* bpf: fix bug on silently truncating 64-bit immediateYonghong Song2017-10-161-0/+35
| | | | | | | | | | | | | | | | We came across an llvm bug when compiling some testcases that 64-bit immediates are silently truncated into 32-bit and then packed into BPF_JMP | BPF_K encoding. This caused comparison with wrong value. This bug looks to be introduced by r308080. The Select_Ri pattern is supposed to be lowered into J*_Ri while the latter only support 32-bit immediate encoding, therefore Select_Ri should have similar immediate predicate check as what J*_Ri are doing. Reported-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 315889
* [PowerPC] Eliminate sign- and zero-extensions if already sign- or zero-extendedHiroshi Inoue2017-10-164-62/+4
| | | | | | | | | | | | | | | | | | This patch enables redundant sign- and zero-extension elimination in PowerPC MI Peephole pass. If the input value of a sign- or zero-extension is known to be already sign- or zero-extended, the operation is redundant and can be eliminated. One common case is sign-extensions for a method parameter or for a method return value; they must be sign- or zero-extended as defined in PPC ELF ABI. For example of the following simple code, two extsw instructions are generated before the invocation of int_func and before the return. With this patch, both extsw are eliminated. void int_func(int); void ii_test(int a) { if (a & 1) return int_func(a); } Such redundant sign- or zero-extensions are quite common in many programs; e.g. I observed about 60,000 occurrences of the elimination while compiling the LLVM+CLANG. Differential Revision: https://reviews.llvm.org/D31319 llvm-svn: 315888
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-162-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | am_unscaled* and am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. The previous commit failed on MSVC due to a failure to convert an initializer_list to a std::vector. Hopefully, MSVC will accept this version. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315887
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement ↵Daniel Sanders2017-10-161-2/+6
| | | | | | | | am_unscaled* and am_indexed* MSVC doesn't like one of the constructors. llvm-svn: 315886
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and ↵Daniel Sanders2017-10-161-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | am_indexed* Summary: iPTR is a pointer of subtarget-specific size to any address space. Therefore type checks on this size derive the SizeInBits from a subtarget hook. At this point, we can import the simplests G_LOAD rules and select load instructions using them. Further patches will support for the predicates to enable additional loads as well as the stores. Depends on D37457 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37458 llvm-svn: 315885
* [globalisel][tablegen] Implement unindexed load, non-extending load, and ↵Daniel Sanders2017-10-162-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ↵Daniel Sanders2017-10-151-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ↵Daniel Sanders2017-10-151-23/+9
| | | | | | | | operator A large number of bots are failing on an ambiguous constructor call. llvm-svn: 315866
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-9/+23
| | | | | | | | | | | | | | | | | | | | | | | Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315863
* [AVX512] Don't mark EXTLOAD as legal with AVX512. Continue using custom ↵Craig Topper2017-10-154-179/+66
| | | | | | | | | | | | | | | | | | | lowering. Summary: This was impeding our ability to combine the extending shuffles with other shuffles as you can see from the test changes. There's one special case that needed to be added to use VZEXT directly for v8i8->v8i64 since the custom lowering requires v64i8. Reviewers: RKSimon, zvi, delena Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38714 llvm-svn: 315860
* revert r314984: revert r314698 - [InstCombine] remove one-use restriction ↵Sanjay Patel2017-10-151-1/+1
| | | | | | | | | for icmp (shr exact X, C1), C2 --> icmp X, (C2<<C1) Recommitting r314698. The bug exposed by this change should be fixed with: https://reviews.llvm.org/rL315579 llvm-svn: 315857
* [MergeFunctions] Merge small functions if possible without a thunk.whitequark2017-10-151-0/+14
| | | | | | | | | | This can result in significant code size savings in some cases, e.g. an interrupt table all filled with the same assembly stub in a certain Cortex-M BSP results in code blowup by a factor of 2.5. Differential Revision: https://reviews.llvm.org/D34806 llvm-svn: 315853
* [MergeFunctions] Replace all uses of unnamed_addr functions.whitequark2017-10-152-0/+48
| | | | | | | | | This reduces code size for constructs like vtables or interrupt tables that refer to functions in global initializers. Differential Revision: https://reviews.llvm.org/D34805 llvm-svn: 315852
* [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve ↵Amjad Aboud2017-10-151-0/+60
| | | | | | | | PR34565 Differential Revision: https://reviews.llvm.org/D38359 llvm-svn: 315851
* [X86] Lower vselect with constant condition to vector_shuffle even with ↵Craig Topper2017-10-153-28/+9
| | | | | | | | | | | | | | | | | | | AVX512 instructions. Summary: It's better to use our shuffle lowering code to handle these than loading an immediate into a k-register. It really feels like this should be a DAG combine optimization rather than a lowering operation, but that's a problem for another day. Reviewers: RKSimon, delena, zvi Reviewed By: delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38932 llvm-svn: 315849
* [X86] Don't use constant condition for select instruction when testing ↵Craig Topper2017-10-1515-11688/+13891
| | | | | | | | masking ops. We should be able to fold constant conditions by converting to shuffles, but fixing that would break these tests in their current form. Since they are really trying to test masking ops, add a non-constant mask to the selects. llvm-svn: 315848
* AMDGPU: Temporary disable pal metadata check line in llvm-readobj testKonstantin Zhuravlyov2017-10-141-1/+2
| | | | | | It fails on mips llvm-svn: 315837
* [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.Craig Topper2017-10-141-1105/+0
| | | | llvm-svn: 315828
* [X86][SSE] Don't attempt to reduce the imul vector width of odd sized ↵Simon Pilgrim2017-10-141-0/+105
| | | | | | vectors (PR34947) llvm-svn: 315825
* [X86][SSE] Test vector imul reduction on 32 and 64-bit targetsSimon Pilgrim2017-10-141-358/+846
| | | | llvm-svn: 315824
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-1412-185/+239
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* llvm-readobj: Print AMDGPU note contentsKonstantin Zhuravlyov2017-10-149-25/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D38752 llvm-svn: 315819
* Cleanup update_llc_test_checks.py notes.Simon Pilgrim2017-10-145-5/+2
| | | | llvm-svn: 315817
* AMDGPU: Cleanup elf-notes.ll testKonstantin Zhuravlyov2017-10-141-26/+25
| | | | llvm-svn: 315816
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