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* Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed.Cong Hou2016-03-234-30/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, AnalyzeBranch() fails non-equality comparison between floating points on X86 (see https://llvm.org/bugs/show_bug.cgi?id=23875). This is because this function can modify the branch by reversing the conditional jump and removing unconditional jump if there is a proper fall-through. However, in the case of non-equality comparison between floating points, this can turn the branch "unanalyzable". Consider the following case: jne.BB1 jp.BB1 jmp.BB2 .BB1: ... .BB2: ... AnalyzeBranch() will reverse "jp .BB1" to "jnp .BB2" and then "jmp .BB2" will be removed: jne.BB1 jnp.BB2 .BB1: ... .BB2: ... However, AnalyzeBranch() cannot analyze this branch anymore as there are two conditional jumps with different targets. This may disable some optimizations like block-placement: in this case the fall-through behavior is enforced even if the fall-through block is very cold, which is suboptimal. Actually this optimization is also done in block-placement pass, which means we can remove this optimization from AnalyzeBranch(). However, currently X86::COND_NE_OR_P and X86::COND_NP_OR_E are not reversible: there is no defined negation conditions for them. In order to reverse them, this patch defines two new CondCode X86::COND_E_AND_NP and X86::COND_P_AND_NE. It also defines how to synthesize instructions for them. Here only the second conditional jump is reversed. This is valid as we only need them to do this "unconditional jump removal" optimization. Differential Revision: http://reviews.llvm.org/D11393 llvm-svn: 264199
* Fix logic for which symbols to keep with comdats.Rafael Espindola2016-03-233-1/+93
| | | | | | | | | | | | If a comdat is dropped, all symbols in it are dropped. If a comdat is kept, the symbols survive to pass regular symbol resolution. With this patch we do that for all global symbols. The added test is a copy of test/tools/gold/X86/comdat.ll that we now pass. llvm-svn: 264192
* Fix a crash in running llvm-objdump -t with an invalid Mach-O file alreadyKevin Enderby2016-03-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in the test suite. While this is not really an interesting tool and option to run on a Mach-O file to show the symbol table in a generic libObject format it shouldn’t crash. The reason for the crash was in MachOObjectFile::getSymbolType() when it was calling MachOObjectFile::getSymbolSection() without checking its return value for the error case. What makes this fix require a fair bit of diffs is that the method getSymbolType() is in the class ObjectFile defined without an ErrorOr<> so I needed to add that all the sub classes.  And all of the uses needed to be updated and the return value needed to be checked for the error case. The MachOObjectFile version of getSymbolType() “can” get an error in trying to come up with the libObject’s internal SymbolRef::Type when the Mach-O symbol symbol type is an N_SECT type because the code is trying to select from the SymbolRef::ST_Data or SymbolRef::ST_Function values for the SymbolRef::Type. And it needs the Mach-O section to use isData() and isBSS to determine if it will return SymbolRef::ST_Data. One other possible fix I considered is to simply return SymbolRef::ST_Other when MachOObjectFile::getSymbolSection() returned an error. But since in the past when I did such changes that “ate an error in the libObject code” I was asked instead to push the error out of the libObject code I chose not to implement the fix this way. As currently written both the COFF and ELF versions of getSymbolType() can’t get an error. But if isReservedSectionNumber() wanted to check for the two known negative values rather than allowing all negative values or the code wanted to add the same check as in getSymbolAddress() to use getSection() and check for the error then these versions of getSymbolType() could return errors. At the end of the day the error printed now is the generic “Invalid data was encountered while parsing the file” for object_error::parse_failed. In the future when we thread Lang’s new TypedError for recoverable error handling though libObject this will improve. And where the added // Diagnostic(… comment is, it would be changed to produce and error message like “bad section index (42) for symbol at index 8” for this case. llvm-svn: 264187
* Codegen: [PPC] Word Rotates are Zero Extending.Kyle Butt2016-03-231-0/+57
| | | | | | | Add Word rotates to the list of instructions that are zero extending. This allows them to be used in dot form to compare with zero. llvm-svn: 264183
* Fix bugs in the MemorySSA walker.George Burgess IV2016-03-232-0/+237
| | | | | | | | | | | | | | | | | | There are a few bugs in the walker that this patch addresses. Primarily: - Caching can break when we have multiple BBs without phis - We weren't optimizing some phis properly - Because of how the DFS iterator works, there were times where we wouldn't cache any results of our DFS I left the test cases with FIXMEs in, because I'm not sure how much effort it will take to get those to work (read: We'll probably ultimately have to end up redoing the walker, or we'll have to come up with some creative caching tricks), and more test coverage = better. Differential Revision: http://reviews.llvm.org/D18065 llvm-svn: 264180
* [X86] Regenerated WidenArith testSimon Pilgrim2016-03-231-10/+12
| | | | llvm-svn: 264157
* [AArch64] Replace some uses of report_fatal_error with reportError in ↵Oliver Stannard2016-03-231-0/+18
| | | | | | | | | | | | AArch64 ELF object writer If we can't handle a relocation type, report it as an error in the source, rather than asserting. I've added a more descriptive message and a test for the only cases of this that I've been able to trigger. Differential Revision: http://reviews.llvm.org/D18388 llvm-svn: 264156
* [X86] Introduction of FeatureX87.Andrey Turetskiy2016-03-231-0/+55
| | | | | | | | Add FeatureX87 in X86 backend to be able to define CPUs which doesn't have x87. Differential Revision: http://reviews.llvm.org/D13979 llvm-svn: 264148
* [mips][microMIPS] Delay slot filler modificationsHrvoje Varga2016-03-231-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D18181 llvm-svn: 264147
* [AMDGPU] Fix missing assembler predicates.Valery Pykhtin2016-03-233-3/+330
| | | | | | Differential Revision: http://reviews.llvm.org/D18351 llvm-svn: 264137
* [StatepointLowering] Schedule gc relocates before uniqueing themSanjoy Das2016-03-231-0/+20
| | | | | | Otherwise we can see an "unexpected" gc.relocate that we uniqued away. llvm-svn: 264127
* [NVVM] Remove noduplicate attribute from synchronizing intrinsics.Justin Lebar2016-03-221-2/+2
| | | | | | | | | | | | | | | Summary: I've completed my audit of all the code that looks at noduplicate and added handling of convergent where appropriate, so we no longer need noduplicate on these intrinsics. Reviewers: jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D18168 llvm-svn: 264107
* Drop comdats from the dst module if they are not selected.Rafael Espindola2016-03-222-0/+38
| | | | | | | | | | | | | | | | | | | | | | | A really unfortunate design of llvm-link and related libraries is that they operate one module at a time. This means they can copy a GV to the destination module that should not be there in the final result because a later bitcode file takes precedence. We already handled cases like a strong GV replacing a weak for example. One case that is not currently handled is a comdat replacing another. This doesn't happen in ELF, but with COFF largest selection kind it is possible. In "llvm-link a.ll b.ll" if the selected comdat was from a.ll, everything will work and we will not copy the comdat from b.ll. But if we run "llvm-link b.ll a.ll", we fail to delete the already copied comdat from b.ll. This patch fixes that. llvm-svn: 264103
* Keep CodeGenPrepare from preserving the domtree.George Burgess IV2016-03-221-0/+41
| | | | | | | | | | CGP modifies the domtree in some cases, so saying that it preserves the domtree is a lie. We'll be able to selectively preserve it with the new pass manager. Differential Revision: http://reviews.llvm.org/D16893 llvm-svn: 264099
* Revert "Support arbitrary addrspace pointers in masked load/store intrinsics"Matthias Braun2016-03-227-278/+183
| | | | | | | | | | | This commit broke LTO builds. Reverting it to unbreak the bots while the issue is investigated. See also: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160321/341002.html This reverts r263158 llvm-svn: 264088
* [X86][AVX] Added AVX1 tests for 256-bit vector idiv-by-constant Simon Pilgrim2016-03-222-1742/+4482
| | | | | | Prep work based on feedback for D18307 llvm-svn: 264086
* [SelectionDAG] Ensure constant folded legalized vector element types are ↵Simon Pilgrim2016-03-221-0/+21
| | | | | | | | compatible with the BUILD_VECTOR type Found during fuzz testing - 32-bit x86 targets were legalizing a <2 x i1> compare result to <2 x i32> when <2 x i64> was expected. llvm-svn: 264085
* CodeGen: check return types match when emitting tail call to builtin.Tim Northover2016-03-222-1/+38
| | | | | | | | | | | We were just completely ignoring the types when determining whether we could safely emit a libcall as a tail call. This is clearly wrong. Theoretically, we could dig deeper looking for incidental matches (much like the generic code in Analysis.cpp does), but it's probably not worth it for the few libcalls that exist. llvm-svn: 264084
* Remove unnecessary branch from testSanjoy Das2016-03-221-3/+0
| | | | | | (Addresses post commit review by Reid Kleckner) llvm-svn: 264083
* [LoopVersioning] Relax an assert for LCSSA PHIsAdam Nemet2016-03-221-0/+35
| | | | | | | | | | | | | When you have multiple LCSSA (single-operand) PHIs that are converted into two-operand PHIs due to versioning, only assert that the PHI currently being converted has a single operand. I.e. we don't want to check PHIs that were converted earlier in the loop. Fixes PR27023. Thanks to Karl-Johan Karlsson for the minimized testcase! llvm-svn: 264081
* Allow lowering call sites with both funclets and deopt stateSanjoy Das2016-03-221-0/+29
| | | | | | | Lowering funclets is a no-op, so we can just go ahead and lower the deopt state. llvm-svn: 264078
* [WebAssembly] Implement the rotate instructions.Dan Gohman2016-03-222-0/+108
| | | | llvm-svn: 264076
* [X86][SSE] Reapplied: Simplify vector LOAD + EXTEND on pre-SSE41 hardwareSimon Pilgrim2016-03-223-76/+105
| | | | | | | | | | | | | | Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions. We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT. Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718). Reapplied with a fix for PR26953 (missing vector widening legalization). Differential Revision: http://reviews.llvm.org/D17932 llvm-svn: 264062
* [mips] Range check simm7.Daniel Sanders2016-03-225-2/+10
| | | | | | | | | | | | | | Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
* [mips] Range check simm5.Daniel Sanders2016-03-221-0/+3
| | | | | | | | | | | | | | | Summary: We can't check the error message for this one because there's another lw/sw available that covers a larger range. We therefore check the transition between the two sizes. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18144 llvm-svn: 264054
* [mips] Range check vsplat_uimm[1234568].Daniel Sanders2016-03-221-24/+158
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18143 llvm-svn: 264053
* [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized ↵Daniel Sanders2016-03-221-0/+22
| | | | | | | | | | | | immediates in MSA copy/insert. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18142 llvm-svn: 264052
* [PATCH] Force LoopReroll to reset the loop trip count value after reroll.Zinovy Nis2016-03-221-1/+1
| | | | | | | | | | | It's a bug fix. For rerolled loops SE trip count remains unchanged. It leads to incorrect work of the next passes. My patch just resets SE info for rerolled loop forcing SE to re-evaluate it next time it requested. I also added a verifier call in the exisitng test to be sure no invalid SE data remain. Without my fix this test would fail with -verify-scev. Differential Revision: http://reviews.llvm.org/D18316 llvm-svn: 264051
* [ELF][gcc compatibility]: support section names with special characters ↵Marina Yatsina2016-03-221-0/+4
| | | | | | | | | | | | (e.g. "/") Adding support for section names with special characters in them (e.g. "/"). GCC successfully compiles such section names. This also fixes PR24520. Differential Revision: http://reviews.llvm.org/D15678 llvm-svn: 264038
* Appease the windows buildbotsSanjoy Das2016-03-221-30/+31
| | | | | | | The guess is that the stdout/stderr ordering may differ between windows / unix. llvm-svn: 264019
* Add "first class" lowering for deopt operand bundlesSanjoy Das2016-03-221-0/+104
| | | | | | | | | | | | | | | | | Summary: After this change, deopt operand bundles can be lowered directly by SelectionDAG into STATEPOINT instructions (which are then lowered to a call or sequence of nop, with an associated __llvm_stackmaps entry0. This obviates the need to round-trip deoptimization state through gc.statepoint via RewriteStatepointsForGC. Reviewers: reames, atrick, majnemer, JosephTremoulet, pgavlin Subscribers: sanjoy, mcrosier, majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D18257 llvm-svn: 264015
* [MemorySSA] Consider def-only BBs for live-in calculations.George Burgess IV2016-03-211-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we have a BB with only MemoryDefs, live-in calculations will ignore it. This means we get results like this: define void @foo(i8* %p) { ; 1 = MemoryDef(liveOnEntry) store i8 0, i8* %p br i1 undef, label %if.then, label %if.end if.then: ; 2 = MemoryDef(1) store i8 1, i8* %p br label %if.end if.end: ; 3 = MemoryDef(1) store i8 2, i8* %p ret void } ...When there should be a MemoryPhi in the `if.end` BB. This patch fixes that behavior. llvm-svn: 263991
* Remove leftover options from multiline.llKrzysztof Parzyszek2016-03-211-2/+2
| | | | | | | I added -march=hexagon to force using Hexagon target when testing locally, and I forgot to take it out. llvm-svn: 263990
* Add a testcase that would have found the bug in r263971.Rafael Espindola2016-03-212-0/+12
| | | | llvm-svn: 263988
* Revert "[llvm-objdump] Printing relocations in executable and shared object ↵Rafael Espindola2016-03-213-9/+5
| | | | | | | | | files. This partially reverts r215844 by removing test objdump-reloc-shared.test which stated GNU objdump doesn't print relocations, it does." This reverts commit r263971. It produces the wrong results for .rela.dyn. I will add a test. llvm-svn: 263987
* Unxfail test/DebugInfo/Generic/multiline.ll on HexagonKrzysztof Parzyszek2016-03-211-3/+2
| | | | llvm-svn: 263986
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-0/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Whole quad mode is already enabled for pixel shaders that compute derivatives, but it must be suspended for instructions that cause a shader to have side effects (i.e. stores and atomics). This pass addresses the issue by storing the real (initial) live mask in a register, masking EXEC before instructions that require exact execution and (re-)enabling WQM where required. This pass is run before register coalescing so that we can use machine SSA for analysis. The changes in this patch expose a problem with the second machine scheduling pass: target independent instructions like COPY implicitly use EXEC when they operate on VGPRs, but this fact is not encoded in the MIR. This can lead to miscompilation because instructions are moved past changes to EXEC. This patch fixes the problem by adding use-implicit operands to target independent instructions. Some general codegen passes are relaxed to work with such implicit use operands. Reviewers: arsenm, tstellarAMD, mareko Subscribers: MatzeB, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18162 llvm-svn: 263982
* [Hexagon] Add handling fixups and instruction relaxationKrzysztof Parzyszek2016-03-211-0/+25
| | | | llvm-svn: 263981
* [Hexagon] Properly encode registers in duplex instructionsKrzysztof Parzyszek2016-03-211-0/+10
| | | | llvm-svn: 263980
* [WebAssembly] Implement the eqz instructions.Dan Gohman2016-03-212-0/+22
| | | | llvm-svn: 263976
* [llvm-objdump] Printing relocations in executable and shared object files. ↵Colin LeMahieu2016-03-213-5/+9
| | | | | | | | | | This partially reverts r215844 by removing test objdump-reloc-shared.test which stated GNU objdump doesn't print relocations, it does. In executable and shared object ELF files, relocations in the file contain the final virtual address rather than section offset so this is adjusted to display section offset. Differential revision: http://reviews.llvm.org/D15965 llvm-svn: 263971
* AMDGPU/SI: Fix threshold calculation for branching when exec is zeroTom Stellard2016-03-211-0/+34
| | | | | | | | | | | | | | | | | | | Summary: When control flow is implemented using the exec mask, the compiler will insert branch instructions to skip over the masked section when exec is zero if the section contains more than a certain number of instructions. The previous code would only count instructions in successor blocks, and this patch modifies the code to start counting instructions in all blocks between the start and end of the branch. Reviewers: nhaehnle, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18282 llvm-svn: 263969
* AMDGPU: Remove SignBitIsZero for mubuf scratch offsetsMatt Arsenault2016-03-212-11/+8
| | | | | | | These instructions do not have the same negative base address problem that DS instructions do on SI. llvm-svn: 263964
* ARM: Better codegen for 64-bit compares.Peter Collingbourne2016-03-213-144/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces a custom lowering for ISD::SETCCE (introduced in r253572) that allows us to emit a short code sequence for 64-bit compares. Before: push {r7, lr} cmp r0, r2 mov.w r0, #0 mov.w r12, #0 it hs movhs r0, #1 cmp r1, r3 it ge movge.w r12, #1 it eq moveq r12, r0 cmp.w r12, #0 bne .LBB1_2 @ BB#1: @ %bb1 bl f pop {r7, pc} .LBB1_2: @ %bb2 bl g pop {r7, pc} After: push {r7, lr} subs r0, r0, r2 sbcs.w r0, r1, r3 bge .LBB1_2 @ BB#1: @ %bb1 bl f pop {r7, pc} .LBB1_2: @ %bb2 bl g pop {r7, pc} Saves around 80KB in Chromium's libchrome.so. Some notes on this patch: - I don't much like the ARMISD::BRCOND and ARMISD::CMOV combines I introduced (nothing else needs them). However, they are necessary in order to avoid poor codegen, and they seem similar to existing combines in other backends (e.g. X86 combines (brcond (cmp (setcc Compare))) to (brcond Compare)). - No support for Thumb-1. This is in principle possible, but we'd need to implement ARMISD::SUBE for Thumb-1. Differential Revision: http://reviews.llvm.org/D15256 llvm-svn: 263962
* [ARM] Add Cortex-A32 supportRenato Golin2016-03-211-0/+35
| | | | | | | | Adding Cortex-A32 as an available target in the ARM backend. Patch by Sam Parker. llvm-svn: 263956
* [llvm-readobj] Impl GNU style symbols printingHemant Kulkarni2016-03-212-0/+46
| | | | | | | | Implements "readelf -sW and readelf -DsW" Differential Revision: http://reviews.llvm.org/D18224 llvm-svn: 263952
* AMDGPU: Add frexp_mant intrinsicMatt Arsenault2016-03-211-0/+64
| | | | llvm-svn: 263948
* Implement constant folding for bitreverseMatt Arsenault2016-03-211-2/+87
| | | | llvm-svn: 263945
* [IndVars] Fix PR26974: make sure replaceCongruentIVs doesn't break LCSSASilviu Baranga2016-03-211-0/+60
| | | | | | | | | | | | | | | | | | | Summary: replaceCongruentIVs can break LCSSA when trying to replace IV increments since it tries to replace all uses of a phi node with another phi node while both of the phi nodes are not necessarily in the processed loop. This will cause an assert in IndVars. To fix this, we add a check to make sure that the replacement maintains LCSSA. Reviewers: sanjoy Subscribers: mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D18266 llvm-svn: 263941
* [DAGCombine] Catch the case where extract_vector_elt can cause an any_ext ↵Silviu Baranga2016-03-211-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | while processing AND SDNodes Summary: extract_vector_elt can cause an implicit any_ext if the types don't match. When processing the following pattern: (and (extract_vector_elt (load ([non_ext|any_ext|zero_ext] V))), c) DAGCombine was ignoring the possible extend, and sometimes removing the AND even though it was required to maintain some of the bits in the result to 0, resulting in a miscompile. This change fixes the issue by limiting the transformation only to cases where the extract_vector_elt doesn't perform the implicit extend. Reviewers: t.p.northover, jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18247 llvm-svn: 263935
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