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* ARM assembly parsing and encoding tests.Jim Grosbach2011-07-221-0/+83
| | | | | | | Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD and SMUADX. llvm-svn: 135810
* Fix test check!Bruno Cardoso Lopes2011-07-221-1/+1
| | | | llvm-svn: 135802
* Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes2011-07-221-0/+28
| | | | | | load folding logic llvm-svn: 135801
* ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.Jim Grosbach2011-07-221-0/+14
| | | | llvm-svn: 135800
* ARM assembly parsing and encoding tests.Jim Grosbach2011-07-221-1/+37
| | | | | | | Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX instructions. llvm-svn: 135798
* ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach2011-07-221-0/+14
| | | | | | Fix parsing of carry-setting variant SMLALS and add tests. llvm-svn: 135797
* ARM encoding and assembly parsing of SMLAD{X} instructions.Jim Grosbach2011-07-221-0/+13
| | | | | | Fix encoding of destination register. Add tests. llvm-svn: 135796
* ARM testcases for assembly parsing and encoding SMLA* instructions.Jim Grosbach2011-07-221-0/+21
| | | | llvm-svn: 135795
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-0/+26
| | | | | | too. Patch by Jeff Muizelaar. llvm-svn: 135789
* ARM assembly parsing and encoding for SMC instruction.Jim Grosbach2011-07-221-0/+9
| | | | llvm-svn: 135782
* ARM encoding and assembly parsing tests.Jim Grosbach2011-07-221-0/+47
| | | | | | Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16. llvm-svn: 135780
* ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2011-07-222-0/+26
| | | | | | | Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
* ARM assembly parsing and encoding tests for SEL instruction.Jim Grosbach2011-07-221-0/+10
| | | | llvm-svn: 135772
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-222-2/+2
| | | | | | | | | | | | | | | | and was actually very wrong, fix it and make it simpler. Also remove the ConcatVectors function, which is unused now. - Fix a introduction of useless nodes in r126664 and r126264. The VUNPCKL* should never be introduced cause we don't want duplicate nodes for 128 AVX and non-AVX modes, the actual instruction difference only exists during isel, but not for target specific DAG nodes. We only introduce V* target nodes when there is no 128-bit version already there. - Fix a fragile test and make it more useful. llvm-svn: 135729
* Although we already support this, add testcases for consistencyBruno Cardoso Lopes2011-07-221-0/+21
| | | | llvm-svn: 135728
* Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes2011-07-221-0/+26
| | | | | | vxorps + vinsertf128 pair of instructions llvm-svn: 135727
* Fix MergeInVectorType to check for vector types with the same allocDan Gohman2011-07-211-0/+27
| | | | | | | size but different element types, so that it filters out the cases that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827. llvm-svn: 135721
* ARM parsing and encoding tests for SBC instruction.Jim Grosbach2011-07-212-3/+53
| | | | llvm-svn: 135718
* ARM testcases for SADD/SASX parsing and encoding.Jim Grosbach2011-07-211-0/+23
| | | | llvm-svn: 135715
* ARM assembly parsing support for RSC instruction.Jim Grosbach2011-07-212-3/+52
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135713
* ARM assembly parsing support for RSB instruction.Jim Grosbach2011-07-212-3/+57
| | | | | | | Add two-operand instruction aliases. Add parsing and encoding tests for variants of the instruction. llvm-svn: 135712
* ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.Jim Grosbach2011-07-211-0/+28
| | | | llvm-svn: 135710
* ARM parsing and encodings tests for saturating arithmetic insns.Jim Grosbach2011-07-212-12/+60
| | | | llvm-svn: 135709
* ARM assembly parsing POP/PUSH mnemonics.Jim Grosbach2011-07-211-0/+29
| | | | | | | | Aliases for LDM/STM. The single-register versions should encode to LDR/STR with writeback, but we don't (yet) get that correct. Neither does Darwin's system assembler, though, so that's not a deal-breaker of a limitation. llvm-svn: 135702
* Add tests for ARM PKH assembly parsing.Jim Grosbach2011-07-212-0/+48
| | | | llvm-svn: 135696
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-211-1/+12
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 llvm-svn: 135663
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 llvm-svn: 135662
* LSR, correct fix for rdar://9786536. Silly casting bug.Andrew Trick2011-07-211-1/+1
| | | | llvm-svn: 135654
* LSR must sometimes sign-extend before generating double constants.Andrew Trick2011-07-211-1/+20
| | | | | | rdar://9786536 llvm-svn: 135650
* LSR crashes on an empty IVUsers list.Andrew Trick2011-07-211-0/+24
| | | | | | rdar://9786536 llvm-svn: 135644
* While emitting constant value, look through derived type and use underlying ↵Devang Patel2011-07-201-0/+61
| | | | | | basic type to determine size and signness of the constant value. llvm-svn: 135627
* Bring LICM into compliance with the new "Memory Model for Concurrent ↵Eli Friedman2011-07-201-0/+37
| | | | | | Operations" in LangRef. llvm-svn: 135625
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-201-2/+3
| | | | llvm-svn: 135607
* Add parsing/encoding tests for ARM ORR instruction.Jim Grosbach2011-07-202-6/+79
| | | | llvm-svn: 135602
* Consolidate ARM NOP encoding test.Jim Grosbach2011-07-202-11/+9
| | | | llvm-svn: 135600
* ARM parsing and encoding tests for MVNJim Grosbach2011-07-201-0/+57
| | | | llvm-svn: 135599
* ARM assembly parsing of MUL instruction.Jim Grosbach2011-07-201-0/+14
| | | | | | | Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. llvm-svn: 135596
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-201-0/+8
| | | | llvm-svn: 135595
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+1
| | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! llvm-svn: 135569
* indvars: Added getInsertPointForUses to find a valid place to truncate the IV.Andrew Trick2011-07-201-0/+39
| | | | llvm-svn: 135568
* New pointer rotate test.Eric Christopher2011-07-201-0/+11
| | | | llvm-svn: 135562
* indvars test case for r135558.Andrew Trick2011-07-201-0/+7
| | | | llvm-svn: 135559
* indvars -disable-iv-rewrite fix: derived GEP IVsAndrew Trick2011-07-201-6/+29
| | | | llvm-svn: 135558
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-191-0/+19
| | | | llvm-svn: 135537
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-191-1/+1
| | | | llvm-svn: 135535
* PR10386: Don't try to split an edge from an indirectbr.Eli Friedman2011-07-191-0/+52
| | | | llvm-svn: 135534
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-194-42/+67
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* ARM assembly parsing of MRS instruction.Jim Grosbach2011-07-192-3/+13
| | | | | | | Teach the parser to recognize the APSR and SPSR system register names. Add and update tests accordingly. llvm-svn: 135527
* ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach2011-07-191-0/+14
| | | | | | Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-191-16/+16
| | | | | | ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
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