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* [InstSimplify] add tests for FP uno/ord with nnan; NFCSanjay Patel2018-08-211-0/+424
| | | | | | | | | This is a slight modification of the tests from D50582; change half of the predicates to 'uno' so we have coverage for that side too. All of the positive tests can fold to a constant (true/false), so that should happen in instsimplify. llvm-svn: 340276
* NFC: Add loop vectorizer tests showing various control flow within loop that ↵Anna Thomas2018-08-211-0/+169
| | | | | | skip iterations llvm-svn: 340275
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-214-0/+76
| | | | | | | | | | | | | | | | | Summary: Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics only allowed float types for the data to be loaded or stored, which sometimes meant the frontend needed to generate a bitcast. In this, the new intrinsics copied the old buffer intrinsics. This commit extends the new intrinsics to allow int types as well. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50315 Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85 llvm-svn: 340270
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-2114-0/+1414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-2110-2/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-211-0/+58
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
* [X86] Add SSE2 sdiv combine testsSimon Pilgrim2018-08-211-651/+1452
| | | | llvm-svn: 340264
* [DAGCombiner] Reduce load widths of shifted masksSam Parker2018-08-212-39/+528
| | | | | | | | | | | During combining, ReduceLoadWdith is used to combine AND nodes that mask loads into narrow loads. This patch allows the mask to be a shifted constant. This results in a narrow load which is then left shifted to compensate for the new offset. Differential Revision: https://reviews.llvm.org/D50432 llvm-svn: 340261
* [TargetLowering] Add BuildSDiv support for division by one or negone.Simon Pilgrim2018-08-211-115/+92
| | | | | | This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1. llvm-svn: 340260
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-215-0/+896
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [LICM] Hoist guards with invariant conditionsMax Kazantsev2018-08-212-7/+8
| | | | | | | | | | This patch teaches LICM to hoist guards from the loop if they are guaranteed to execute and if there are no side effects that could prevent that. Differential Revision: https://reviews.llvm.org/D50501 Reviewed By: reames llvm-svn: 340256
* [RegisterCoalescer] Do not assert when trying to remat dead valuesBjorn Pettersson2018-08-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: RegisterCoalescer::reMaterializeTrivialDef used to assert that the input register was live in. But as shown by the new coalesce-dead-lanes.mir test case that seems to be a valid scenario. We now return false instead of the assert, simply avoiding to remat the dead def. Normally a COPY of an undef value is eliminated by eliminateUndefCopy(). Although we only do that when the destination isn't a physical register. So the situation above should be limited to the case when we copy an undef value to a physical register. Reviewers: kparzysz, wmi, tpr Reviewed By: kparzysz Subscribers: MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50842 llvm-svn: 340255
* [NFC] Add some LICM testsMax Kazantsev2018-08-211-0/+179
| | | | llvm-svn: 340254
* [IR Verifier] Do not allow bitcast of pointer to vector of pointers and vice ↵Serguei Katkov2018-08-214-0/+49
| | | | | | | | | | | | | | | | | | versa. LangRef for BitCast requires that "The bit sizes of value and the destination type, ty2, must be identical". Currently verifier allows BitCast of pointer to vector of pointers so that the sizes are different. This change fixes that. Reviewers: arsenm Reviewed By: arsenm Subscribers: llvm-commits, wdng Differential Revision: https://reviews.llvm.org/D50886 llvm-svn: 340249
* [AST] Mark invariant.starts as being readonlyPhilip Reames2018-08-211-5/+4
| | | | | | | | These intrinsics are modelled as writing for control flow purposes, but they don't actually write to any location. Marking these - as we did for guards - allows LICM to hoist loads out of loops containing invariant.starts. Differential Revision: https://reviews.llvm.org/D50861 llvm-svn: 340245
* [LICM] Add tests from D50786 [NFC]Philip Reames2018-08-212-0/+34
| | | | | | Exercise more use of volatiles to illustrate that nothing changes as we tweak how we detect them. llvm-svn: 340244
* [LICM][NFC] Add tests from D50730Philip Reames2018-08-211-0/+38
| | | | | | | Landing tests so corresponding change can show effects clearly. see D50730 [AST] Generalize argument specific aliasing llvm-svn: 340243
* [LICM] More tests for D50925 [NFC]Philip Reames2018-08-211-0/+238
| | | | | | This time, the corresponding cases where we can hoist (store-like) calls out of loops. llvm-svn: 340242
* Fix global_metadata_external_comdat.ll testReid Kleckner2018-08-211-2/+2
| | | | llvm-svn: 340240
* [MS Demangler] Demangle special operator 'dynamic initializer'.Zachary Turner2018-08-201-0/+6
| | | | | | | | | | | This is encoded as __E and should print something like "dynamic initializer for 'Foo'(void)" This also adds support for dynamic atexit destructor, which is basically identical but encoded as __F with slightly different description. llvm-svn: 340239
* [MS Demangler] Anonymous namespace hashes can be backreferenced.Zachary Turner2018-08-201-0/+3
| | | | | | | Previously we were not remembering the key values of anonymous namespaces, but we need to do this. llvm-svn: 340238
* [MS Demangler] Properly demangle anonymous namespaces.Zachary Turner2018-08-201-0/+2
| | | | llvm-svn: 340237
* [WebAssembly] Revert type of wake count in atomic.wake to i32Heejin Ahn2018-08-201-25/+25
| | | | | | | | | | | | | | Summary: We decided to revert this from i64 to i32 in Nov 28 CG meeting. Fixes PR38632. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D51010 llvm-svn: 340234
* [LICM][Tests] Add tests for store hoisting [NFC]Philip Reames2018-08-201-0/+230
| | | | | | https://reviews.llvm.org/D50925 will be rebased on top of this. llvm-svn: 340233
* Re-land r334313 "[asan] Instrument comdat globals on COFF targets"Reid Kleckner2018-08-202-0/+55
| | | | | | | | | | | | | | | | | | | If we can use comdats, then we can make it so that the global metadata is thrown away if the prevailing definition of the global was uninstrumented. I have only tested this on COFF targets, but in theory, there is no reason that we cannot also do this for ELF. This will allow us to re-enable string merging with ASan on Windows, reducing the binary size cost of ASan on Windows. I tested this change with ASan+PGO, and I fixed an issue with the __llvm_profile_raw_version symbol. With the old version of my patch, we would attempt to instrument that symbol on ELF because it had a comdat with external linkage. If we had been using the linker GC-friendly metadata scheme, everything would have worked, but clang does not enable it by default. llvm-svn: 340232
* [InstCombine] Add splat vector constant support to foldICmpAddOpConst.Craig Topper2018-08-201-6/+43
| | | | | | Differential Revision: https://reviews.llvm.org/D50946 llvm-svn: 340231
* extend binop folds for selects to include true and false binops flag ↵Michael Berg2018-08-201-2/+2
| | | | | | | | | | | | | | intersection Summary: This change address bug 38641 Reviewers: spatel, wristow Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D50996 llvm-svn: 340222
* [llvm-objdump] Add ability to demangle COFF symbols.Zachary Turner2018-08-201-7/+1
| | | | llvm-svn: 340221
* [X86] Add test command line to expose PR38649.Craig Topper2018-08-201-44/+105
| | | | | | Bypass slow division and constant hoisting are conspiring to break div+rem of large constants. llvm-svn: 340217
* [X86] Prevent lowerVectorShuffleByMerging128BitLanes from creating cyclesCraig Topper2018-08-201-0/+18
| | | | | | | | | | | | Due to some splat handling code in getVectorShuffle, its possible for NewV1/NewV2 to have their mask modified from what is requested. This can lead to cycles being created in the DAG. This patch examines the returned mask and makes sure its different. Long term we may need to look closer at that splat code in getVectorShuffle, or add more splat awareness to getVectorShuffle. Fixes PR38639 Differential Revision: https://reviews.llvm.org/D50981 llvm-svn: 340214
* [X86] Teach combineTruncatedArithmetic to handle some cases of ISD::SUBCraig Topper2018-08-201-201/+17
| | | | | | | | We can safely avoid interfering with the subus combine if both inputs are freely truncatable. Either both extends, or an extend and a constant vector. Differential Revision: https://reviews.llvm.org/D50878 llvm-svn: 340212
* [X86] Pre-commit test cases for D50878.Craig Topper2018-08-201-0/+236
| | | | llvm-svn: 340211
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-203-2/+53
| | | | | | | | | | | | 1. Change the software pipeliner to use unknown size instead of dropping memory operands. It used to do it before, but MachineInstr::mayAlias did not handle it correctly. 2. Recognize UnknownSize in MachineInstr::mayAlias. 3. Print and parse UnknownSize in MIR. Differential Revision: https://reviews.llvm.org/D50339 llvm-svn: 340208
* Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space"Vitaly Buka2018-08-201-6/+0
| | | | | | | | As it introduces out of bound access. This reverts commit r340172 and r340171 llvm-svn: 340202
* [FPEnv] Support constrained FREM intrinsicCameron McInally2018-08-202-14/+288
| | | | | | Differential Revision: https://reviews.llvm.org/D50975 llvm-svn: 340201
* [MS Demangler] Demangle member pointer template parameters.Zachary Turner2018-08-202-0/+126
| | | | llvm-svn: 340199
* Revert "Revert r339977: [GISel]: Add Opcodes for a few LLVM Intrinsics"Aditya Nandakumar2018-08-202-0/+26
| | | | | | | | | | This reverts commit 7debc334e6421bb5251ef8f18e97166dfc7dd787. I missed updating legalizer-info-validation.mir as I had assertions turned off in my build and that specific test requires asserts. Fixed it now. llvm-svn: 340197
* [TargetLowering] Disable BuildSDiv division by one or negone.Simon Pilgrim2018-08-201-80/+116
| | | | | | Fuzz tests have detected an issue, currently working on a fix. llvm-svn: 340195
* [ConstantFolding] improve folding of binops with vector undef operandSanjay Patel2018-08-201-8/+8
| | | | | | | A non-undef operand may still have undef constant elements, so we should always propagate the vector results per-lane. llvm-svn: 340194
* [ConstantFolding] add tests for binops on vectors with undef elements; NFCSanjay Patel2018-08-201-0/+61
| | | | llvm-svn: 340190
* ValueTracking: Handle more instructions in isKnownNeverNaNMatt Arsenault2018-08-201-41/+10
| | | | llvm-svn: 340187
* [InstCombine] add tests for insertelement+binop; NFCSanjay Patel2018-08-201-0/+635
| | | | llvm-svn: 340184
* AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr spaceSamuel Pitoiset2018-08-201-0/+6
| | | | | | | | | | | | | | 32-bit constant address space is declared as 6, so the maximum number of address spaces is 6, not 5. Fixes "LLVM ERROR: Pointer address space out of range". v3: use static_assert() v2: add a very simple test for 32-bit addr space Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106630 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> llvm-svn: 340171
* [SelectionDAG] Add partial sign-bit support to ComputeNumSignBits for ↵Simon Pilgrim2018-08-201-22/+14
| | | | | | | | | | BITCAST nodes Only adds support to the existing 'large element' scalar/vector to 'small element' vector bitcasts. Handle the case where the sign bit extends to only part of the small elements. llvm-svn: 340169
* [X86][SSE] Fix PACKSS bitcast test from rL340166Simon Pilgrim2018-08-201-7/+7
| | | | | | We need the signbits to extends to lower 16-bits of the even elements llvm-svn: 340167
* [X86][SSE] Add PACKSS test showing ComputeNumSignBits failure to handle a ↵Simon Pilgrim2018-08-201-0/+57
| | | | | | partial sign bits extension through a bitcast llvm-svn: 340166
* [X86] Drop unnecessary exact qualifier from packss testSimon Pilgrim2018-08-201-1/+1
| | | | llvm-svn: 340165
* [AArch64][SVE] Asm: Add SVE System registersSander de Smalen2018-08-202-0/+113
| | | | | | | | | | | | | | | | | | This patch adds system registers for controlling aspects of SVE: - ZCR_EL1 (r/w) visible at EL1 and EL0. - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0. - ZCR_EL3 (r/w) visible at all exception levels. and a system register identifying SVE: - ID_AA64ZFR0_EL1 (r) SVE Feature identifier. Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D50885 llvm-svn: 340158
* [PowerPC] Add a peephole post RA to transform the inst that fed by addQingShan Zhang2018-08-2018-107/+109
| | | | | | | | | | | | | If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 llvm-svn: 340149
* [InstCombine] Add test cases for an icmp combine that is missing support for ↵Craig Topper2018-08-191-0/+51
| | | | | | splat vector constants. llvm-svn: 340144
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