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* [ARM] FP16 vmaxnm/vminnm scalar instructionsSjoerd Meijer2018-04-133-1/+790
| | | | | | | | | This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
* [llvm-mca] Ensure that instructions with a schedule read-advance are always ↵Andrea Di Biagio2018-04-131-0/+44
| | | | | | | | | | | | | | issued in the right order. Normally, the Scheduler prioritizes older instructions over younger instructions during the instruction issue stage. In one particular case where a dependent instruction had a schedule read-advance associated to one of the input operands, this rule was not correctly applied. This patch fixes the issue and adds a test to verify that we don't regress that particular case. llvm-svn: 330032
* [ARC] Add LImm support for J/JLYan Luo2018-04-131-0/+6
| | | | llvm-svn: 330031
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructionsSander de Smalen2018-04-1314-0/+911
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45618 llvm-svn: 330024
* [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not ↵Simon Pilgrim2018-04-131-192/+192
| | | | | | WriteFAdd llvm-svn: 330023
* [PostRASink]Add register dependency check for implicit operandsJun Bum Lim2018-04-131-0/+63
| | | | | | | | | | | | | | | | Summary: This change extend the register dependency check for implicit operands in Copy instructions. Fixes PR36902. Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB Reviewed By: thegameg Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44958 llvm-svn: 330018
* [InstCombine][NFC] Regenerate logical-select.ll testRoman Lebedev2018-04-131-90/+90
| | | | llvm-svn: 330017
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.Sander de Smalen2018-04-138-0/+526
| | | | | | | | | | | | | | | | | | | | Summary: Added instructions for contiguous stores, ST1, with scalar+imm addressing modes and corresponding tests. The patch also adds parsing of 'mul vl' as needed for the VL-scaled immediate. This is patch [6/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45432 llvm-svn: 330014
* [NEON] Support intrinsic for scalar and vector versions of the VRINTN ↵Ivan A. Kosarev2018-04-131-0/+11
| | | | | | | | instruction Differential Revision: https://reviews.llvm.org/D45514 llvm-svn: 330011
* [InstCombine][NFC] Add last few tests with constant mask for masked merge ↵Roman Lebedev2018-04-131-4/+69
| | | | | | | | | folding. A followup for rL330003 https://bugs.llvm.org/show_bug.cgi?id=6773 llvm-svn: 330007
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-132-2/+2
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [InstCombine][NFC] Add tests for masked merge folding.Roman Lebedev2018-04-131-0/+570
| | | | | | | | | | | | https://bugs.llvm.org/show_bug.cgi?id=6773 As discussed there, some backends may want to undo this fold (x86+bmi for scalars, x86+sse for vectors, ...) https://bugs.llvm.org/show_bug.cgi?id=37104 https://rise4fun.com/Alive/JXt llvm-svn: 330003
* [InstCombine]: foldSelectICmpAndAnd(): and is commutativeRoman Lebedev2018-04-131-14/+13
| | | | | | | | | | | | | | | | | | | | | Summary: The fold added in D45108 did not account for the fact that the and instruction is commutative, and if the mask is a variable, the mask variable and the fold variable may be swapped. I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] This extends/generalizes that fold, so it is handled too. Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45539 llvm-svn: 330001
* [X86] Introduce cldemote instructionGabor Buella2018-04-135-0/+48
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.Craig Topper2018-04-1312-1664/+2610
| | | | | | | | This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics. We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well. llvm-svn: 329990
* Enable debug fission for thinLTO linked via gold-pluginYunlian Jiang2018-04-132-0/+64
| | | | | | | | | | | | | | Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user. Reviewers: tejohnson, pcc, dblaikie Reviewed By: pcc Subscribers: JDevlieghere, mehdi_amini, inglorion Differential Revision: https://reviews.llvm.org/D44792 llvm-svn: 329988
* [PowerPC] add fsub-fneg test; NFCSanjay Patel2018-04-121-0/+21
| | | | | | | | | This is a test for a transform that was suggested in the post-commit mailing list thread for rL329821. The target in question is not in trunk, so PPC gets to stand in for it because it's the only in-tree target that sets 'isFPExtFree()' to 'true'. llvm-svn: 329963
* Let llvm-diff correctly deal with ↵Brian Gesiak2018-04-124-0/+49
| | | | | | | | | | | | | | | | | | | | | | Undef/ConstantAggregateZero/ConstantVector/IndirectBr Summary: llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr. (This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`) This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 . Reviewers: dexonsmith, rjmccall Reviewed By: rjmccall Subscribers: chenwj, mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D34856 llvm-svn: 329957
* AArch64: Introduce a DAG combine for folding offsets into addresses.Peter Collingbourne2018-04-126-68/+172
| | | | | | | | | | | This is a code size win in code that takes offseted addresses frequently, such as C++ constructors that typically need to compute an offseted address of a vtable. This reduces the size of Chromium for Android's .text section by 108KB. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 329956
* [DebugInfo] Create merged locations for instructions other than callsVedant Kumar2018-04-125-30/+36
| | | | | | | | | | | | | | | | | | This lifts a restriction on DILocation::getMergedLocation(), allowing it to create merged locations for instructions other than calls. Instruction::applyMergedLocation() now defaults to creating merged locations for all instructions. The default behavior of getMergedLocation() is unchanged: callers which invoke it directly are unaffected. This change will enable a follow-up Mem2Reg fix which improves crash reporting. Differential Revision: https://reviews.llvm.org/D45396 llvm-svn: 329955
* [WebAssembly] libObject: Don't include the name the size of custom sectionsSam Clegg2018-04-124-8/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D45579 llvm-svn: 329947
* [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal2018-04-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC compresses the pseudo instruction "mv rd, rs", which is an alias of "addi rd, rs, 0", to "c.mv rd, rs". In LLVM we rely on the canonical MC instruction (MCInst) to do our compression checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv rd, rs" we lose this compression opportunity to gcc. In this patch we fix that by adding an addi to c.mv compression pattern, the instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like gcc does. Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal). Reviewers: asb, apazos, zzheng, mgrang, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits Differential Revision: https://reviews.llvm.org/D45583 llvm-svn: 329939
* [X86] Introduce LLVM wbinvd intrinsicGabor Buella2018-04-121-0/+19
| | | | | | | | | | | | A previously missing intrinsic for an old instruction. Reviewers: craig.topper, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45312 llvm-svn: 329936
* [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-PrecisionLei Huang2018-04-121-0/+140
| | | | | | | | | | | Legalize and emit code for: * xscvsdqp * xscvudqp Differential Revision: https://reviews.llvm.org/D45230 llvm-svn: 329931
* [AArch64] Move AFI->setRedZone(false) to top of emitPrologueJessica Paquette2018-04-121-5/+35
| | | | | | | | | | | | | AFI->setRedZone(false) was put in the wrong place before, and so it only fired on functions that didn't have stack frames. This moves that to the top of emitPrologue to make sure that every function without a redzone has it set correctly. This also adds a function representing one of the early exit cases (GHC calling convention) to the MachineOutliner noredzone test to ensure that we can outline from functions like these, where we never use a redzone. llvm-svn: 329922
* revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-04-128-83/+330
| | | | | | | This change is exposing UB in source code - as was warned/predicted. :) See D44909 for discussion. Reverting while we figure out how to fix things. llvm-svn: 329920
* [mips] Correct the predicates of the load/store (double)word for coprocessor 3.Simon Dardis2018-04-123-0/+12
| | | | llvm-svn: 329913
* [IRCE] isKnownNonNegative helper functionSam Parker2018-04-121-1/+1
| | | | | | | | | | Created a helper function to query for non negative SCEVs. Uses the SGE predicate to catch constants that could be interpreted as negative. Differential Revision: https://reviews.llvm.org/D45481 llvm-svn: 329907
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-1233-8/+220
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* [InstCombine][NFC]: Add tests: foldSelectICmpAndAnd(): and is commutativeRoman Lebedev2018-04-121-0/+52
| | | | | | | | | | | | | | | | | | | Summary: The fold added in D45108 did not account for the fact that the and instruction is commutative, and if the mask is a variable, the mask variable and the fold variable may be swapped. I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45538 llvm-svn: 329901
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-0/+13
| | | | | | | | | | | | | | | | | | Summary: According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but instruction allow to be aligned to 16-bit boundaries for C-extension. So we just align to 4 bytes and 2 bytes for C-extension is enough. Reviewers: asb, apazos Differential Revision: https://reviews.llvm.org/D45560 Patch by Kito Cheng. llvm-svn: 329899
* [MIPS GlobalISel] minor update to MIR tests added in r329819Petar Jovanovic2018-04-123-12/+0
| | | | | | | | Remove 'registers' section, as suggested (D. Sanders) at code review https://reviews.llvm.org/D44304 llvm-svn: 329888
* [NFC] fix trivial typos in documents and commentsHiroshi Inoue2018-04-122-2/+2
| | | | | | "is is" -> "is", "if if" -> "if", "or or" -> "or" llvm-svn: 329878
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-124-0/+1327
| | | | | | | | Also add double-prevoius-failure.ll which captures a test case that at one point triggered a compiler crash, while developing calling convention support for f64 on RV32D with soft-float ABI. llvm-svn: 329877
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-122-0/+106
| | | | | | | This also includes support and a test for truncating stores, which are now possible thanks to the fpround pattern. llvm-svn: 329876
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-121-0/+256
| | | | llvm-svn: 329874
* [RISCV] Add tests missed in r329871Alex Bradbury2018-04-126-0/+464
| | | | llvm-svn: 329872
* [DeadArgElim] Remove allocsize attributes on callsitesGeorge Burgess IV2018-04-121-0/+5
| | | | | | | | | | | | | | | We're already removing allocsize attributes from Functions that we remove args from, since removing arguments from a function may make the allocsize attribute incorrect. It appears we forgot to also remove them from callsites. Without this, I get verifier errors on `@Test2`. It probably wouldn't be too hard to make DAE properly update allocsize attributes instead of dropping them, but I can't think of a scenario where that'd be useful in practice. llvm-svn: 329868
* Revert "[llvm-objcopy] Switch over to using TableGen for parsing arguments"Jake Ehrlich2018-04-128-8/+8
| | | | | | | | TableGen seems to work differently on windows. I'll need to revert this This reverts commit 7a153ddea067b24da59f6a66c733d79205969501. llvm-svn: 329867
* [llvm-objcopy] Switch over to using TableGen for parsing argumentsJake Ehrlich2018-04-118-8/+8
| | | | | | | | | Swithces from using the command line library to using TableGen. This will allow llvm-strip to exist and allow refinements of the command line syntax. Differential Revision: https://reviews.llvm.org/D44236 llvm-svn: 329863
* [PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+iNemanja Ivanovic2018-04-111-0/+64
| | | | | | | | | | This patch fixes https://bugs.llvm.org/show_bug.cgi?id=37039 The condition only covers one of the two 64-bit rotate instructions. This just adds the second (RLDICLo). Patch by Josh Stone. llvm-svn: 329852
* Attempting to work around a non-determinism issue.Puyan Lotfi2018-04-111-2/+0
| | | | | | | The main thing that matters with this test is that the COPYs are moved together not where the REG_SEQUENCES are. llvm-svn: 329850
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-117-0/+39
| | | | | | | | | | | | | | | Similar to the wbinvd instruction, except this one does not invalidate caches. Ring 0 only. The encoding matches a wbinvd instruction with an F3 prefix. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43816 llvm-svn: 329847
* [DSE] Add tests for atomic memory intrinsics (NFC)Daniel Neilson2018-04-114-0/+705
| | | | | | | | Summary: These tests show that DSE currently does nothing with the atomic memory intrinsics. Future work will teach DSE how to simplify these. llvm-svn: 329845
* [DSE] Regenerate tests with update_test_checks.py (NFC)Daniel Neilson2018-04-112-24/+135
| | | | | | | | | Summary: In preparation for a future commit, this regenerates the test checks for test/Transforms/DeadStoreElimination/OverwriteStoreBegin.ll test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll llvm-svn: 329839
* CodeGen: Don't try to canonicalize Unix-style paths in CodeView debug info.Peter Collingbourne2018-04-113-8/+8
| | | | | | | | | Most importantly, we should not replace slashes with backslashes because that would invalidate the path. Differential Revision: https://reviews.llvm.org/D45473 llvm-svn: 329838
* [X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)Simon Pilgrim2018-04-1111-159/+172
| | | | | | | | | | | | | | | | Atom is the only x86 target that still uses schedule itineraries, if we can remove this then we can begin the work on removing x86 itineraries. I've also found that it will help with PR36550. I've focussed on matching the existing model as closely as possible (relying on the schedule tests), PR36895 indicated a lot of these were incorrect but we can just as easily fix these after this patch as before. Hopefully we can get llvm-exegesis to help here, There are a few instructions that rely on itinerary scheduling (mainly push/pop/return) of multiple resource stages, but I don't think any of these are show stoppers. There are also a few codegen changes that seem related to the post-ra scheduler acting a little differently, I haven't tracked these down but they don't seem critical. NOTE: I don't have access to any Atom hardware, so this hasn't been tested in the wild. Differential Revision: https://reviews.llvm.org/D45486 llvm-svn: 329837
* [NVPTX] Removed 'satom' feature which is no longer used.Artem Belevich2018-04-111-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D45061 llvm-svn: 329830
* [AMDGPU] Ensure there are enough registers for wave dispatchTim Renouf2018-04-111-0/+18
| | | | | | | | | | | | | | | | | Summary: This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to allow for registers set up in wave dispatch, even if those registers are not used in the shader. Re-landed after noticing that the buildbot failure from 329808 seemed to be unrelated. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45503 Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771 llvm-svn: 329826
* [DSE] Regenerate tests with update_test_checks.py (NFC)Daniel Neilson2018-04-112-175/+308
| | | | | | | | | Summary: In preparation for a future commit, this regenerates the test checks for test/Transforms/DeadStoreElimination/simple.ll test/Transforms/DeadStoreElimination/memintrinsics.ll llvm-svn: 329824
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