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* Revert "[Assembler] Enable nicer diagnostics for inline assembly."Diana Picus2017-02-081-9/+0
| | | | | | This reverts commit r294433 because it seems it broke the buildbots. llvm-svn: 294448
* Revert r294356, "DebugInfo: Track spilled variables in LiveDebugValues"NAKAMURA Takumi2017-02-081-468/+0
| | | | | | | | | | | | | | It caused undefined behavior in VarLoc. As far as I investigated, - VarLoc::VarLoc() treats negative offset value as InvalidKind. Consider the case that (int64_t)MI.getOperand(1).getImm() is negative and whether it satisfies ((uint64_t)Offset < (1ULL << 32)). - Comparison operators in VarLoc behave undefined since VarLoc::Loc.Hash is uninitialized in case of InvalidKind. I guess Offset (in VarLoc) could be made aware of signed, but I am not sure. So I have reverted it for now. llvm-svn: 294447
* Move test from r294430 to target-specific directoryDiana Picus2017-02-082-0/+0
| | | | | | | The test is X86-specific, and it broke on the ARM bots because they don't build the X86 target. llvm-svn: 294446
* [ARM] GlobalISel: Add FPR reg bankDiana Picus2017-02-083-0/+92
| | | | | | | | | | | | | Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-0822-230/+230
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* [AVR] XFAIL a set of failing CodeGen testsDylan McKay2017-02-0810-0/+33
| | | | | | | | | There are about 3 underlying bugs causing the tests to fail. On top of that, some tests just we're 'generic' enough. i.e. 32-bit registers. llvm-svn: 294434
* [Assembler] Enable nicer diagnostics for inline assembly.Sanne Wouda2017-02-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Enables source location in diagnostic messages from the backend. This is after parsing, during finalization. This requires the SourceMgr, the inline assembly string buffer, and DiagInfo to still be alive after EmitInlineAsm returns. This patch creates a single SourceMgr for inline assembly inside the AsmPrinter. MCContext gets a pointer to this SourceMgr. Using one SourceMgr per call to EmitInlineAsm would make it difficult for MCContext to figure out in which SourceMgr the SMLoc is located, while a single SourceMgr can figure it out if it has multiple buffers. The Str argument to EmitInlineAsm is copied into a buffer and owned by the inline asm SourceMgr. This ensures that DiagHandlers won't print garbage. (Clang emits a "note: instantiated into assembly here", which refers to this string.) The AsmParser gets destroyed before finalization, which means that the DiagHandlers the AsmParser installs into the SourceMgr will be stale. Restore the saved DiagHandlers. Since now we're using just one SourceMgr for multiple inline asm strings, we need to tell the AsmParser which buffer it needs to parse currently. Hand a buffer id -- returned from SourceMgr:: AddNewSourceBuffer -- to the AsmParser. Reviewers: rnk, grosbach, compnerd, rengolin, rovka, anemet Reviewed By: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29441 llvm-svn: 294433
* Use dynamic symbols for ELF disassemblySam Parker2017-02-082-0/+10
| | | | | | | | | | | Disassembly currently begins from addresses obtained from the objects symbol table. For ELF, add the dynamic symbols to the list if no static symbols are available so that we can more successfully disassemble stripped binaries. Differential Revision: https://reviews.llvm.org/D29632 llvm-svn: 294430
* [ArgPromote] Delete a test that makes no sense (any more).Chandler Carruth2017-02-081-23/+0
| | | | | | | | | This test is under 'ArgumentPromotion' but there are no arguments that get promoted in the test case, so there seems to be no point. Also, there are no assertions about the output at all, so this seems like something we should just delete given the low value. llvm-svn: 294428
* [ArgPromote] Clean up a crash test case by rinsing it through opt,Chandler Carruth2017-02-081-35/+46
| | | | | | | | | | | renaming things to at least have somewhat spelled out names, and even have meaningful names where I could guess at what they should be. Also add FileCheck assertions that we're actually doing what we set out to do for some of the tests, for example not promoting a type that would result in infinite promotion. llvm-svn: 294426
* [ArgPromote] Actually add FileCheck to a test that I actually updated toChandler Carruth2017-02-081-2/+1
| | | | | | | have nice CHECK patterns instead of relying on a coarse 'not grep' check. Sorry that I missed this the first time through. llvm-svn: 294422
* [ArgPromote] Actually run FileCheck on this test. The CHECK lines areChandler Carruth2017-02-081-1/+1
| | | | | | already there, just waiting to, well, be checked. =] llvm-svn: 294421
* LSR: Check atomic instruction pointer operandsMatt Arsenault2017-02-081-0/+87
| | | | llvm-svn: 294410
* AMDGPU: Enable InferAddressSpacesMatt Arsenault2017-02-082-22/+22
| | | | llvm-svn: 294408
* [X86] Add test for clflushopt intrinsic and only enable it to be selected if ↵Craig Topper2017-02-081-0/+13
| | | | | | the feature flag is set. llvm-svn: 294407
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-083-9/+2
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* [DAGCombiner] Push truncate through adde when the carry isn't used.Amaury Sechet2017-02-082-9/+5
| | | | | | | | | | | | Summary: As per title. Reviewers: mkuper, spatel, bkramer, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29528 llvm-svn: 294394
* [IRCE] Add a missing invariant checkSanjoy Das2017-02-071-0/+45
| | | | | | | | | | | | | | | | | | | | | | | Currently IRCE relies on the loops it transforms to be (semantically) of the form: for (i = START; i < END; i++) ... or for (i = START; i > END; i--) ... However, we were not verifying the presence of the START < END entry check (i.e. check before the first iteration). We were only verifying that the backedge was guarded by (i + 1) < END. Usually this would work "fine" since (especially in Java) most loops do actually have the START < END check, but of course that is not guaranteed. llvm-svn: 294375
* [X86][SSE] Add SSE2 build vector insertion testsSimon Pilgrim2017-02-071-105/+285
| | | | llvm-svn: 294365
* [X86][SSE] Add additional v4i32/v8i16/v16i8 build vector insertion testsSimon Pilgrim2017-02-071-0/+272
| | | | | | With particular interest in cases where we don't make use of implicit zeroing or fail to break register dependencies llvm-svn: 294363
* DebugInfo: Track spilled variables in LiveDebugValuesWolfgang Pieb2017-02-071-0/+468
| | | | | | | | | | | | | When variables are spilled to the stack by the register allocator, keep track of their debug locations in LiveDebugValues and insert DBG_VALUE instructions at the appropriate place. Ensure that the locations are propagated down the dominator tree via the existing mechanisms. Reviewer: aprantl Differential Revision: https://reviews.llvm.org/D29500 llvm-svn: 294356
* Fix a typo in an error message for a check of invalid Mach-O files whereKevin Enderby2017-02-071-1/+1
| | | | | | | | | | | | it was printing the field name fileoff instead of filesize. The original check was added in r278557. This was found in tracking down the problem that lead to the fix in r293842 - [dsymutil] Fix __LINKEDIT vmsize in dsymutil upgrade path rdar://30386075 llvm-svn: 294354
* Add PredicateInfo utility and printing passDaniel Berlin2017-02-072-0/+668
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds a utility to build extended SSA (see "ABCD: eliminating array bounds checks on demand"), and an intrinsic to support it. This is then used to get functionality equivalent to propagateEquality in GVN, in NewGVN (without having to replace instructions as we go). It would work similarly in SCCP or other passes. This has been talked about a few times, so i built a real implementation and tried to productionize it. Copies are inserted for operands used in assumes and conditional branches that are based on comparisons (see below for more) Every use affected by the predicate is renamed to the appropriate intrinsic result. E.g. %cmp = icmp eq i32 %x, 50 br i1 %cmp, label %true, label %false true: ret i32 %x false: ret i32 1 will become %cmp = icmp eq i32, %x, 50 br i1 %cmp, label %true, label %false true: ; Has predicate info ; branch predicate info { TrueEdge: 1 Comparison: %cmp = icmp eq i32 %x, 50 } %x.0 = call @llvm.ssa_copy.i32(i32 %x) ret i32 %x.0 false: ret i23 1 (you can use -print-predicateinfo to get an annotated-with-predicateinfo dump) This enables us to easily determine what operations are affected by a given predicate, and how operations affected by a chain of predicates. Reviewers: davide, sanjoy Subscribers: mgorny, llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D29519 Update for review comments Fix a bug Nuno noticed where we are giving information about and/or on edges where the info is not useful and easy to use wrong Update for review comments llvm-svn: 294351
* [X86] Disable conditional tail calls (PR31257)Hans Wennborg2017-02-073-140/+4
| | | | | | | | | They are currently modelled incorrectly (as calls, which clobber registers, confusing e.g. Machine Copy Propagation). Reverting until we figure out the proper solution. llvm-svn: 294348
* GlobalISel: translate @llvm.va_end intrinsic.Tim Northover2017-02-071-0/+10
| | | | | | | Turns out no-one actually cares about this one (at least) in tree so we can just drop it entirely. llvm-svn: 294345
* [LV] Add new ARM/AArch64 interleaved access cost model tests (NFC)Matthew Simpson2017-02-072-0/+153
| | | | llvm-svn: 294342
* [ImplicitNullCheck] Extend Implicit Null Check scope by using storesSanjoy Das2017-02-073-14/+689
| | | | | | | | | | | | | | | | | | | | | Summary: This change allows usage of store instruction for implicit null check. Memory Aliasing Analisys is not used and change conservatively supposes that any store and load may access the same memory. As a result re-ordering of store-store, store-load and load-store is prohibited. Patch by Serguei Katkov! Reviewers: reames, sanjoy Reviewed By: sanjoy Subscribers: atrick, llvm-commits Differential Revision: https://reviews.llvm.org/D29400 llvm-svn: 294338
* [LV] Simplify ARM/AArch64 interleaved access cost model tests (NFC)Matthew Simpson2017-02-072-89/+76
| | | | | | | | This patch removes unneeded instructions from the existing ARM/AArch64 interleaved access cost model tests. I'll be adding a similar set of tests in a follow-on patch to increase coverage. llvm-svn: 294336
* [PowerPC][Altivec] Add vnot extended mnemonicNemanja Ivanovic2017-02-072-20/+23
| | | | | | | | | | Adds the vnot extended mnemonic for the vnor instruction. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29225 llvm-svn: 294330
* [AMDGPU] Fix for SIMachineScheduler crash. SI Scheduler should trackAlexander Timofeev2017-02-071-0/+49
| | | | | | | | lane masks. Differential revision: https://reviews.llvm.org/D29442 llvm-svn: 294324
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-073-4/+176
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* Fix my GVNHoist test case from r294317Reid Kleckner2017-02-071-3/+4
| | | | llvm-svn: 294319
* Fix the bitcode upgrade for DIGlobalVariable in a DIImportedEntity context.Adrian Prantl2017-02-073-12/+16
| | | | | | | | | | | | | | | The bitcode upgrade for DIGlobalVariable unconditionally wrapped DIGlobalVariables in a DIGlobalVariableExpression. When a DIGlobalVariable is referenced by a DIImportedEntity, however, this is wrong. This patch fixes the bitcode upgrade by deferring the creation of DIGlobalVariableExpressions until we know the context of the DIGlobalVariable. <rdar://problem/30134279> Differential Revision: https://reviews.llvm.org/D29349 llvm-svn: 294318
* Revert "[GVNHoist] Merge DebugLoc metadata on hoisted instructions"Reid Kleckner2017-02-072-69/+82
| | | | | | | | | This reverts commit r294250. It caused PR31891. Add a test case that shows that inlinable calls retain location information with an accurate scope. llvm-svn: 294317
* Add DAGCombiner load combine tests for {a|s}ext, {a|z|s}ext load nodesArtur Pilipenko2017-02-075-4/+786
| | | | | | | | Currently we don't support these nodes, so the tests check the current codegen without load combine. This change makes the review of the change to support these nodes more clear. Separated from https://reviews.llvm.org/D29591 review. llvm-svn: 294305
* [X86][SSE] Generalized integer absolute tests to test canonical pattern as ↵Simon Pilgrim2017-02-071-6/+31
| | | | | | well as intrinsics llvm-svn: 294300
* [ARM] Make RWPI use movw/movt when availableChristof Douma2017-02-071-19/+125
| | | | | | | | | | | | | | | | | When constructing global address literals while targeting the RWPI relocation model. LLVM currently only uses literal pools. If MOVW/MOVT instructions are available we can use these instead. Beside being more efficient it allows -arm-execute-only to work with -relocation-model=RWPI as well. When we generate MOVW/MOVT for global addresses when targeting the RWPI relocation model, we need to use base relative relocations. This patch does the needed plumbing in MC to generate these for MOVW/MOVT. Differential Revision: https://reviews.llvm.org/D29487 Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d llvm-svn: 294298
* [X86][SSE] Added 256-bit vector tests casesSimon Pilgrim2017-02-071-0/+1151
| | | | | | Exposes some poor codegen with identity shuffle due to bad interaction with insert_subvector(extract_subvector) / concat_subvectors llvm-svn: 294296
* Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"Daniel Jasper2017-02-071-6/+7
| | | | | | | | | | | | | This reverts commit r294186. On an internal test, this triggers an out-of-memory error on PPC, presumably because there is another dagcombine that does the exact opposite triggering and endless loop consuming more and more memory. Chandler has started at creating a reduced test case and we'll attach it as soon as possible. llvm-svn: 294288
* [AVX-512] Add masked and unmasked shift by immediate instructions to load ↵Craig Topper2017-02-071-0/+102
| | | | | | folding tables. llvm-svn: 294287
* [AVX-512] Add masked shift instructions to load folding tables.Craig Topper2017-02-071-0/+42
| | | | | | This adds the masked versions of everything, but the shift by immediate instructions. llvm-svn: 294286
* [AVX-512] Add some of the shift instructions to the load folding tables.Craig Topper2017-02-072-0/+486
| | | | | | | | This includes unmasked forms of variable shift and shifting by the lower element of a register. Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms. llvm-svn: 294285
* [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including ↵Craig Topper2017-02-071-14/+28
| | | | | | YMM16-31. llvm-svn: 294277
* [AVX-512] Put the integer stack folding tests in alphabetical order.Craig Topper2017-02-072-1253/+1237
| | | | llvm-svn: 294276
* RegisterCoalescer: Fix joinReservedPhysReg()Matthias Braun2017-02-071-20/+75
| | | | | | | | | | | joinReservedPhysReg() can only deal with a liverange in a single basic block when copying from a vreg into a physreg. See also rdar://30306405 Differential Revision: https://reviews.llvm.org/D29436 llvm-svn: 294268
* [AMDGPU] Lower null pointers in static variable initializerYaxun Liu2017-02-071-0/+113
| | | | | | | | | | | | For amdgcn target Clang generates addrspacecast to represent null pointers in private and local address spaces. In LLVM codegen, the static variable initializer is lowered by virtual function AsmPrinter::lowerConstant which is target generic. Since addrspacecast is target specific, AsmPrinter::lowerConst This patch overrides AsmPrinter::lowerConstant with AMDGPUAsmPrinter::lowerConstant, which is able to lower the target-specific addrspacecast in the null pointer representation so that -1 is co Differential Revision: https://reviews.llvm.org/D29284 llvm-svn: 294265
* [x86] add tests to show current codegen for vblendv*; NFCSanjay Patel2017-02-071-0/+319
| | | | | | | As noted in the comments, we should be able to eliminate cmp ops in several cases. llvm-svn: 294263
* GlobalISel: legalize narrow G_SELECTS on AArch64.Tim Northover2017-02-061-5/+15
| | | | | | Otherwise there aren't any patterns to select them. llvm-svn: 294261
* Fix the samplepgo indirect call promotion bug: we should not promote a ↵Dehao Chen2017-02-062-0/+18
| | | | | | | | | | | | | | | | direct call. Summary: Checking CS.getCalledFunction() == nullptr does not necessary indicate indirect call. We also need to check if CS.getCalledValue() is not a constant. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29570 llvm-svn: 294260
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-0616-39/+678
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
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