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* Temporarily revert "Recommit r328307: [IPSCCP] Use constant range ↵Eric Christopher2018-07-121-42/+13
| | | | | | | | | | information for comparisons of parameters." as it's causing miscompiles. A testcase was provided in the original review thread. This reverts commit r336098. llvm-svn: 336877
* [x86] Fix another trivial bug in x86 flags copy lowering that has beenChandler Carruth2018-07-121-0/+106
| | | | | | | | | | | | | | | there for a long time. The boolean tracking whether we saw a kill of the flags was supposed to be per-block we are scanning and instead was outside that loop and never cleared. It requires a quite contrived test case to hit this as you have to have multiple levels of successors and interleave them with kills. I've included such a test case here. This is another bug found testing SLH and extracted to its own focused patch. llvm-svn: 336876
* [X86] Add patterns to use VMOVSS/SD zero masking for scalar f32/f64 select ↵Craig Topper2018-07-122-18/+12
| | | | | | | | with zero. These showed up in some of the upgraded FMA code. We really need to improve these test cases more, but this helps for now. llvm-svn: 336875
* [x86] Fix EFLAGS copy lowering to correctly handle walking past uses inChandler Carruth2018-07-121-0/+79
| | | | | | | | | | | | | | | | | | multiple successors where some of the uses end up killing the EFLAGS register. There was a bug where rather than skipping to the next basic block queued up with uses once we saw a kill, we stopped processing the blocks entirely. =/ Test case produces completely nonsensical code w/o this tiny fix. This was found testing Speculative Load Hardening and split out of that work. Differential Revision: https://reviews.llvm.org/D49211 llvm-svn: 336874
* [X86] Remove and autoupgrade the scalar fma intrinsics with masking.Craig Topper2018-07-125-275/+1581
| | | | | | This converts them to what clang is now using for codegen. Unfortunately, there seem to be a few kinks to work out still. I'll try to address with follow up patches. llvm-svn: 336871
* Add -allow-deprecated-dag-overlap to one of the experimental webassembly ↵Eric Christopher2018-07-121-1/+1
| | | | | | target tests. llvm-svn: 336870
* IR: Skip -print-*-all after -print-*Duncan P. N. Exon Smith2018-07-111-0/+13
| | | | | | | | | | This changes `-print-*` from transformation passes to analysis passes so that `-print-after-all` and `-print-before-all` don't trigger. This avoids some redundant output. Patch by Son Tuan Vu! llvm-svn: 336869
* [CodeGen] Emit more precise AssertZext/AssertSext nodes.Eli Friedman2018-07-113-2/+23
| | | | | | | | | | | | This is marginally helpful for removing redundant extensions, and the code is easier to read, so it seems like an all-around win. In the new test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an AssertZext i2, which allows the extension of the return value to be eliminated. Differential Revision: https://reviews.llvm.org/D49004 llvm-svn: 336868
* [LoopIdiomRecognize] Don't convert a do while loop to ctlz.Craig Topper2018-07-111-8/+15
| | | | | | | | | | | | | | | | | | | This commit suppresses turning loops like this into "(bitwidth - ctlz(input))". unsigned foo(unsigned input) { unsigned num = 0; do { ++num; input >>= 1; } while (input != 0); return num; } The loop version returns a value of 1 for both an input of 0 and an input of 1. Converting to a naive ctlz does not preserve that. Theoretically we could do better if we checked isKnownNonZero or we could insert a select to handle the divergence. But until we have motivating cases for that, this is the easiest solution. llvm-svn: 336864
* [LoopIdiomRecognize] Add a test case showing a loop we turn into ctlz that ↵Craig Topper2018-07-111-0/+36
| | | | | | | | we shouldn't. This loop executes one iteration without checking the input value. This produces a count of 1 for an input of 0 and 1. We are turning this into 32 - ctlz(n), but that returns 0 if n is 0. llvm-svn: 336862
* [NFC][InstCombine] Tests for x & (-1 >> y) != x -> x u> (-1 >> y) foldRoman Lebedev2018-07-112-0/+314
| | | | | | | https://bugs.llvm.org/show_bug.cgi?id=38123 https://rise4fun.com/Alive/Rny llvm-svn: 336857
* finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-112-4/+4
| | | | | | | | | Differential Revision: https://reviews.llvm.org/D47171 This contains the portions of that patch that could not be committed using the git monorepo because of dos line ending problems. llvm-svn: 336848
* [FileCheck] Don't permit overlapping CHECK-DAGJoel E. Denny2018-07-112-0/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That is, make CHECK-DAG skip matches that overlap the matches of any preceding consecutive CHECK-DAG directives. This change makes CHECK-DAG more consistent with other directives, and there is evidence it makes CHECK-DAG more intuitive and less error-prone. See the RFC discussion starting at: http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html Moreover, this behavior enables CHECK-DAG groups for unordered, non-unique strings or patterns. For example, it is useful for verifying output or logs from a parallel program, such as the OpenMP runtime. This patch also implements the command-line option -allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old overlapping behavior. This option should not be used in new tests. It is meant only for the existing tests that are broken by this change and that need time to update. See the following bugzilla issue for tracking of such tests: https://bugs.llvm.org/show_bug.cgi?id=37532 Patches to add -allow-deprecated-dag-overlap to those tests will follow immediately. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47106 llvm-svn: 336847
* [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-1162-208/+208
| | | | | | | | | | | | | | | | | | | See https://reviews.llvm.org/D47106 for details. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47171 This commit drops that patch's changes to: llvm/test/CodeGen/NVPTX/f16x2-instructions.ll llvm/test/CodeGen/NVPTX/param-load-store.ll For some reason, the dos line endings there prevent me from commiting via the monorepo. A follow-up commit (not via the monorepo) will finish the patch. llvm-svn: 336843
* [InstCombine] Fold x & (-1 >> y) == x to x u<= (-1 >> y)Roman Lebedev2018-07-114-49/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: https://bugs.llvm.org/show_bug.cgi?id=38123 This pattern will be produced by Implicit Integer Truncation sanitizer, https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530 in unsigned case, therefore it is probably a good idea to improve it. https://rise4fun.com/Alive/Rny ^ there are more opportunities for folds, i will follow up with them afterwards. Caveat: this somehow exposes a missing opportunities in `test/Transforms/InstCombine/icmp-logical.ll` It seems, the problem is in `foldLogOpOfMaskedICmps()` in `InstCombineAndOrXor.cpp`. But i'm not quite sure what is wrong, because it calls `getMaskedTypeForICmpPair()`, which calls `decomposeBitTestICmp()` which should already work for these cases... As @spatel notes in https://reviews.llvm.org/D49179#1158760, that code is a rather complex mess, so we'll let it slide. Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: yamauchi, majnemer, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D49179 llvm-svn: 336834
* Revert r336830: [FileCheck] Don't permit overlapping CHECK-DAGJoel E. Denny2018-07-112-524/+0
| | | | | | | Companion patches are failing to commit, and this patch alone breaks many tests. llvm-svn: 336833
* Quick fix for some Windows botsPaul Robinson2018-07-111-4/+4
| | | | llvm-svn: 336832
* [FileCheck] Don't permit overlapping CHECK-DAGJoel E. Denny2018-07-112-0/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That is, make CHECK-DAG skip matches that overlap the matches of any preceding consecutive CHECK-DAG directives. This change makes CHECK-DAG more consistent with other directives, and there is evidence it makes CHECK-DAG more intuitive and less error-prone. See the RFC discussion starting at: http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html Moreover, this behavior enables CHECK-DAG groups for unordered, non-unique strings or patterns. For example, it is useful for verifying output or logs from a parallel program, such as the OpenMP runtime. This patch also implements the command-line option -allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old overlapping behavior. This option should not be used in new tests. It is meant only for the existing tests that are broken by this change and that need time to update. See the following bugzilla issue for tracking of such tests: https://bugs.llvm.org/show_bug.cgi?id=37532 Patches to add -allow-deprecated-dag-overlap to those tests will follow immediately. Reviewed By: probinson Differential Revision: https://reviews.llvm.org/D47106 llvm-svn: 336830
* Revert "[llvm-objdump] Add -demangle (-C) option"Paul Semel2018-07-111-47/+0
| | | | | | | This reverts commit 3a44ccd156e0edd2e89226f8ed63928e227900bb. This reverts commit d5cfc836bb5552e20507d3612d13ff66ff9e36a0. llvm-svn: 336829
* [X86] Remove patterns for inserting a load into a zero vector.Craig Topper2018-07-111-4/+4
| | | | | | | | We can instead block the load folding isProfitableToFold. Then isel will emit a register->register move for the zeroing part and a separate load. The PostProcessISelDAG should be able to remove the register->register move. This saves us patterns and fixes the fact that we only had unaligned load patterns. The test changes show places where we should have been using an aligned load. llvm-svn: 336828
* [TargetTransformInfo] Add pow2 analysis for scalar constantsSimon Pilgrim2018-07-112-144/+144
| | | | | | Add ConstantInt analysis to getOperandInfo so we get more realistic div/rem expansion costs comparable to the vector costs. llvm-svn: 336827
* [InstSimplify] add/move tests for add folds; NFCSanjay Patel2018-07-112-9/+57
| | | | | | | | isKnownNegation() is currently proposed as part of D48754, but it could be used to make InstSimplify stronger independently of any abs() improvements. llvm-svn: 336822
* Fix llvm-objdump demangle test (added triple option)Paul Semel2018-07-111-5/+5
| | | | llvm-svn: 336821
* [X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions.Andrea Di Biagio2018-07-1118-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Before revision 336728, the "mayLoad" flag for instruction (V)MOVLPSrm was inferred directly from the "default" pattern associated with the instruction definition. r336728 removed special node X86Movlps, and all the patterns associated to it. Now instruction (V)MOVLPSrm doesn't have a pattern associated to it, and the 'mayLoad/hasSideEffects' flags are left unset. When the instruction info is emitted by tablegen, method CodeGenDAGPatterns::InferInstructionFlags() sees that (V)MOVLPSrm doesn't have a pattern, and flags are undefined. So, it conservatively sets the "hasSideEffects" flag for it. As a consequence, we were losing the 'mayLoad' flag, and we were gaining a 'hasSideEffect' flag in its place. This patch fixes the issue (originally reported by Michael Holmen). The mca tests show the differences in the instruction info flags. Instructions that were affected by this problem were: MOVLPSrm/VMOVLPSrm/VMOVLPSZ128rm. Differential Revision: https://reviews.llvm.org/D49182 llvm-svn: 336818
* [llvm-objdump] Add -demangle (-C) optionPaul Semel2018-07-111-0/+47
| | | | | | Differential Revision: https://reviews.llvm.org/D49043 llvm-svn: 336816
* [SLPVectorizer] Add initial alternate opcode support for cast instructions. ↵Simon Pilgrim2018-07-111-76/+154
| | | | | | | | | | | | | | | | | | | (REAPPLIED) We currently only support binary instructions in the alternate opcode shuffles. This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism: 1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly. 2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this. 3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc. 4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements. Reapplied with fix to only accept 2 different casts if they come from the same source type. Differential Revision: https://reviews.llvm.org/D49135 llvm-svn: 336812
* [SLPVectorizer] Ensure alternate/passthrough doesn't vectorize sdiv with ↵Simon Pilgrim2018-07-111-0/+81
| | | | | | undef elts llvm-svn: 336809
* [SLPVectorizer] Add some additional alternate cast testsSimon Pilgrim2018-07-111-0/+107
| | | | | | Initial attempt at D49135 failed as we weren't correctly handling casts with different source types. llvm-svn: 336808
* Revert rL336804: [SLPVectorizer] Add initial alternate opcode support for ↵Simon Pilgrim2018-07-111-151/+52
| | | | | | | | cast instructions. Reverting due to buildbot failures llvm-svn: 336806
* [SLPVectorizer] Add initial alternate opcode support for cast instructions.Simon Pilgrim2018-07-111-52/+151
| | | | | | | | | | | | | | | We currently only support binary instructions in the alternate opcode shuffles. This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism: 1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly. 2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this. 3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc. 4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements. Differential Revision: https://reviews.llvm.org/D49135 llvm-svn: 336804
* [CodeGen] Ignore debug uses in MachineCopyPropagationKrzysztof Parzyszek2018-07-111-0/+23
| | | | | | | Debug uses should not count as real uses, since the presence of debug information could affect the generated code. llvm-svn: 336803
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-11212-2025/+2025
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [NFC][InstCombine] Tests for x & (-1 >> y) == x -> x u<= (-1 >> y) foldRoman Lebedev2018-07-112-0/+314
| | | | | | | | | | | | | https://bugs.llvm.org/show_bug.cgi?id=38123 This pattern will be produced by Implicit Integer Truncation sanitizer, https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530 in unsigned case, therefore it is probably a good idea to improve it. https://rise4fun.com/Alive/Rny llvm-svn: 336796
* [ARM] ParallelDSP: multiple reduction stmts in loopSjoerd Meijer2018-07-111-1/+76
| | | | | | | | | | This fixes an issue that we were not properly supporting multiple reduction stmts in a loop, and not generating SMLADs for these cases. The alias analysis checks were done too early, making it too conservative. Differential revision: https://reviews.llvm.org/D49125 llvm-svn: 336795
* Use debug-prefix-map for AT_NAMEJonas Devlieghere2018-07-111-0/+8
| | | | | | | | | | | | | | | | | | AT_NAME was being emitted before the directory paths were remapped. This ensures that all paths are remapped before anything is emitted. An additional test case has been added. Note that this only works if the replacement string is an absolute path. If not, then AT_decl_file believes the new path is a relative path, and joins that path with the compilation directory. I do not know of a good way to resolve this. Patch by: Siddhartha Bagaria (starsid) Differential revision: https://reviews.llvm.org/D49169 llvm-svn: 336793
* [AArch64][SVE] Asm: Support for COMPACT instruction.Sander de Smalen2018-07-112-0/+48
| | | | | | | | | | | The compact instruction shuffles active elements of vector into lowest numbered elements and sets remaining elements to zero. e.g. compact z0.s, p0, z1.s llvm-svn: 336789
* Fix check-prefix vs check-prefixes typo in updated testSimon Pilgrim2018-07-111-2/+2
| | | | llvm-svn: 336787
* [AArch64] Regenerate SDIV testsSimon Pilgrim2018-07-112-64/+92
| | | | | | Will make codegen diffs much easier to grok in a future patch llvm-svn: 336786
* [NFC][InstCombine] icmp-logical.ll: add a few more tests.Roman Lebedev2018-07-111-0/+30
| | | | | | | | | | | The @masked_and_notA_slightly_optimized and @masked_or_A will break when PR38123 will be fixed: https://rise4fun.com/Alive/Rny Clearly, they aren't optimized currently. https://rise4fun.com/Alive/ERo llvm-svn: 336784
* [AArch64][SVE] Asm: Support for LAST(A|B) and CLAST(A|B) instructions.Sander de Smalen2018-07-118-0/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LASTB and LASTA instructions extract the last active element, or element after the last active, from the source vector. The added variants are: Scalar: last(a|b) w0, p0, z0.b last(a|b) w0, p0, z0.h last(a|b) w0, p0, z0.s last(a|b) x0, p0, z0.d SIMD & FP Scalar: last(a|b) b0, p0, z0.b last(a|b) h0, p0, z0.h last(a|b) s0, p0, z0.s last(a|b) d0, p0, z0.d The CLASTB and CLASTA conditionally extract the last or element after the last active element from the source vector. The added variants are: Scalar: clast(a|b) w0, p0, w0, z0.b clast(a|b) w0, p0, w0, z0.h clast(a|b) w0, p0, w0, z0.s clast(a|b) x0, p0, x0, z0.d SIMD & FP Scalar: clast(a|b) b0, p0, b0, z0.b clast(a|b) h0, p0, h0, z0.h clast(a|b) s0, p0, s0, z0.s clast(a|b) d0, p0, d0, z0.d Vector: clast(a|b) z0.b, p0, z0.b, z1.b clast(a|b) z0.h, p0, z0.h, z1.h clast(a|b) z0.s, p0, z0.s, z1.s clast(a|b) z0.d, p0, z0.d, z1.d Please refer to the architecture specification for more details on the semantics of the added instructions. llvm-svn: 336783
* [llvm-readobj] Add -hex-dump (-x) optionPaul Semel2018-07-111-0/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D48281 llvm-svn: 336782
* [NFC][InstCombine] Fix extra space padding in icmp-mul-zext.ll testRoman Lebedev2018-07-111-3/+4
| | | | | | update_test_checks will drop it anyway, creating noise.. llvm-svn: 336781
* [NFC][InstCombine] Add variable names and regenerate icmp-logical.ll test.Roman Lebedev2018-07-111-422/+423
| | | | llvm-svn: 336780
* [llvm-mca] Add tests for partial register writes.Andrea Di Biagio2018-07-114-0/+310
| | | | | | | | | | llvm-mca doesn't know that on modern AMD processors, portions of a general purpose register are not treated independently. So, a partial register write has a false dependency on the super-register. The issue with partial register writes will be addressed by a follow-up patch. llvm-svn: 336778
* [DAGCombiner] Support non-uniform X%C -> X-(X/C)*C foldsSimon Pilgrim2018-07-111-143/+118
| | | | | | | | | | First stage in PR38057 - support non-uniform constant vectors in the combine to reuse the division-by-constant logic. We can definitely do better for srem pow2 remainders (and avoid that extra multiply....) but this at least helps keep everything on the vector unit. Differential Revision: https://reviews.llvm.org/D48975 llvm-svn: 336774
* [DAGCombiner] Add (urem X, -1) -> select(X == -1, 0, x) foldSimon Pilgrim2018-07-111-40/+14
| | | | llvm-svn: 336773
* [TableGen] Add a general-purpose JSON backend.Simon Tatham2018-07-112-0/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
* [X86] The TEST instruction is eliminated when BSF/TZCNT is usedCraig Topper2018-07-111-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: These changes cover the PR#31399. Now the ffs(x) function is lowered to (x != 0) ? llvm.cttz(x) + 1 : 0 and it corresponds to the following llvm code: %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true) %tobool = icmp eq i32 %v, 0 %.op = add nuw nsw i32 %cnt, 1 %add = select i1 %tobool, i32 0, i32 %.op and x86 asm code: bsfl %edi, %ecx addl $1, %ecx testl %edi, %edi movl $0, %eax cmovnel %ecx, %eax In this case the 'test' instruction can't be eliminated because the 'add' instruction modifies the EFLAGS, namely, ZF flag that is set by the 'bsf' instruction when 'x' is zero. We now produce the following code: bsfl %edi, %ecx movl $-1, %eax cmovnel %ecx, %eax addl $1, %eax Patch by Ivan Kulagin Reviewers: davide, craig.topper, spatel, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48765 llvm-svn: 336768
* [X86] Remove some composite MOVSS/MOVSD isel patterns.Craig Topper2018-07-1111-173/+191
| | | | | | | | | | | | These patterns looked for a MOVSS/SD followed by a scalar_to_vector. Or a scalar_to_vector followed by a load. In both cases we emitted a MOVSS/SD for the MOVSS/SD part, a REG_CLASS for the scalar_to_vector, and a MOVSS/SD for the load. But we have patterns that do each of those 3 things individually so there's no reason to build large patterns. Most of the test changes are just reorderings. The one test that had a meaningful change is pr30430.ll and it appears to be a regression. But its doing -O0 so I think it missed a lot of opportunities and was just getting lucky before. llvm-svn: 336762
* [WebAssembly] Add pass to infer prototypes for prototype-less functionsSam Clegg2018-07-111-0/+20
| | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=35385 Differential Revision: https://reviews.llvm.org/D48471 llvm-svn: 336759
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