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* [Hexagon] Generate "insert" instructions more aggressivelyKrzysztof Parzyszek2015-07-081-0/+66
| | | | llvm-svn: 241681
* [yaml2obj] Align section content using AddressAlign field's valueSimon Atanasyan2015-07-081-0/+53
| | | | | | | | Use AddressAlign field's value to properly align sections content in the yaml2obj tool. Before this change the yaml2obj ignored AddressAlign and always aligned section on 16 bytes boundary. llvm-svn: 241674
* [LAA] Merge memchecks for accesses separated by a constant offsetSilviu Baranga2015-07-084-11/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Often filter-like loops will do memory accesses that are separated by constant offsets. In these cases it is common that we will exceed the threshold for the allowable number of checks. However, it should be possible to merge such checks, sice a check of any interval againt two other intervals separated by a constant offset (a,b), (a+c, b+c) will be equivalent with a check againt (a, b+c), as long as (a,b) and (a+c, b+c) overlap. Assuming the loop will be executed for a sufficient number of iterations, this will be true. If not true, checking against (a, b+c) is still safe (although not equivalent). As long as there are no dependencies between two accesses, we can merge their checks into a single one. We use this technique to construct groups of accesses, and then check the intervals associated with the groups instead of checking the accesses directly. Reviewers: anemet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10386 llvm-svn: 241673
* [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding supportSimon Pilgrim2015-07-082-4/+36
| | | | llvm-svn: 241671
* [yaml2obj] Use regex to match sections offsets. NFCSimon Atanasyan2015-07-082-3/+3
| | | | llvm-svn: 241669
* Allow constfolding of llvm.sin.* and llvm.cos.* intrinsicsKarthik Bhat2015-07-081-0/+22
| | | | | | | | This patch const folds llvm.sin.* and llvm.cos.* intrinsics whenever feasible. Differential Revision: http://reviews.llvm.org/D10836 llvm-svn: 241665
* llvm-objdump: Replace the -macho -raw option with a generic -raw-clang-astAdrian Prantl2015-07-081-2/+0
| | | | | | | | | | | | | | | option that works with all object container formats. Now that clang modules/PCH are object containers this option is useful to to construct pipes like llvm-objdump -raw-clang-ast foo.pcm | llvm-bcanalyzer - to inspect the AST contents in a PCH container. Will be tested via clang. Belatedly addresses review feedback for r233390. llvm-svn: 241659
* [WinEH] Make llvm.x86.seh.restoreframe work for stack realignment prologuesReid Kleckner2015-07-071-0/+99
| | | | | | | | | | The incoming EBP value points to the end of a local stack allocation, so we can use that to restore ESI, the base pointer. Once we do that, we can use local stack allocations. If we know we need stack realignment, spill the original frame pointer in the prologue and reload it after restoring ESI. llvm-svn: 241648
* [WinEH] Add localaddress intrinsic instead of using frameaddressReid Kleckner2015-07-073-11/+11
| | | | | | | Clang uses this for SEH finally. The new intrinsic will produce the right value when stack realignment is required. llvm-svn: 241643
* Add more nvcastsArnold Schwaighofer2015-07-071-0/+14
| | | | | | | | | Tim Northover has told me that they can occur when the compiler cleverly constructs constants - as demonstrated in the test case. rdar://21703486 llvm-svn: 241641
* Rename llvm.frameescape and llvm.framerecover to localescape and localrecoverReid Kleckner2015-07-0728-127/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Initially, these intrinsics seemed like part of a family of "frame" related intrinsics, but now I think that's more confusing than helpful. Initially, the LangRef specified that this would create a new kind of allocation that would be allocated at a fixed offset from the frame pointer (EBP/RBP). We ended up dropping that design, and leaving the stack frame layout alone. These intrinsics are really about sharing local stack allocations, not frame pointers. I intend to go further and add an `llvm.localaddress()` intrinsic that returns whatever register (EBP, ESI, ESP, RBX) is being used to address locals, which should not be confused with the frame pointer. Naming suggestions at this point are welcome, I'm happy to re-run sed. Reviewers: majnemer, nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11011 llvm-svn: 241633
* [llvm-objdump] Print the call target next to the instructionDavid Majnemer2015-07-071-11/+11
| | | | | | | GNU binutils provides this behavior. objdump -r doesn't really help when you aren't dealing with relocation object files. llvm-svn: 241631
* MIR Serialization: Serialize the 'dead' register machine operand flag.Alex Lorenz2015-07-071-0/+26
| | | | llvm-svn: 241624
* Add CHECK lines to test caseArnold Schwaighofer2015-07-071-1/+8
| | | | llvm-svn: 241619
* Add a pattern for a nvcast from v2f64 -> v4f32Arnold Schwaighofer2015-07-071-0/+8
| | | | | | | | | Since the NvCast is generated by the selection process the concerns about endianess and bit reversal don't apply. rdar://21703486 llvm-svn: 241611
* Delete UnknownAddress. It is a perfectly valid symbol value.Rafael Espindola2015-07-071-0/+3
| | | | | | | | | | | getSymbolValue now returns a value that in convenient for most callers: * 0 for undefined * symbol size for common symbols * offset/address for symbols the rest Code that needs something more specific can check getSymbolFlags. llvm-svn: 241605
* Fix test case to unbreak build.Akira Hatanaka2015-07-071-9/+18
| | | | | | | | This commit changes the target arch to fix the test case commited in r241566 that was failing on ninja-x64-msvc-RA-centos6. Also add checks to make sure the callee's address is loaded to blx's operand. llvm-svn: 241588
* Common symbols are not undefined, at least for ObjectFile.Rafael Espindola2015-07-071-0/+9
| | | | | | | | | They are implemented like that in some object formats, but for the interface provided by lib/Object, SF_Undefined and SF_Common are different things. This matches the ELF and COFF implementation and fixes llvm-nm for MachO. llvm-svn: 241587
* [ARM] Define a subtarget feature and use it to decide whether long calls shouldAkira Hatanaka2015-07-075-9/+49
| | | | | | | | | | | | | | | | | be emitted. This is needed to enable ARM long calls for LTO and enable and disable it on a per-function basis. Out-of-tree projects currently using EnableARMLongCalls to emit long calls should start passing "+long-calls" to the feature string (see the changes made to clang in r241565). rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D9364 llvm-svn: 241566
* MIR Parser: Verify the implicit machine register operands.Alex Lorenz2015-07-0712-26/+142
| | | | | | | | | | | | This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
* [WebAssembly] Create a CodeGen unittest directory.Dan Gohman2015-07-061-0/+2
| | | | llvm-svn: 241520
* MIR Serialization: Serialize the implicit register flag.Alex Lorenz2015-07-063-2/+65
| | | | | | | | | | | | | | This commit serializes the implicit flag for the register machine operands. It introduces two new keywords into the machine instruction syntax: 'implicit' and 'implicit-def'. The 'implicit' keyword is used for the implicit register operands, and the 'implicit-def' keyword is used for the register operands that have both the implicit and the define flags set. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10709 llvm-svn: 241519
* [X86][AVX] Add support for shuffle decoding of vperm2f128/vperm2i128 with ↵Simon Pilgrim2015-07-061-10/+10
| | | | | | | | | | | | zero'd lanes The vperm2f128/vperm2i128 shuffle mask decoding was not attempting to deal with shuffles that give zero lanes. This patch fixes this so that the assembly printer can provide shuffle comments. As this decoder is also used in X86ISelLowering for shuffle combining, I've added an early-out to match existing behaviour. The hope is that we can add zero support in the future, this would allow other ops' decodes (e.g. insertps) to be combined as well. Differential Revision: http://reviews.llvm.org/D10593 llvm-svn: 241516
* [x86] extend machine combiner reassociation optimization to SSE scalar addsSanjay Patel2015-07-061-42/+89
| | | | | | | | | | | | Extend the reassociation optimization of http://reviews.llvm.org/rL240361 (D10460) to SSE scalar FP SP adds in addition to AVX scalar FP SP adds. With the 'switch' in place, we can trivially add other opcodes and test cases in future patches. Differential Revision: http://reviews.llvm.org/D10975 llvm-svn: 241515
* [X86][SSE] Vectorized i64 uniform constant SRA shiftsSimon Pilgrim2015-07-065-79/+55
| | | | | | | | This patch adds vectorization support for uniform constant i64 arithmetic shift right operators. Differential Revision: http://reviews.llvm.org/D9645 llvm-svn: 241514
* llvm-nm: treat weak undefined as undefined.Rafael Espindola2015-07-062-2/+11
| | | | | | This matches the behavior of gnu ld. llvm-svn: 241512
* [WinEH] Add some test cases I forgot to add to previous commitsReid Kleckner2015-07-062-0/+258
| | | | llvm-svn: 241510
* [WinEH] Insert the EH code load before the block terminatorReid Kleckner2015-07-061-0/+66
| | | | | | | The previous code put the load after the terminator, leading to invalid IR and downstream crashes. This caused http://crbug.com/506446. llvm-svn: 241509
* [X86][SSE4A] Shuffle lowering using SSE4A EXTRQ/INSERTQ instructionsSimon Pilgrim2015-07-061-0/+221
| | | | | | | | | | | | This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 llvm-svn: 241508
* When sorting by address, undefined symbols go first.Rafael Espindola2015-07-061-16/+17
| | | | | | This matches gnu nm. llvm-svn: 241488
* [llvm-extract] Drop comdats from declarationsReid Kleckner2015-07-061-2/+5
| | | | | | The verifier rejects comdats on declarations. llvm-svn: 241483
* Fix printing of common symbols.Rafael Espindola2015-07-061-0/+3
| | | | | | Printing the symbol size matches the behavior or both gnu nm and freebsd nm. llvm-svn: 241480
* llc: Add a 'run-pass' option.Alex Lorenz2015-07-061-0/+7
| | | | | | | | | | | | | | | This commit adds a 'run-pass' option to llc, which instructs the compiler to run one specific code generation pass only. Llc already has the 'start-after' and the 'stop-after' options, and this new option complements the other two by making it easier to write tests that want to invoke a single pass only. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10776 llvm-svn: 241476
* AMDGPU/SI: Add debugging subtarget feature for DS offsetsMatt Arsenault2015-07-061-2/+3
| | | | | | | | We don't have a good way to detect most situations where DS offsets are usable on SI, so add an option to force using them even if unsafe for debugging performance problems. llvm-svn: 241462
* [Sparc] Add more instruction aliases.James Y Knight2015-07-062-3/+131
| | | | | | | | | These are mostly from the chart in the SparcV8 spec, section "A.3 Synthetic Instructions". Differential Revision: http://reviews.llvm.org/D9834 llvm-svn: 241461
* [Sparc] Add support for flush instruction.James Y Knight2015-07-061-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D9833 llvm-svn: 241460
* Check that COFF .obj files have sections with zero virtual address spaces.Rafael Espindola2015-07-062-0/+13
| | | | | | | | | | | | | When talking about the virtual address of sections the coff spec says: ... for simplicity, compilers should set this to zero. Otherwise, it is an arbitrary value that is subtracted from offsets during relocation. We don't currently subtract it, so check that it is zero. If some producer does create such files, we can change getRelocationOffset instead. llvm-svn: 241447
* [X86][SSE] Added missing stack folding test for SQRTSD and SQRTSS instructions.Simon Pilgrim2015-07-061-2/+14
| | | | llvm-svn: 241445
* [X86][AVX512] Multiply Packed Unsigned Integers with Round and ScaleAsaf Badouh2015-07-064-0/+149
| | | | | | | | | pmulhrsw review: http://reviews.llvm.org/D10948 llvm-svn: 241443
* [Mips] Add support for MCJIT for MIPS32r6Petar Jovanovic2015-07-062-0/+54
| | | | | | | | | | Add support for resolving MIPS32r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10687 llvm-svn: 241442
* Fix handling of ELF::R_MIPS_32 on Mips64.Rafael Espindola2015-07-062-0/+6
| | | | | | Thanks to Aboud, Amjad for reporting the regression and providing the testcase. llvm-svn: 241440
* Make this test a bit more interesting.Rafael Espindola2015-07-061-1/+4
| | | | | | Before every test was using a section with an address of zero. llvm-svn: 241427
* change CHECK to CHECK-LABEL for more precisionSanjay Patel2015-07-051-1/+1
| | | | llvm-svn: 241422
* remove unnecessary test specificationsSanjay Patel2015-07-051-5/+4
| | | | llvm-svn: 241419
* minimize test case and remove unnecessary opt passesSanjay Patel2015-07-051-65/+24
| | | | llvm-svn: 241418
* Verifier: Forbid comdats on linker declarations.Peter Collingbourne2015-07-052-0/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D10945 llvm-svn: 241414
* [X86][SSE3] Just use an explicit SSE3 target attribute - not a cpu type.Simon Pilgrim2015-07-051-1/+1
| | | | | | Merged arch/target into a specific triple - we had i686 and x86_64 targets overriding each other.... llvm-svn: 241410
* [X86][SSE2] Just use an explicit SSE2 target attribute - not a cpu type.Simon Pilgrim2015-07-051-1/+1
| | | | | | corei7 is capable of a lot more than just SSE2.... llvm-svn: 241409
* [x86][AVX512] add Multiply High OpAsaf Badouh2015-07-054-0/+297
| | | | | | | | | include encoding and intrinsics tests. review http://reviews.llvm.org/D10896 llvm-svn: 241406
* [X86] Fix incorrect/inefficient pushw encodings for x86-64 targetsMichael Kuperstein2015-07-053-0/+45
| | | | | | | | | | | | | Correctly support assembling "pushw $imm8" on x86-64 targets. Also some cleanup of the PUSH instructions (PUSH64i16 and PUSHi16 actually represent the same instruction) This fixes PR23996 Patch by: david.l.kreitzer@intel.com Differential Revision: http://reviews.llvm.org/D10878 llvm-svn: 241404
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