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* autogenerate checksIgor Breger2016-08-141-3/+20
| | | | llvm-svn: 278624
* [AVX512] Fix insertelement i1 lowering.Igor Breger2016-08-145-60/+155
| | | | | | | | | 1. Use shuffle to insert element i1 into vector. The previous implementation was incorrect ( dest_bit OR src_bit , it doesn't clear the bit if src_bit=0 ) 2. Improve shuffle i1 vector, use CVT2MASK if supported instead TRUNCATE. Differential Revision: http://reviews.llvm.org/D23347 llvm-svn: 278623
* Revert "CodeGen: If Convert blocks that would form a diamond when tail-merged."Diana Picus2016-08-142-79/+4
| | | | | | | | | This reverts commit r278287. This commit broke the clang-cmake-thumbv7-a15-full-sh bot. See https://llvm.org/bugs/show_bug.cgi?id=28949 llvm-svn: 278621
* Revert "Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough."Diana Picus2016-08-141-34/+0
| | | | | | | | | This reverts commit r278288. r278287 broke the clang-cmake-thumbv7-a15-full-sh bot. Revert this so we can get to r278287. llvm-svn: 278620
* [IRCE] Create llvm::Loop instances for cloned out loopsSanjoy Das2016-08-1412-16/+16
| | | | llvm-svn: 278618
* [IRCE] Don't iterate on loops that were cloned outSanjoy Das2016-08-141-0/+25
| | | | | | | | | | | | | | | | IRCE has the ability to further version pre-loops and post-loops that it created, but this isn't useful at all. This change teaches IRCE to leave behind some metadata in the loops it creates (by cloning the main loop) so that these new loops are not re-processed by IRCE. Today this bug is hidden by another bug -- IRCE does not update LoopInfo properly so the loop pass manager does not re-invoke IRCE on the loops it split out. However, once the latter is fixed the bug addressed in this change causes IRCE to infinite-loop in some cases (e.g. it splits out a pre-loop, a pre-pre-loop from that, a pre-pre-pre-loop from that and so on). llvm-svn: 278617
* Fix bitcode auto-upgrade when using bitcode lazy loadingMehdi Amini2016-08-142-0/+23
| | | | | | | | | | | | The auto-upgrade path could be called before the VST (global names) was fully parsed, and thus intrinsic names were not available and the autoupgrade logic could not operate. Fix link failures with ThinLTO. This is a recommit of r278610 with a different fix. llvm-svn: 278615
* Fix unsupported relocation type R_HEX_6_X' for symbol .rodataRon Lieberman2016-08-131-0/+40
| | | | | | | | | | | LowerTargetConstantPool is not properly setting the TargetFlag to indicate desired relocation. Coding error, the offset parameter was omitted, so the TargetFlag was used as the offset, and the TargetFlag defaulted to zero. This only affects -fpic compilation, and only those items created in a Constant Pool, for example a vector of constants. Halide ran into this issue. llvm-svn: 278614
* Revert "Fix bitcode auto-upgrade when using bitcode lazy loading"Mehdi Amini2016-08-132-23/+0
| | | | | | This reverts commit r278610. Tests are broken llvm-svn: 278613
* [IRCE] Fix test case; NFCSanjoy Das2016-08-131-1/+1
| | | | | | | | The (negative) test case is supposed to check that IRCE does not muck with range checks it cannot handle, not that it does the right thing in the absence of profiling information. llvm-svn: 278612
* [IRCE] Be resilient in the face of non-simplified loopsSanjoy Das2016-08-131-1/+38
| | | | | | | | Loops containing `indirectbr` may not be in simplified form, even after running LoopSimplify. Reject then gracefully, instead of tripping an assert. llvm-svn: 278611
* Fix bitcode auto-upgrade when using bitcode lazy loadingMehdi Amini2016-08-132-0/+23
| | | | | | | | | | The auto-upgrade path could be called before the VST (global names) was fully parsed, and thus intrinsic names were not available and the autoupgrade logic could not operate. Fix link failures with ThinLTO. llvm-svn: 278610
* Revert "Revert "Invariant start/end intrinsics overloaded for address space""Mehdi Amini2016-08-136-18/+45
| | | | | | This reverts commit 32fc6488e48eafc0ca1bac1bd9cbf0008224d530. llvm-svn: 278609
* Revert "Invariant start/end intrinsics overloaded for address space"Mehdi Amini2016-08-136-45/+18
| | | | | | This reverts commit r276447. llvm-svn: 278608
* Add missing REQUIRES in sancov/print_coverage_pcs.test: it requires aarch64 ↵Mehdi Amini2016-08-131-1/+1
| | | | | | as well now llvm-svn: 278601
* [x86] add tests to show missed 64-bit immediate mergingSanjay Patel2016-08-131-0/+54
| | | | | | | Tests are slightly modified versions of those written by Sunita Marathe in D23391. llvm-svn: 278599
* [AVX-512] Remove an AddedComplexity that was prioritizing basic vzmovl ↵Craig Topper2016-08-131-12/+6
| | | | | | patterns over more complex ones that produce better code. llvm-svn: 278593
* [AVX-512] Add patterns to support VZEXT_MOVL from 512-bit vectors with ↵Craig Topper2016-08-134-0/+101
| | | | | | | | 64-bit and 32-bit elements. Fixes PR28961. llvm-svn: 278592
* [PM] Port LoopDataPrefetch to new pass managerTeresa Johnson2016-08-131-0/+1
| | | | | | | | | | | | | | | | Summary: Refactor the existing support into a LoopDataPrefetch implementation class and a LoopDataPrefetchLegacyPass class that invokes it. Add a new LoopDataPrefetchPass for the new pass manager that utilizes the LoopDataPrefetch implementation class. Reviewers: mehdi_amini Subscribers: sanjoy, mzolotukhin, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D23483 llvm-svn: 278591
* AMDGPU: Fix missing test for addressing mode with odd offsetsMatt Arsenault2016-08-131-5/+31
| | | | | | Add test if the constant offset looks unaligned. llvm-svn: 278589
* [IndVars] Ignore (s|z)exts that don't extend the induction variableSanjoy Das2016-08-131-0/+20
| | | | | | | | | | | | | | | | | | `IVVisitor::visitCast` used to have the invariant that if the instruction it was passed was a sext or zext instruction, the result of the instruction would be wider than the induction variable. This is no longer true after rL275037, so this change teaches `IndVarSimplify` s implementation of `IVVisitor::visitCast` to work with the relaxed invariant. A corresponding change to SimplifyIndVar to preserve the said invariant after rL275037 would also work, but given how `IVVisitor::visitCast` is spelled (no indication of said invariant), I figured the current fix is cleaner. Fixes PR28935. llvm-svn: 278584
* [WebAssembly] Re-enable disabled debug value testDominic Chen2016-08-121-1/+0
| | | | | | | | | | | | | | | Summary: This test was resulting in asan/valgrind failures due to undefined DWARF register mappings for WebAssembly, and was disabled in r278495. These have been resolved. Reviewers: sunfish, dschuff Subscribers: bkramer, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D23459 llvm-svn: 278576
* Reapply [BranchFolding] Restrict tail merging loop blocks after MBPHaicheng Wu2016-08-122-1/+93
| | | | | | | | | Fixed a bug in the test case. To fix PR28104, this patch restricts tail merging to blocks that belong to the same loop after MBP. llvm-svn: 278575
* [LoopVectorize] Detect loops in the innermost loop before creating ↵Tim Shen2016-08-121-0/+71
| | | | | | | | | | | | | InnerLoopVectorizer InnerLoopVectorizer shouldn't handle a loop with cycles inside the loop body, even if that cycle isn't a natural loop. Fixes PR28541. Differential Revision: https://reviews.llvm.org/D22952 llvm-svn: 278573
* [Inliner] Don't treat inalloca allocas as staticReid Kleckner2016-08-121-0/+63
| | | | | | | | | They aren't static, and moving them to the entry block across something else will only result in tears. Root cause of http://crbug.com/636558. llvm-svn: 278571
* [NVPTX] Use untyped (.b) integer registers in PTX.Artem Belevich2016-08-121-0/+69
| | | | | | | | | | | | This bring LLVM-generated PTX closer to what nvcc generates and avoids triggering issues in ptxas. For instance, ptxas does not accept .s16 (or .u16) registers as operands for .fp16 instructions. Differential Revision: https://reviews.llvm.org/D23460 llvm-svn: 278568
* [AArch64LoadStoreOptimizer] Check aliasing correctly when creating paired ↵Eli Friedman2016-08-121-0/+47
| | | | | | | | | | loads/stores. The existing code accidentally skipped the aliasing check in edge cases. Differential revision: https://reviews.llvm.org/D23372 llvm-svn: 278562
* [AArch64] Registering default MCInstrAnalysisMike Aizatsky2016-08-122-0/+4
| | | | | | | | | | | | Even in this form it is useful: it can detect branch instructions. https://github.com/google/sanitizers/issues/706 Subscribers: aemerson, rengolin Differential Revision: https://reviews.llvm.org/D23426 llvm-svn: 278560
* [AArch64LoadStoreOpt] Handle offsets correctly for post-indexed paired loads.Eli Friedman2016-08-121-1/+102
| | | | | | | | Trunk would try to create something like "stp x9, x8, [x0], #512", which isn't actually a valid instruction. Differential revision: https://reviews.llvm.org/D23368 llvm-svn: 278559
* Next set of additional error checks for invalid Mach-O files.Kevin Enderby2016-08-1212-9/+39
| | | | | | | | | | This contains the two missing checks for LC_SEGMENT load command fields. And checks for the Mach-O sections fields that would make them invalid. With the new checks, some of the existing malformed file checks now trips one of these instead of the issue it was having before so those tests were adjusted. llvm-svn: 278557
* [sancov] test file cleanupMike Aizatsky2016-08-121-1/+0
| | | | llvm-svn: 278556
* [sancov] MachO indirect symbols support.Mike Aizatsky2016-08-122-0/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D23338 llvm-svn: 278551
* [PM] Port LowerInvoke to the new pass managerMichael Kuperstein2016-08-121-0/+1
| | | | llvm-svn: 278531
* Fine tuning of sample profile propagation algorithm.Dehao Chen2016-08-1210-28/+29
| | | | | | | | | | | | Summary: The refined propagation algorithm is more accurate and robust. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23224 llvm-svn: 278522
* [x86] X86ISelLowering zext(add_nuw(x, C)) --> add(zext(x), C_zext)Artur Pilipenko2016-08-121-3/+29
| | | | | | | | | | | | | Currently X86ISelLowering has a similar transformation for sexts: sext(add_nsw(x, C)) --> add(sext(x), C_sext) In this change I extend this code to handle zexts as well. Reviewed By: spatel Differential Revision: https://reviews.llvm.org/D23359 llvm-svn: 278520
* [LVI] Take guards into accountArtur Pilipenko2016-08-121-0/+95
| | | | | | | | | | Teach LVI to gather control dependant constraints from guards. Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D23358 llvm-svn: 278518
* [LVI] Fix potential memory corruption in getValueFromConditionArtur Pilipenko2016-08-121-0/+140
| | | | | | Rewrite Visited[Cond] = getValueFromConditionImpl(..., Visited) statement which can lead to a memory corruption since getValueFromConditionImpl changes Visited map and invalidates the iterators. llvm-svn: 278514
* Revert "[Sparc] Leon errata fix passes."James Y Knight2016-08-128-151/+62
| | | | | | | | | | | ...and the two followup commits: Revert "[Sparc][Leon] Missed resetting option flags from check-in 278489." Revert "[Sparc][Leon] Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor." This reverts commit r274856, r278489, and r278492. llvm-svn: 278511
* [PM] Port NameAnonFunction pass to new pass managerTeresa Johnson2016-08-121-0/+1
| | | | | | | | | | | | | | | Summary: Port the NameAnonFunction pass and add a test. Depends on D23439. Reviewers: mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23440 llvm-svn: 278509
* [PM] Port ModuleSummaryIndex analysis to new pass managerTeresa Johnson2016-08-121-0/+2
| | | | | | | | | | | | | | | | | | | Summary: Port the ModuleSummaryAnalysisWrapperPass to the new pass manager. Use it in the ported BitcodeWriterPass (similar to how we use the legacy ModuleSummaryAnalysisWrapperPass in the legacy WriteBitcodePass). Also, pass the -module-summary opt flag through to the new pass manager pipeline and through to the bitcode writer pass, and add a test that uses it. Reviewers: mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23439 llvm-svn: 278508
* [X86][SSE] Add support for combining target shuffles to PSLLDQ/PSRLDQ byte ↵Simon Pilgrim2016-08-128-43/+35
| | | | | | shifts llvm-svn: 278502
* [LVI] Take range metadata into account while calculating icmp condition ↵Artur Pilipenko2016-08-122-0/+36
| | | | | | | | | | | | | | | | | constraints Take range metadata into account for conditions like this: %length = load i32, i32* %length_ptr, !range !{i32 0, i32 2147483647} %cmp = icmp ult i32 %a, %length This is a common pattern for range checks where the length of the array is dynamically loaded. Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D23267 llvm-svn: 278496
* [Webassembly] disable unstable test.Benjamin Kramer2016-08-121-0/+2
| | | | | | It reads uninitialized memory and crashes randomly. llvm-svn: 278495
* [X86][SSE] Fixed PALIGNR target shuffle decodeSimon Pilgrim2016-08-121-2/+2
| | | | | | | | The PALIGNR target shuffle decode was not taking into account that DecodePALIGNRMask (rather oddly) expects the operands to be in reverse order, nor was it detecting unary patterns, causing combines to combine with the incorrect input. The cgbuiltin, auto upgrade and instruction comments code correctly swap the operands so are not affected. llvm-svn: 278494
* [LVI] Handle any predicate in comparisons like icmp <pred> (add Val, ↵Artur Pilipenko2016-08-121-0/+130
| | | | | | | | | | | | | | | | | Offset), ... Currently LVI can only gather value constraints from comparisons like: * icmp <pred> Val, ... * icmp ult (add Val, Offset), ... In fact we can handle any predicate in latter comparisons. Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D23357 llvm-svn: 278493
* [Sparc][Leon] Errata fixes for various errata in different versions of the ↵Chris Dewhurst2016-08-125-82/+47
| | | | | | | | | | | | Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. These changes update older versions of these errata fixes with improvements to code and unit tests. Differential Revision: https://reviews.llvm.org/D21960 llvm-svn: 278489
* Revert "[BranchFolding] Restrict tail merging loop blocks after MBP"Haicheng Wu2016-08-122-93/+1
| | | | | | This reverts commit r278463 because it hits the bot. llvm-svn: 278484
* [Coroutines]: Part6b: Add coro.id intrinsic.Gor Nishanov2016-08-123-24/+25
| | | | | | | | | | | | | | | Summary: 1. Make coroutine representation more robust against optimization that may duplicate instruction by introducing coro.id intrinsics that returns a token that will get fed into coro.alloc and coro.begin. Due to coro.id returning a token, it won't get duplicated and can be used as reliable indicator of coroutine identify when a particular coroutine call gets inlined. 2. Move last three arguments of coro.begin into coro.id as they will be shared if coro.begin will get duplicated. 3. doc + test + code updated to support the new intrinsic. Reviewers: mehdi_amini, majnemer Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D23412 llvm-svn: 278481
* Recommit 'Remove the restriction that MachineSinking is now stopped byWei Mi2016-08-129-304/+347
| | | | | | | | | | | | | | | | "insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
* [BranchFolding] Restrict tail merging loop blocks after MBPHaicheng Wu2016-08-122-1/+93
| | | | | | | | | To fix PR28014, this patch restricts tail merging to blocks that belong to the same loop after MBP. Differential Revision: https://reviews.llvm.org/D23191 llvm-svn: 278463
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