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* Add a test for r307754George Burgess IV2017-07-121-0/+16
| | | | | | | | | | | As promised in D35003. Uses -codegenprepare instead of -instcombine since we hit the same buggy path anyway, and CGP lets us keep this test really simple (instcombine likes turning the alloca T, N into alloca [N x T], which hides the bug this is testing for). llvm-svn: 307811
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-123-1/+9
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* Add back a CHECK line.Rafael Espindola2017-07-121-0/+1
| | | | | | | | I accidentally removed it in r307730. Thanks to Martin Storsjö for noticing! llvm-svn: 307801
* [CodeGen] Add dependency printerEvandro Menezes2017-07-1212-52/+52
| | | | | | | | Add SDep printer to make debugging sessions more productive. Differential revision: https://reviews.llvm.org/D35144 llvm-svn: 307799
* [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats.Davide Italiano2017-07-121-0/+15
| | | | | | | | | | FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797
* Add element atomic memmove intrinsicDaniel Neilson2017-07-122-0/+87
| | | | | | | | | | | | | | Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-124-0/+19
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [X86][SSE] Fix file check prefix warning breaking buildbotsSimon Pilgrim2017-07-122-4/+4
| | | | llvm-svn: 307790
* Make shell redirection construct portableKamil Rytarowski2017-07-1222-23/+22
| | | | | | | | | | | | | | | | | | | | | | Summary: NetBSD shell sh(1) does not support ">& /dev/null" construct. This is bashism. The portable and POSIX solution is to use: "> /dev/null 2>&1". This change fixes 22 Unexpected Failures on NetBSD/amd64 for the "check-llvm" target. Sponsored by <The NetBSD Foundation> Reviewers: joerg, dim, rnk Reviewed By: joerg, rnk Subscribers: rnk, davide, llvm-commits Differential Revision: https://reviews.llvm.org/D35277 llvm-svn: 307789
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-9/+13
| | | | | | | | | When we have a diamond ifcvt the fallthough block will have a branch at the end of it that disappears when predicated, so discount it from the predication cost. Differential Revision: https://reviews.llvm.org/D34952 llvm-svn: 307788
* [X86][SSE] Add 512-bit (iX bitcast(vXi1)) test casesSimon Pilgrim2017-07-122-0/+3245
| | | | | | Improves test coverage for pre-AVX512 targets as well llvm-svn: 307783
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-124-0/+25
| | | | llvm-svn: 307779
* [Linker] Add directives to support mixing ARM/Thumb module-level inline asm.Florian Hahn2017-07-122-0/+23
| | | | | | | | | | | | | | | | | | | | | | Summary: By prepending `.text .thumb .balign 2` to the module-level inline assembly from a Thumb module, the assembler will generate the assembly from that module as Thumb, even if the destination module uses an ARM triple. Similar directives are used for module-level inline assembly in ARM modules. The alignment and instruction set are reset based on the target triple before emitting the first function label. Reviewers: olista01, tejohnson, echristo, t.p.northover, rafael Reviewed By: echristo Subscribers: aemerson, javed.absar, eraman, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34622 llvm-svn: 307772
* [ARM] GlobalISel: Select s64 G_FCMPDiana Picus2017-07-121-0/+605
| | | | | | | Very similar to how we select s32 G_FCMP, the only thing that is different is the exact opcodes that we use. llvm-svn: 307763
* [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess.Michael Zuckerman2017-07-121-83/+143
| | | | | | Adding base test for AVX512 llvm-svn: 307761
* Specify complete target triple in testMatthias Braun2017-07-121-2/+2
| | | | | | This should fix the problems on the greendragon build. llvm-svn: 307747
* LowerTypeTests: When importing functions skip definitions where the summary ↵Peter Collingbourne2017-07-122-0/+8
| | | | | | | | | | | | | | contains a decl. This normally indicates mixed CFI + non-CFI compilation, and will result in us treating the function in the same way as a function defined outside of the LTO unit. Part of PR33752. Differential Revision: https://reviews.llvm.org/D35281 llvm-svn: 307744
* [WebAssembly] Expose the offset of each data segmentSam Clegg2017-07-123-4/+7
| | | | | | | | | | | | | | Summary: This allows tools like lld that process relocations to apply data relocation correctly. This information is required because relocation are stored as section offset. Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D35234 llvm-svn: 307741
* [codeview] Change readobj symbol dumping formatReid Kleckner2017-07-1131-164/+172
| | | | | | | | Avoid duplicating DictScope with hand-written names everywhere. Print the S_-prefixed symbol kind for every record. This should make it easier to search for certain kinds of records when debugging PDB linking. llvm-svn: 307732
* Fully fix the movw/movt addend.Rafael Espindola2017-07-111-1/+12
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [IPO] Temporarily rollback r307215.Davide Italiano2017-07-111-17/+0
| | | | | | | | | [GlobalOpt] Remove unreachable blocks before optimizing a function. While the change is presumably correct, it exposes a latent bug in DI which breaks on of the CFI checks. I'll analyze it further and try to understand what's going on. llvm-svn: 307729
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-1125-423/+590
| | | | | | | | | | | | | | | | | | | | | | | | | | | OpenCL 2.0 introduces the notion of memory scopes in atomic operations to global and local memory. These scopes restrict how synchronization is achieved, which can result in improved performance. This change extends existing notion of synchronization scopes in LLVM to support arbitrary scopes expressed as target-specific strings, in addition to the already defined scopes (single thread, system). The LLVM IR and MIR syntax for expressing synchronization scopes has changed to use *syncscope("<scope>")*, where <scope> can be "singlethread" (this replaces *singlethread* keyword), or a target-specific name. As before, if the scope is not specified, it defaults to CrossThread/System scope. Implementation details: - Mapping from synchronization scope name/string to synchronization scope id is stored in LLVM context; - CrossThread/System and SingleThread scopes are pre-defined to efficiently check for known scopes without comparing strings; - Synchronization scope names are stored in SYNC_SCOPE_NAMES_BLOCK in the bitcode. Differential Revision: https://reviews.llvm.org/D21723 llvm-svn: 307722
* [x86] auto-generate full checks; NFCSanjay Patel2017-07-111-79/+126
| | | | llvm-svn: 307718
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+36
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
* [ProfileData] Add new option to dump topn hottest functionsXinliang David Li2017-07-111-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D35155 llvm-svn: 307702
* [NewGVN] Check for congruency of memory accesses.Davide Italiano2017-07-111-0/+91
| | | | | | | | | | This is fine as nothing in the code relies on leader and memory leader being the same for a given congruency class. Ack'ed by Dan. Fixes PR33720. llvm-svn: 307699
* reverting 307677.Michael Zuckerman2017-07-111-144/+67
| | | | llvm-svn: 307698
* [PPC] Fix one test case regression for patch https://reviews.llvm.org/D34337.Tony Jiang2017-07-111-1/+0
| | | | llvm-svn: 307691
* [msan] Only check shadow memory for operands that are sized.Evgeniy Stepanov2017-07-111-0/+22
| | | | | | | | | | Fixes PR33347: https://bugs.llvm.org/show_bug.cgi?id=33347. Differential Revision: https://reviews.llvm.org/D35160 Patch by Matt Morehouse. llvm-svn: 307684
* [mips][mt][1/7] Add the MT ASE as a subtarget feature.Simon Dardis2017-07-111-0/+10
| | | | | | | | | | Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 llvm-svn: 307679
* [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess. Michael Zuckerman2017-07-111-67/+144
| | | | | | | Base test for avx512 adding new base test to trunk befor commit change on the test llvm-svn: 307677
* [LoopUnrollRuntime] Avoid multi-exit nested loop with epilog generationAnna Thomas2017-07-111-0/+44
| | | | | | | | | | The loop structure for the outer loop does not contain the epilog preheader when we try to unroll inner loop with multiple exits and epilog code is generated. For now, we just bail out in such cases. Added a test case that shows the problem. Without this bailout, we would trip on assert saying LCSSA form is incorrect for outer loop. llvm-svn: 307676
* [Hexagon] Do not rely on callee-saved info in hasFPKrzysztof Parzyszek2017-07-112-0/+165
| | | | llvm-svn: 307675
* [PPC] Fix two bugs in frame lowering.Tony Jiang2017-07-113-4/+40
| | | | | | | | | | | 1. The available program storage region of the red zone to compilers is 288 bytes rather than 244 bytes. 2. The formula for negative number alignment calculation should be y = x & ~(n-1) rather than y = (x + (n-1)) & ~(n-1). Differential Revision: https://reviews.llvm.org/D34337 llvm-svn: 307672
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-0/+28
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [ARM] GlobalISel: Tighten G_FCMP selection test. NFCDiana Picus2017-07-111-68/+68
| | | | | | | | Use CHECK-NEXT for the comparison sequence, to make sure we don't get any unexpected instructions in the middle of our flag manipulation efforts. llvm-svn: 307656
* [DWARF] - Add testcase for checking message about broken relocations.George Rimar2017-07-111-0/+35
| | | | | | Addresses comments for r306677, which fixed error message itself. llvm-svn: 307655
* [X86][AVX512] regenerate avx512-insert-extract.llGuy Blank2017-07-111-3/+3
| | | | llvm-svn: 307654
* [ARM] GlobalISel: Add reg mapping for s64 G_FCMPDiana Picus2017-07-111-0/+29
| | | | | | Map the result into GPR and the operands into FPR. llvm-svn: 307653
* [ARM] GlobalISel: Tighten legalizer tests. NFCDiana Picus2017-07-113-0/+110
| | | | | | | | | | | | | | Make sure that all the legalizer tests where the original instruction needs to be removed check for the removal. We do this by adding CHECK-NOT lines before and after the replacement sequence. This won't catch pathological cases where the instruction remains somewhere in the middle of the instruction sequence that's supposed to replace it, but hopefully that won't occur in practice (since ideally we'd be setting the insert point for the new instruction sequence either before or after the original instruction and not fiddle with it while building the sequence). llvm-svn: 307647
* [globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is ↵Daniel Sanders2017-07-111-46/+102
| | | | | | | | | | | | | | | | | | | | | | used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
* [ARM] ldr pc,=expression should be allowed in Thumb2Peter Smith2017-07-111-8/+8
| | | | | | | | | | | This change allows the pc to be used as a destination register for the pseudo instruction LDR pc,=expression . The pseudo instruction must not be transformed into a MOV, but it can use the Thumb2 LDR (literal) instruction to a constant pool entry. See (A7.7.43 from ARMv7M ARM ARM). Differential Revision: https://reviews.llvm.org/D34751 llvm-svn: 307640
* [ARM] GlobalISel: Fix oversight in G_FCMP legalizationDiana Picus2017-07-111-0/+8
| | | | | | | We used to forget to erase the original instruction when replacing a G_FCMP true/false. Fix this bug and make sure the tests check for it. llvm-svn: 307639
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-112-2/+40
| | | | | | | | | | | | TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
* [ARM] GlobalISel: Legalize s64 G_FCMPDiana Picus2017-07-111-0/+878
| | | | | | Same as the s32 version, for both hard and soft float. llvm-svn: 307633
* Revert Revert [MBP] do not rotate loop if it creates extra branchSerguei Katkov2017-07-112-4/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a second attempt to land this patch. The first one resulted in a crash of clang sanitizer buildbot. The fix is here and regression test is added. This is a last fix for the corner case of PR32214. Actually this is not really corner case in general. We should not do a loop rotation if we create an additional branch due to it. Consider the case where we have a loop chain H, M, B, C , where H is header with viable fallthrough from pre-header and exit from the loop M - some middle block B - backedge to Header but with exit from the loop also. C - some cold block of the loop. Let's H is determined as a best exit. If we do a loop rotation M, B, C, H we can introduce the extra branch. Let's compute the change in number of branches: +1 branch from pre-header to header -1 branch from header to exit +1 branch from header to middle block if there is such -1 branch from cold bock to header if there is one So if C is not a predecessor of H then we introduce extra branch. This change actually prohibits rotation of the loop if both true Best Exit has next element in chain as successor. Last element in chain is not a predecessor of first element of chain. Reviewers: iteratee, xur, sammccall, chandlerc Reviewed By: iteratee Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34745 llvm-svn: 307631
* [GlobalISel][X86] Use correct AND instructions.Igor Breger2017-07-111-1/+1
| | | | | | AND8ri8 not supported in 64bit. llvm-svn: 307630
* [CGP] Relax a bit restriction for optimizeMemoryInst to extend scopeSerguei Katkov2017-07-111-0/+25
| | | | | | | | | | | | | | | | | | CodeGenPrepare::optimizeMemoryInst contains a check that we do nothing if all instructions combining the address for memory instruction is in the same block as memory instruction itself. However if any of these instruction are placed after memory instruction then address calculation will not be folded to memory instruction. The added test case shows an example. Reviewers: loladiro, spatel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34862 llvm-svn: 307628
* fix typos in comments; NFCHiroshi Inoue2017-07-111-1/+1
| | | | llvm-svn: 307626
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