summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [Support][CachePruning] prune least recently accessed files firstBob Haarman2018-08-221-23/+29
| | | | | | | | | | | | | | | | | Summary: Before this change, pruning order was based on size. This changes it to be based on time of last use instead, preferring to keep recently used files and prune older ones. Reviewers: pcc, rnk, espindola Reviewed By: rnk Subscribers: emaste, arichardson, hiraditya, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51062 llvm-svn: 340374
* [CodeGenPrepare] Set debug locations when splitting selectsVedant Kumar2018-08-221-3/+17
| | | | | | | When splitting a select into a diamond, set debug locations on newly-created branch instructions and phi nodes. llvm-svn: 340371
* [CodeGenPrepare] Clean up dbg.value use-before-def as late as possibleVedant Kumar2018-08-211-2/+2
| | | | | | | | | | | CodeGenPrepare has a strategy for moving dbg.values so that a value's definition always dominates its debug users. This cleanup was happening too early (before certain CGP transforms were run), resulting in some dbg.value use-before-def errors. Perform this cleanup as late as possible to avoid use-before-def. llvm-svn: 340370
* [CodeGenPrepare] Pre-commit debug info test for optimizeSelectInstVedant Kumar2018-08-211-0/+15
| | | | | | | | This test shows that optimizeSelectInst splits a select and sinks a `fdiv` operation to one side of the diamond. However, the dbg.value for the operation isn't moved. llvm-svn: 340369
* Avoid dbg.value use-before-def in a few tests (NFC)Vedant Kumar2018-08-214-13/+13
| | | | | | | | | | This is preparation for landing a use-before-def verifier for debug intrinsics (D46100). As a drive-by, remove `tail` from debug intrinsic calls because it doesn't mean anything in that context. llvm-svn: 340366
* [MS Demangler] Print template constructor args.Zachary Turner2018-08-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously if you had something like this: template<typename T> struct Foo { template<typename U> Foo(U); }; Foo F(3.7); this would mangle as ??$?0N@?$Foo@H@@QEAA@N@Z and this would be demangled as: undname: __cdecl Foo<int>::Foo<int><double>(double) llvm-undname: __cdecl Foo<int>::Foo<int>(double) Note the lack of the constructor template parameter in our demangling. This patch makes it so we print the constructor argument list. llvm-svn: 340356
* [LICM] Fix a test so it actualy checks what was meant [NFC]Philip Reames2018-08-211-8/+29
| | | | llvm-svn: 340344
* [AMDGPU] Consider loads from flat addrspace to be potentially divergentScott Linder2018-08-211-0/+15
| | | | | | | | | In general we can't assume flat loads are uniform, and cases where we can prove they are should be handled through infer-address-spaces. Differential Revision: https://reviews.llvm.org/D50991 llvm-svn: 340343
* [MS Demangler] Fix a few more edge cases.Zachary Turner2018-08-213-0/+8
| | | | | | | | | | | | | | | | I found these by running llvm-undname over a couple hundred megabytes of object files generated as part of building chromium. The issues fixed in this patch are: 1) decltype-auto return types. 2) Indirect vtables (e.g. const A::`vftable'{for `B'}) 3) Pointers, references, and rvalue-references to member pointers. I have exactly one remaining symbol out of a few hundred MB of object files that produces a name we can't demangle, and it's related to back-referencing. llvm-svn: 340341
* [WebAssembly] Restore __stack_pointer after catch instructionsHeejin Ahn2018-08-211-0/+5
| | | | | | | | | | | | | | | Summary: After the stack is unwound due to a thrown exception, the `__stack_pointer` global can point to an invalid address. This inserts instructions that restore `__stack_pointer` global. Reviewers: jgravelle-google, dschuff Subscribers: mgorny, sbc100, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50980 llvm-svn: 340339
* NFC: update the test comments in LV test about early exit loopsAnna Thomas2018-08-211-2/+14
| | | | llvm-svn: 340337
* [WebAssembly] v128.constThomas Lively2018-08-213-2/+88
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [CodeExtractor] Use 'normal destination' BB as insert point to store invoke ↵Florian Hahn2018-08-211-0/+47
| | | | | | | | | | | | | | | | | | | results. Currently CodeExtractor tries to use the next node after an invoke to place the store for the result of the invoke, if it is an out parameter of the region. This fails, as the invoke terminates the current BB. In that case, we can place the store in the 'normal destination' BB, as the result will only be available in that case. Reviewers: davidxl, davide, efriedma Reviewed By: davidxl Differential Revision: https://reviews.llvm.org/D51037 llvm-svn: 340331
* [WebAssembly] Don't make wasm cleanuppads into funclet entriesHeejin Ahn2018-08-211-2/+1
| | | | | | | | | | | | | | | Summary: Catchpads and cleanuppads are not funclet entries; they are only EH scope entries. We already dont't set `isEHFuncletEntry` for catchpads. This patch does the same thing for cleanuppads. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50654 llvm-svn: 340330
* [RegisterCoalescer] Use substPhysReg in reMaterializeTrivialDefBjorn Pettersson2018-08-211-0/+51
| | | | | | | | | | | | | | | | | | | Summary: When RegisterCoalescer::reMaterializeTrivialDef is substituting a register use in a DBG_VALUE instruction, and the old register is a subreg, and the new register is a physical register, then we need to use substPhysReg in order to extract the correct subreg. Reviewers: wmi, aprantl Reviewed By: wmi Subscribers: hiraditya, MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50844 llvm-svn: 340326
* [WebAssembly] Add isEHScopeReturn instruction propertyHeejin Ahn2018-08-211-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | Summary: So far, `isReturn` property is used to mean both a return instruction from a functon and the end of an EH scope, a scope that starts with a EH scope entry BB and ends with a catchret or a cleanupret instruction. Because WinEH uses funclets, all EH-scope-ending instructions are also real return instruction from a function. But for wasm, they only serve as the end marker of an EH scope but not a return instruction that exits a function. This mismatch caused incorrect prolog and epilog generation in wasm EH scopes. This patch fixes this. This patch is in the same vein with rL333045, which splits `MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and `isEHScopeEntry`. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50653 llvm-svn: 340325
* [GVN] Assign new value number to calls reading memory, if there is no MemDep ↵Florian Hahn2018-08-211-0/+29
| | | | | | | | | | | | | | | | | | | | | | info. Currently we assign the same value number to two calls reading the same memory location if we do not have MemoryDependence info. Without MemDep Info we cannot guarantee that there is no store between the two calls, so we have to assign a new number to the second call. It also adds a new option EnableMemDep to enable/disable running MemoryDependenceAnalysis and also renamed NoLoads to NoMemDepAnalysis to be more explicit what it does. As it also impacts calls that read memory, NoLoads is a bit confusing. Reviewers: efriedma, sebpop, john.brawn, wmi Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D50893 llvm-svn: 340319
* [RegisterCoalscer] Manually remove leftover segments when commuting defKrzysztof Parzyszek2018-08-211-0/+78
| | | | | | | | | | | | | In removeCopyByCommutingDef, segments from the source live range are copied into (and merged with) the segments of the target live range. This is performed for all subranges of the source interval. It can happen that there will be subranges of the target interval that had no corresponding subranges in the source interval, and in such cases these subrages will not be updated. Since the copy being coalesced is about to be removed, these ranges need to be updated by removing the segments that are started by the copy. llvm-svn: 340318
* [NVPTX] Remove ftz variants of cvt with rounding modeBenjamin Kramer2018-08-211-58/+117
| | | | | | | | These do not exist in ptxas, it refuses to compile them. Differential Revision: https://reviews.llvm.org/D51042 llvm-svn: 340317
* Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift ↵Eric Christopher2018-08-211-17/+0
| | | | | | | | immediate instruction" due to it causing a compiler crash on valid. This reverts commit r340016, testcase forthcoming. llvm-svn: 340315
* [X86][SSE] Add non-uniform udiv test that is mostly divide by 1.Simon Pilgrim2018-08-211-0/+178
| | | | | | The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this...... llvm-svn: 340313
* [AST] Remove notion of volatile from alias sets [NFCI]Philip Reames2018-08-211-2/+2
| | | | | | | | | | Volatility is not an aliasing property. We used to model volatile as if it had extremely conservative aliasing implications, but that hasn't been true for several years now. So, it doesn't make sense to be in AliasSet. It also turns out the code is entirely a noop. Outside of the AST code to update it, there was only one user: load store promotion in LICM. L/S promotion doesn't need the check since it walks all the users of the address anyway. It already checks each load or store via !isUnordered which causes us to bail for volatile accesses. (Look at the lines immediately following the two remove asserts.) There is the possibility of some small compile time impact here, but the only case which will get noticeably slower is a loop with a large number of loads and stores to the same address where only the last one we inspect is volatile. This is sufficiently rare it's not worth optimizing for.. llvm-svn: 340312
* Update DBG_VALUE register operand during LiveInterval operationsYury Delendik2018-08-211-0/+110
| | | | | | | | | | | | | | | | | | | Summary: Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in PR16110. However DBG_VALUE register operands are not getting updated. This patch properly resolves the value location. Reviewers: MatzeB, vsk Reviewed By: MatzeB Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D48994 llvm-svn: 340310
* [BypassSlowDivision] Teach bypass slow division not to interfere with div by ↵Craig Topper2018-08-211-68/+26
| | | | | | | | | | | | | | constant where constants have been constant hoisted, but not moved from their basic block DAGCombiner doesn't pay attention to whether constants are opaque before doing the div by constant optimization. So BypassSlowDivision shouldn't introduce control flow that would make DAGCombiner unable to see an opaque constant. This can occur when a div and rem of the same constant are used in the same basic block. it will be hoisted, but not leave the block. Longer term we probably need to look into the X86 immediate cost model used by constant hoisting and maybe not mark div/rem immediates for hoisting at all. This fixes the case from PR38649. Differential Revision: https://reviews.llvm.org/D51000 llvm-svn: 340303
* [AMDGPU] Support idot2 pattern.Farhana Aleen2018-08-211-0/+1850
| | | | | | | | | | | | | | | | Summary: Transform add (mul ((i32)S0.x, (i32)S1.x), add( mul ((i32)S0.y, (i32)S1.y), (i32)S3) => i/udot2((v2i16)S0, (v2i16)S1, (i32)S3) Author: FarhanaAleen Reviewed By: arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D50024 llvm-svn: 340295
* [InstCombine] Add new tests for icmp ugt/ult (add nuw X, C2), CNicola Zaghen2018-08-211-0/+43
| | | | | | Differential Revision: https://reviews.llvm.org/D51040 llvm-svn: 340284
* [X86] Add SSE2 and XOP udiv combine testsSimon Pilgrim2018-08-211-155/+515
| | | | llvm-svn: 340282
* [InstSimplify] use isKnownNeverNaN to fold more fcmp ord/unoSanjay Patel2018-08-212-253/+28
| | | | | | | | | | | Remove duplicate tests from InstCombine that were added with D50582. I left negative tests there to verify that nothing in InstCombine tries to go overboard. If isKnownNeverNaN is improved to handle the FP binops or other cases, we should have coverage under InstSimplify, so we could remove more duplicate tests from InstCombine at that time. llvm-svn: 340279
* [LV] Vectorize loops where non-phi instructions used outside loopAnna Thomas2018-08-211-0/+147
| | | | | | | | | | | | | | | | | | | Summary: Follow up change to rL339703, where we now vectorize loops with non-phi instructions used outside the loop. Note that the cyclic dependency identification occurs when identifying reduction/induction vars. We also need to identify that we do not allow users where the PSCEV information within and outside the loop are different. This was the fix added in rL307837 for PR33706. Reviewers: Ayal, mkuper, fhahn Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D50778 llvm-svn: 340278
* [InstSimplify] add tests for FP uno/ord with nnan; NFCSanjay Patel2018-08-211-0/+424
| | | | | | | | | This is a slight modification of the tests from D50582; change half of the predicates to 'uno' so we have coverage for that side too. All of the positive tests can fold to a constant (true/false), so that should happen in instsimplify. llvm-svn: 340276
* NFC: Add loop vectorizer tests showing various control flow within loop that ↵Anna Thomas2018-08-211-0/+169
| | | | | | skip iterations llvm-svn: 340275
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-214-0/+76
| | | | | | | | | | | | | | | | | Summary: Previously the new llvm.amdgcn.raw/struct.buffer.load/store intrinsics only allowed float types for the data to be loaded or stored, which sometimes meant the frontend needed to generate a bitcast. In this, the new intrinsics copied the old buffer intrinsics. This commit extends the new intrinsics to allow int types as well. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50315 Change-Id: I8202af2d036455553681dcbb3d7d32ae273f8f85 llvm-svn: 340270
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-2114-0/+1414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.buffer.load llvm.amdgcn.raw.buffer.load.format llvm.amdgcn.raw.buffer.load.format.d16 llvm.amdgcn.struct.buffer.load llvm.amdgcn.struct.buffer.load.format llvm.amdgcn.struct.buffer.load.format.d16 llvm.amdgcn.raw.buffer.store llvm.amdgcn.raw.buffer.store.format llvm.amdgcn.raw.buffer.store.format.d16 llvm.amdgcn.struct.buffer.store llvm.amdgcn.struct.buffer.store.format llvm.amdgcn.struct.buffer.store.format.d16 llvm.amdgcn.raw.buffer.atomic.* llvm.amdgcn.struct.buffer.atomic.* with the following changes from the llvm.amdgcn.buffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::BUFFER_* SD nodes always have an index operand, all three offset operands, combined cachepolicy operand, and an extra idxen operand. The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D50306 Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205 llvm-svn: 340269
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-2110-2/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit adds new intrinsics llvm.amdgcn.raw.tbuffer.load llvm.amdgcn.struct.tbuffer.load llvm.amdgcn.raw.tbuffer.store llvm.amdgcn.struct.tbuffer.store with the following changes from the llvm.amdgcn.tbuffer.* intrinsics: * there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set; * there is a combined format arg (dfmt+nfmt) * there is a combined cachepolicy arg (glc+slc) * there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field. The AMDISD::TBUFFER_* SD nodes always have an index operand, all three offset operands, combined format operand, combined cachepolicy operand, and an extra idxen operand. The tbuffer pseudo- and real instructions now also have a combined format operand. The obsolescent llvm.amdgcn.tbuffer.* and llvm.SI.tbuffer.store intrinsics continue to work. V2: Separate raw and struct intrinsics. V3: Moved extract_glc and extract_slc defs to a more sensible place. V4: Rebased on D49995. V5: Only two separate offset args instead of three. V6: Pseudo- and real instructions have joint format operand. V7: Restored optionality of dfmt and nfmt in assembler. V8: Addressed minor review comments. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D49026 Change-Id: If22ad77e349fac3a5d2f72dda53c010377d470d4 llvm-svn: 340268
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-211-0/+58
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
* [X86] Add SSE2 sdiv combine testsSimon Pilgrim2018-08-211-651/+1452
| | | | llvm-svn: 340264
* [DAGCombiner] Reduce load widths of shifted masksSam Parker2018-08-212-39/+528
| | | | | | | | | | | During combining, ReduceLoadWdith is used to combine AND nodes that mask loads into narrow loads. This patch allows the mask to be a shifted constant. This results in a narrow load which is then left shifted to compensate for the new offset. Differential Revision: https://reviews.llvm.org/D50432 llvm-svn: 340261
* [TargetLowering] Add BuildSDiv support for division by one or negone.Simon Pilgrim2018-08-211-115/+92
| | | | | | This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1. llvm-svn: 340260
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-215-0/+896
| | | | | | | | | | Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
* [LICM] Hoist guards with invariant conditionsMax Kazantsev2018-08-212-7/+8
| | | | | | | | | | This patch teaches LICM to hoist guards from the loop if they are guaranteed to execute and if there are no side effects that could prevent that. Differential Revision: https://reviews.llvm.org/D50501 Reviewed By: reames llvm-svn: 340256
* [RegisterCoalescer] Do not assert when trying to remat dead valuesBjorn Pettersson2018-08-211-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: RegisterCoalescer::reMaterializeTrivialDef used to assert that the input register was live in. But as shown by the new coalesce-dead-lanes.mir test case that seems to be a valid scenario. We now return false instead of the assert, simply avoiding to remat the dead def. Normally a COPY of an undef value is eliminated by eliminateUndefCopy(). Although we only do that when the destination isn't a physical register. So the situation above should be limited to the case when we copy an undef value to a physical register. Reviewers: kparzysz, wmi, tpr Reviewed By: kparzysz Subscribers: MatzeB, qcolombet, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D50842 llvm-svn: 340255
* [NFC] Add some LICM testsMax Kazantsev2018-08-211-0/+179
| | | | llvm-svn: 340254
* [IR Verifier] Do not allow bitcast of pointer to vector of pointers and vice ↵Serguei Katkov2018-08-214-0/+49
| | | | | | | | | | | | | | | | | | versa. LangRef for BitCast requires that "The bit sizes of value and the destination type, ty2, must be identical". Currently verifier allows BitCast of pointer to vector of pointers so that the sizes are different. This change fixes that. Reviewers: arsenm Reviewed By: arsenm Subscribers: llvm-commits, wdng Differential Revision: https://reviews.llvm.org/D50886 llvm-svn: 340249
* [AST] Mark invariant.starts as being readonlyPhilip Reames2018-08-211-5/+4
| | | | | | | | These intrinsics are modelled as writing for control flow purposes, but they don't actually write to any location. Marking these - as we did for guards - allows LICM to hoist loads out of loops containing invariant.starts. Differential Revision: https://reviews.llvm.org/D50861 llvm-svn: 340245
* [LICM] Add tests from D50786 [NFC]Philip Reames2018-08-212-0/+34
| | | | | | Exercise more use of volatiles to illustrate that nothing changes as we tweak how we detect them. llvm-svn: 340244
* [LICM][NFC] Add tests from D50730Philip Reames2018-08-211-0/+38
| | | | | | | Landing tests so corresponding change can show effects clearly. see D50730 [AST] Generalize argument specific aliasing llvm-svn: 340243
* [LICM] More tests for D50925 [NFC]Philip Reames2018-08-211-0/+238
| | | | | | This time, the corresponding cases where we can hoist (store-like) calls out of loops. llvm-svn: 340242
* Fix global_metadata_external_comdat.ll testReid Kleckner2018-08-211-2/+2
| | | | llvm-svn: 340240
* [MS Demangler] Demangle special operator 'dynamic initializer'.Zachary Turner2018-08-201-0/+6
| | | | | | | | | | | This is encoded as __E and should print something like "dynamic initializer for 'Foo'(void)" This also adds support for dynamic atexit destructor, which is basically identical but encoded as __F with slightly different description. llvm-svn: 340239
* [MS Demangler] Anonymous namespace hashes can be backreferenced.Zachary Turner2018-08-201-0/+3
| | | | | | | Previously we were not remembering the key values of anonymous namespaces, but we need to do this. llvm-svn: 340238
OpenPOWER on IntegriCloud