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* [x86] avoid flipping sign bits for vector icmp by using known bitsSanjay Patel2017-06-072-104/+34
| | | | | | | | | | | | | | | | If we know that both operands of an unsigned integer vector comparison are non-negative, then it's safe to directly use a signed-compare-greater-than instruction (the only non-equality integer vector compare predicate provided by SSE/AVX). We're intentionally not changing the condition code to signed in order to preserve the existing transforms that use min/max/psubus below here. This should solve PR33276: https://bugs.llvm.org/show_bug.cgi?id=33276 Differential Revision: https://reviews.llvm.org/D33862 llvm-svn: 304909
* [PowerPC] Eliminate integer compare instructions - vol. 5Nemanja Ivanovic2017-06-075-6/+567
| | | | | | | | Adds handling for i64 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33720 llvm-svn: 304907
* [mips] do not use FastISel when -mxgot is presentPetar Jovanovic2017-06-071-0/+3
| | | | | | | | | | | | | | | The clang compiler by default uses FastISel when invoked with -O0, which is also the default. In that case, passing of -mxgot does not get honored, i.e. the code path that is to deal with large got is not taken. Clang produces same output regardless of -mxgot being present or not. This change checks whether -mxgot is passed as an option, and turns off FastISel if it is. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33593 llvm-svn: 304906
* [ARM] GlobalISel: Purge G_SEQUENCEDiana Picus2017-06-075-64/+46
| | | | | | | | | | | | | | | | | According to the commit message from r296921, G_MERGE_VALUES and G_INSERT are to be preferred over G_SEQUENCE. Therefore, stop generating G_SEQUENCE in the ARM backend and remove the code dealing with it. This boils down to the code breaking up double values for the soft float calling convention. Use G_MERGE_VALUES + G_UNMERGE_VALUES instead of G_SEQUENCE + G_EXTRACT for it. This maps very nicely to VMOVDRR + VMOVRRD and simplifies the code in the instruction selector. There's one occurence of G_SEQUENCE left in arm-irtranslator.ll, but that is part of the target-independent code for translating constant structs. Therefore, it is beyond the scope of this commit. llvm-svn: 304902
* [PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic2017-06-079-39/+798
| | | | | | | | Adds handling for i32 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33718 llvm-svn: 304901
* [FileCheck] Don't scan past the closing CHECK-DAG for CHECK-NOT inside CHECK-DAGBenjamin Kramer2017-06-071-0/+9
| | | | | | | If there's enough data in fron of it the skipped region would just become arbitrarily large, and we scan for the CHECK-NOT everywhere. llvm-svn: 304900
* [ARM] GlobalISel: Support G_XORDiana Picus2017-06-074-0/+168
| | | | | | | | | Same as the other binary operators: - legalize to 32 bits - map to GPRs - select to EORrr via TableGen'erated code llvm-svn: 304898
* evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled"Simon Dardis2017-06-078-19/+41
| | | | | | | This reverts commit r301394. It broke some internal buildbots, reverting while the issue is being investigated. llvm-svn: 304896
* [X86][SSE] Fix an issue with PEXTRW/PEXTRB indices during shuffle combiningSimon Pilgrim2017-06-071-40/+4
| | | | | | We were checking that the index was in range of the destination vector type, not the (larger) source vector type llvm-svn: 304894
* [ARM] GlobalISel: Support G_ORDiana Picus2017-06-074-0/+168
| | | | | | | | | Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890
* [Linker] Remove llc usage from link-arm-and-thumb.ll test case.Florian Hahn2017-06-071-9/+6
| | | | | | This fixes a buildbot failure when the ARM target is not built. llvm-svn: 304888
* [ARM] GlobalISel: Support G_ANDDiana Picus2017-06-074-0/+170
| | | | | | | | | This is identical to the support for the other binary operators: - widen to s32 - map into GPR - select ANDrr (via TableGen'erated code) llvm-svn: 304885
* [Linker] Remove warning when linking ARM and Thumb IR modules.Florian Hahn2017-06-074-0/+89
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch updates Triple::isCompatibleWith to make armxx and thumbxx triples compatible, as long as the subarch, vendor, os, envorionment and object format match. Thumb/ARM code generation should be controlled using the thumb-mode per-function target feature rather than by the triple to allow mixing Thumb and ARM functions. D33448 updates Clang's codegen to add thumb-mode for all functions with armxx or thumbxx triples. Reviewers: echristo, t.p.northover, rafael, kristof.beyls, rengolin, tejohnson Reviewed By: tejohnson Subscribers: rinon, eugenis, pcc, srhines, aemerson, mehdi_amini, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33287 llvm-svn: 304884
* [ARM] Create relocations for unconditional branches.Florian Hahn2017-06-071-0/+25
| | | | | | | | | | | | | | | | | | | Summary: Relocations are required for unconditional branches to function symbols with different execution mode. Without this patch, incorrect branches are generated for tail calls between functions with different execution mode. Reviewers: peter.smith, rafael, echristo, kristof.beyls Reviewed By: peter.smith Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33898 llvm-svn: 304882
* Introduce the new feature "abi-breaking-checks" to satisfy -reverse-iterate ↵NAKAMURA Takumi2017-06-074-2/+6
| | | | | | | | | | | | | in llvm/test/Transforms/Util/PredicateInfo/ A few tests in llvm/test/Transforms/Util/PredicateInfo/ are using -reverse-iterate. The option -reverse-iterate is enabled with +Asserts in usual cases, but it can be turned on/off regardless of LLVM_ENABLE_ASSERTIONS. I wonder if this were incompatible to https://reviews.llvm.org/D33908 (r304757). Differential Revision: https://reviews.llvm.org/D33854 llvm-svn: 304851
* [CGP / PowerPC] use direct compares if there's only one load per block in ↵Sanjay Patel2017-06-071-20/+14
| | | | | | | | | | | | | | | | | memcmp() expansion I'd like to enable CGP memcmp expansion for x86, but the output from CGP would regress the special cases (memcmp(x,y,N) != 0 for N=1,2,4,8,16,32 bytes) that we already handle. I'm not sure if we'll actually be able to produce the optimal code given the block-at-a-time limitation in the DAG. We might have to just avoid those special-cases here in CGP. But regardless of that, I think this is a win for the more general cases. http://rise4fun.com/Alive/cbQ Differential Revision: https://reviews.llvm.org/D33963 llvm-svn: 304849
* Introduce -brief command line option to llvm-dwarfdumpAdrian Prantl2017-06-062-0/+133
| | | | | | | | | | | | | This patch introduces a new command line option, called brief, to llvm-dwarfdump. When -brief is used, the attribute forms for the .debug_info section will not be emitted to output. Patch by Spyridoula Gravani! rdar://problem/21474365 Differential Revision: https://reviews.llvm.org/D33867 llvm-svn: 304844
* [PowerPC] auto-generate full checks and increase test coverageSanjay Patel2017-06-061-77/+160
| | | | | | | 3 of the tests were testing exactly the same thing: memcmp(x, y, 16) != 0. I changed that to test 4, 7, and 16 bytes, so we can see how those differ. llvm-svn: 304838
* Added tests for X86InterleavedStore.Evgeny Stupachenko2017-06-062-1/+153
| | | | | | | | | | Reviewers: RKSimon, DavidKreitzer Differential Revision: https://reviews.llvm.org/D33684 Patch by: Aleen Farhana <Farhana.aleen@gmail.com> llvm-svn: 304834
* [SLP] Change extension of the test, NFC.Alexey Bataev2017-06-061-0/+0
| | | | llvm-svn: 304829
* [SLP] Add a test for fix of PR32164, NFC.Alexey Bataev2017-06-061-0/+138
| | | | llvm-svn: 304826
* llc: Add ability to parse mir from stdinMatthias Braun2017-06-061-0/+20
| | | | | | | | - Add -x <language> option to switch between IR and MIR inputs. - Change MIR parser to read from stdin when filename is '-'. - Add a simple mir roundtrip test. llvm-svn: 304825
* Fix PR23384 (part 3 of 3)Evgeny Stupachenko2017-06-0613-89/+93
| | | | | | | | | | | | | Summary: The patch makes instruction count the highest priority for LSR solution for X86 (previously registers had highest priority). Reviewers: qcolombet Differential Revision: http://reviews.llvm.org/D30562 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 304824
* [LVI Printer] Rely on the LVI analysis functions rather than the LVI cacheAnna Thomas2017-06-061-25/+43
| | | | | | | | | | | | | | | | | | | | | | | Summary: LVIPrinter pass was previously relying on the LVICache. We now directly call the the LVI functions which solves the value if the LVI information is not already available in the cache. This has 2 benefits over the printing of LVI cache: 1. higher coverage (i.e. catches errors) in LVI code when cache value is invalidated. 2. relies on the core functions, and not dependent on the LVI cache (which may be scrapped at some point). It would still catch any cache invalidation errors, since we first go through the cache. Reviewers: reames, dberlin, sanjoy Reviewed by: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32135 llvm-svn: 304819
* [WebAssembly] MC: Refactor relocation handlingSam Clegg2017-06-061-10/+10
| | | | | | | | | | | | | The change cleans up and unifies the handling of relocation entries in WasmObjectWriter. Type index relocation no longer need to be handled separately. The only externally visible change should be that type index relocations are no longer grouped at the end. Differential Revision: https://reviews.llvm.org/D33918 llvm-svn: 304816
* MIRPrinter: Avoid assert() when printing empty INLINEASM strings.Matthias Braun2017-06-061-0/+12
| | | | | | | | | | | CodeGen uses MO_ExternalSymbol to represent the inline assembly strings. Empty strings for symbol names appear to be invalid. For now just special case the output code to avoid hitting an `assert()` in `printLLVMNameWithoutPrefix()`. This fixes https://llvm.org/PR33317 llvm-svn: 304815
* [LoopIdiom] Move X86 specific atomic memcpy test to the X86 directoryAnna Thomas2017-06-061-0/+0
| | | | | | | | | | Patch https://reviews.llvm.org/rL304806 was causing failures in Aarch64 and multiple other targets since the test should be run on X86 only. Specifying the target triple is not enough. Moving the testcase to the X86 target directory in LoopIdiom. llvm-svn: 304809
* NewGVN: Fix PR/33187. This is a bug caused by two things:Daniel Berlin2017-06-064-4/+150
| | | | | | | | | | | | | 1. When there is no perfect iteration order, we can't let phi nodes put themselves in terms of things that come later in the iteration order, or we will endlessly cycle (the normal RPO algorithm clears the hashtable to avoid this issue). 2. We are sometimes erasing the wrong expression (causing pessimism) because our equality says loads and stores are the same. We introduce an exact equality function and use it when erasing to make sure we erase only identical expressions, not equivalent ones. llvm-svn: 304807
* [Atomics][LoopIdiom] Recognize unordered atomic memcpyAnna Thomas2017-06-062-0/+480
| | | | | | | | | | | | | | | | | | | | | | Summary: Expanding the loop idiom test for memcpy to also recognize unordered atomic memcpy. The only difference for recognizing an unordered atomic memcpy and instead of a normal memcpy is that the loads and/or stores involved are unordered atomic operations. Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html Patch by Daniel Neilson! Reviewers: reames, anna, skatkov Reviewed By: reames, anna Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33243 llvm-svn: 304806
* [mips] Add madd4 subtarget featurePetar Jovanovic2017-06-061-222/+233
| | | | | | | | | | | Addition of a feature and a predicate used to control generation of madd.fmt and similar instructions. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33400 llvm-svn: 304801
* [IRCE] Canonicalize pre/post loops after the blocks are added into parent loopAnna Thomas2017-06-061-0/+182
| | | | | | | | | | | | | | | | | | | | | Summary: We were canonizalizing the pre loop (into loop-simplify form) before the post loop blocks were added into parent loop. This is incorrect when IRCE is done on a subloop. The post-loop blocks are created, but not yet added to the parent loop. So, loop-simplification on the pre-loop incorrectly updates LoopInfo. This patch corrects the ordering so that pre and post loop blocks are added to parent loop (if any), and then the loops are canonicalized to LCSSA and LoopSimplifyForm. Reviewers: reames, sanjoy, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33846 llvm-svn: 304800
* [X86][AVX1] Split 256-bit vector non-temporal FastISel loads to keep it ↵Simon Pilgrim2017-06-061-6/+30
| | | | | | | | non-temporal (PR32744) Extension to D33728 llvm-svn: 304798
* AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legalTom Stellard2017-06-061-0/+24
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33890 llvm-svn: 304797
* [InstSimplify] Constant fold the new GEP in SimplifyGEPInst.Joey Gouly2017-06-066-6/+60
| | | | llvm-svn: 304784
* Vivek Pandya2017-06-0676-1422/+1438
| | | | | | | | | | | | [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. If -simplify-mir option is passed then MIRPrinter will not print such fields. This change also required some lit test cases in CodeGen directory to be changed. Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D32304 llvm-svn: 304779
* [x86] Stop this test from dirtying the source tree when run.Chandler Carruth2017-06-061-1/+1
| | | | | | The output isn't used anyways. llvm-svn: 304766
* [x86] Add the test for folding stack spills into pextrw.Chandler Carruth2017-06-061-2/+15
| | | | | | | | This is a negative test as pextrw doesn't write to all 32-bits of the spilled GPR. This fold ended up happening when D32684 was landed and covers the regression that motivated reverting it in r304762. llvm-svn: 304763
* [x86] Revert the X86FoldTablesEmitter due to more miscompiles.Chandler Carruth2017-06-063-16/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In testing, we've found yet another miscompile caused by the new tables. And this one is even less clear how to fix (we could teach it to fold a 16-bit load instead of the 32-bit load it wants, or block folding entirely). Also, the approach to excluding instructions seems increasingly to not scale well. I have left a more detailed analysis on the review log for the original patch (https://reviews.llvm.org/D32684) along with suggested path forward. I will land an additional test case that I wrote which covers the code that was miscompiling (folding into the output of `pextrw`) in a subsequent commit to keep this a pure revert. For each commit reverted here, I've restricted the revert to the non-test code touching the x86 fold table emission until the last commit where I did revert the test updates. This means the *new* test cases added for `insertps` and `xchg` remain untouched (and continue to pass). Reverted commits: r304540: [X86] Don't fold into memory operands into insertps in the ... r304347: [TableGen] Adapt more places to getValueAsString now ... r304163: [X86] Don't fold away the memory operand of an xchg. r304123: Don't capture a temporary std::string in a StringRef. r304122: Resubmit "[X86] Adding new LLVM TableGen backend that ..." Original commit was in r304088, and after a string of fixes was reverted previously in r304121 to fix build bots, and then re-landed in r304122. llvm-svn: 304762
* [DWARF] Adding support for the DWARF v5 string offsets table ↵Wolfgang Pieb2017-06-0615-0/+1095
| | | | | | | | | | (consumer/reader part only). Reviewers: dblaikie, aprantl Differential Revision: https://reviews.llvm.org/D32779 llvm-svn: 304759
* CodeGen: Refactor MIR parsingMatthias Braun2017-06-066-15/+22
| | | | | | | | | | | | When parsing .mir files immediately construct the MachineFunctions and put them into MachineModuleInfo. This allows us to get rid of the delayed construction (and delayed error reporting) through the MachineFunctionInitialzier interface. Differential Revision: https://reviews.llvm.org/D33809 llvm-svn: 304758
* CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCIMatthias Braun2017-06-062-3/+3
| | | | | | | | | | | | - Move ISel (and pre-isel) pass construction into TargetPassConfig - Extract AsmPrinter construction into a helper function Putting the ISel code into TargetPassConfig seems a lot more natural and both changes together make make it easier to build custom pipelines involving .mir in an upcoming commit. This moves MachineModuleInfo to an earlier place in the pass pipeline which shouldn't have any effect. llvm-svn: 304754
* [x86] fix over-specific triple; NFCSanjay Patel2017-06-061-18/+18
| | | | | | | | There's nothing darwin-specific in these tests, and using that setting causes extra phantom diffs when the auto-generated check lines are regenerated today. llvm-svn: 304753
* [InlineSpiller] Don't spill fully undef valuesQuentin Colombet2017-06-051-0/+67
| | | | | | | | | | Althought it is not wrong to spill undef values, it is useless and harms both code size and runtime. Before spilling a value, check that its content actually matters. http://www.llvm.org/PR33311 llvm-svn: 304752
* RenameIndependentSubregs: Fix handling of undef tied operandsMatt Arsenault2017-06-051-0/+69
| | | | | | | | If a tied source operand was undef, it would be replaced but not update the other tied operand, which would end up using different virtual registers. llvm-svn: 304747
* [GlobalISel] IRTranslator: Add MachineMemOperand to target memory intrinsicsVolkan Keles2017-06-051-0/+12
| | | | | | | | | | | | Reviewers: qcolombet, ab, t.p.northover, aditya_nandakumar, dsanders Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33724 llvm-svn: 304743
* [SelectionDAG] Update the dominator after splitting critical edges.Davide Italiano2017-06-051-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Running `llc -verify-dom-info` on the attached testcase results in a crash in the verifier, due to a stale dominator tree. i.e. DominatorTree is not up to date! Computed: =============================-------------------------------- Inorder Dominator Tree: [1] %safe_mod_func_uint8_t_u_u.exit.i.i.i {0,7} [2] %lor.lhs.false.i61.i.i.i {1,2} [2] %safe_mod_func_int8_t_s_s.exit.i.i.i {3,6} [3] %safe_div_func_int64_t_s_s.exit66.i.i.i {4,5} Actual: =============================-------------------------------- Inorder Dominator Tree: [1] %safe_mod_func_uint8_t_u_u.exit.i.i.i {0,9} [2] %lor.lhs.false.i61.i.i.i {1,2} [2] %safe_mod_func_int8_t_s_s.exit.i.i.i {3,8} [3] %safe_div_func_int64_t_s_s.exit66.i.i.i {4,5} [3] %safe_mod_func_int8_t_s_s.exit.i.i.i.lor.lhs.false.i61.i.i.i_crit_edge {6,7} This is because in `SelectionDAGIsel` we split critical edges without updating the corresponding dominator for the function (and we claim in `MachineFunctionPass::getAnalysisUsage()` that the domtree is preserved). We could either stop preserving the domtree in `getAnalysisUsage` or tell `splitCriticalEdge()` to update it. As the second option is easy to implement, that's the one I chose. Differential Revision: https://reviews.llvm.org/D33800 llvm-svn: 304742
* test: fix hexagon buildSaleem Abdulrasool2017-06-053-0/+3
| | | | | | Add a x86-registered-target requirement to the tests. llvm-svn: 304739
* [CodeView] Handle Cross Module Imports and Exports.Zachary Turner2017-06-052-0/+84
| | | | | | | | | | | | | | | While it's not entirely clear why a compiler or linker might put this information into an object or PDB file, one has been spotted in the wild which was causing llvm-pdbdump to crash. This patch adds support for reading-writing these sections. Since I don't know how to get one of the native tools to generate this kind of debug info, the only test here is one in which we feed YAML into the tool to produce a PDB and then spit out YAML from the resulting PDB and make sure that it matches. llvm-svn: 304738
* AMDGPU: Remove deprecated and unused elf definitionsKonstantin Zhuravlyov2017-06-056-69/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D33689 llvm-svn: 304737
* CodeGen: add support for emitting ObjC image infoSaleem Abdulrasool2017-06-053-0/+42
| | | | | | | | | This ensures that we can emit the ObjC Image Info structure on COFF and ELF as well. The frontend already would attempt to emit this information but would get dropped when generating assembly or an object file. llvm-svn: 304736
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