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* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-227-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. NOTE: re-commit by fixing a failure in Codegen/AMDGPU/llvm.dbg.value.ll Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256282
* Also add unnamed_addr to functions.Rafael Espindola2015-12-221-0/+6
| | | | llvm-svn: 256281
* Delete dead GlobalAliases.Rafael Espindola2015-12-223-3/+6
| | | | llvm-svn: 256276
* Revert "AMDGPU/SI: Use flat for global load/store when targeting HSA"Rafael Espindola2015-12-227-39/+15
| | | | | | | | This reverts commit r256273. It broke CodeGen/AMDGPU/llvm.dbg.value.ll llvm-svn: 256275
* AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang2015-12-227-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: For some reason doing executing an MUBUF instruction with the addr64 bit set and a zero base pointer in the resource descriptor causes the memory operation to be dropped when the shader is executed using the HSA runtime. This kind of MUBUF instruction is commonly used when the pointer is stored in VGPRs. The base pointer field in the resource descriptor is set to zero and and the pointer is stored in the vaddr field. This patch resolves the issue by only using flat instructions for global memory operations when targeting HSA. This is an overly conservative fix as all other configurations of MUBUF instructions appear to work. Reviewers: tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15543 llvm-svn: 256273
* [BPI] Replace weights by probabilities in BPI.Cong Hou2015-12-222-6/+6
| | | | | | | | | | | | This patch removes all weight-related interfaces from BPI and replace them by probability versions. With this patch, we won't use edge weight anymore in either IR or MC passes. Edge probabilitiy is a better representation in terms of CFG update and validation. Differential revision: http://reviews.llvm.org/D15519 llvm-svn: 256263
* Remove deprecated llvm.experimental.gc.result.{int,float,ptr} intrinsics.Manuel Jacob2015-12-221-2/+2
| | | | | | | | | | | | | | Summary: These were deprecated 11 months ago when a generic llvm.experimental.gc.result intrinsic, which works for all types, was added. Reviewers: sanjoy, reames Subscribers: sanjoy, chenli, llvm-commits Differential Revision: http://reviews.llvm.org/D15719 llvm-svn: 256262
* [RS4GC] Fix crash in the case that a live variable has a constant base.Manuel Jacob2015-12-222-0/+39
| | | | | | | | | | | | | | | | | | | Summary: Previously, RS4GC crashed in CreateGCRelocates() because it assumed that every base is also in the array of live variables, which isn't true if a live variable has a constant base. This change fixes the crash by making sure CreateGCRelocates() won't try to relocate a live variable with a constant base. This would be unnecessary anyway because anything with a constant base won't move. Reviewers: reames Subscribers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D15556 llvm-svn: 256252
* [AArch64] Promote loads from storedJun Bum Lim2015-12-223-5/+671
| | | | | | | | | | | | | | | | | | | | This is a recommit of r256004 which was reverted in r256160. The issue was the incorrect promotion for half and byte loads transformed into mov instructions. This fix will replace half and byte type loads only with bit field extracts. Original commit message: This change promotes load instructions which directly read from stored by replacing them with mov instructions. If the store is wider than the load, the load will be replaced with a bitfield extract. For example : STRWui %W1, %X0, 1 %W0 = LDRHHui %X0, 3 becomes STRWui %W1, %X0, 1 %W0 = UBFMWri %W1, 16, 31 llvm-svn: 256249
* [X86][AVX512] Add rcp14 and rsqrt14 intrinsicsAsaf Badouh2015-12-221-0/+181
| | | | | | Differential Revision: http://reviews.llvm.org/D15414 llvm-svn: 256237
* [ASMPrinter] Fix missing handling of DW_OP_bit_pieceKeno Fischer2015-12-221-0/+64
| | | | | | | | In r256077, I added printing for DIExpressions in DEBUG_VALUE comments, but neglected to handle DW_OP_bit_piece operands. Thanks to Mikael Holmen and Joerg Sonnenberger for spotting this. llvm-svn: 256236
* [MC] Don't use the architecture to govern which object file format to useDavid Majnemer2015-12-223-11/+11
| | | | | | | | | | | InitMCObjectFileInfo was trying to override the triple in awkward ways. For example, a triple specifying COFF but not Windows was forced as ELF. This makes it easy for internal invariants to get violated, such as those which triggered PR25912. This fixes PR25912. llvm-svn: 256226
* Partial fix for PR25912, see comment 13. Should fix the sanitizer bootstrap botKostya Serebryany2015-12-221-1/+1
| | | | llvm-svn: 256225
* Handle empty Subprogram list when linking metadata.Teresa Johnson2015-12-221-0/+17
| | | | | | | | Use an iterator that handles an empty subprogram list. Fixes PR25915. llvm-svn: 256224
* Determine callee's hotness and adjust threshold based on that. NFC.Easwaran Raman2015-12-222-0/+78
| | | | | | | | | | This uses the same criteria used in CFE's CodeGenPGO to identify hot and cold callees and uses values of inlinehint-threshold and inlinecold-threshold respectively as the thresholds for such callees. Differential Revision: http://reviews.llvm.org/D15245 llvm-svn: 256222
* [safestack] Add option for non-TLS unsafe stack pointer.Evgeniy Stepanov2015-12-221-0/+5
| | | | | | | | | | | | | This patch adds an option, -safe-stack-no-tls, for using normal storage instead of thread-local storage for the unsafe stack pointer. This can be useful when SafeStack is applied to an operating system kernel. http://reviews.llvm.org/D15673 Patch by Michael LeMay. llvm-svn: 256221
* [PGO] Fix another comdat related issue for COFFXinliang David Li2015-12-221-3/+3
| | | | | | | | | | | The linker requires that a comdat section must be associated with a another comdat section that precedes it. This means the comdat section's name needs to use the profile name var's name. Patch tested by Johan Engelen. llvm-svn: 256220
* Fix test case comment (NFC)Xinliang David Li2015-12-211-2/+2
| | | | llvm-svn: 256206
* [cfi] Fix LowerBitSets on 32-bit targets.Evgeniy Stepanov2015-12-211-0/+21
| | | | | | | This code attempts to truncate IntPtrTy to i32, which may be the same type. llvm-svn: 256205
* [MC, COFF] Support link /incremental conditionallyDavid Majnemer2015-12-213-4/+4
| | | | | | | | | | | | | | | | Today, we always take into account the possibility that object files produced by MC may be consumed by an incremental linker. This results in us initialing fields which vary with time (TimeDateStamp) which harms hermetic builds (e.g. verifying a self-host went well) and produces sub-optimal code because we cannot assume anything about the relative position of functions within a section (call sites can get redirected through incremental linker thunks). Let's provide an MCTargetOption which controls this behavior so that we can disable this functionality if we know a-priori that the build will not rely on /incremental. llvm-svn: 256203
* Enhance BranchProbabilityInfo::calcUnreachableHeuristics for InvokeInstJun Bum Lim2015-12-214-4/+51
| | | | | | | | | | | | | | | This is recommit of r256028 with minor fixes in unittests: CodeGen/Mips/eh.ll CodeGen/Mips/insn-zero-size-bb.ll Original commit message: When identifying blocks post-dominated by an unreachable-terminated block in BranchProbabilityInfo, consider only the edge to the normal destination block if the terminator is InvokeInst and let calcInvokeHeuristics() decide edge weights for the InvokeInst. llvm-svn: 256202
* Resubmit r256193 with test fix: assertion failure analyzedXinliang David Li2015-12-211-0/+7
| | | | llvm-svn: 256201
* Revert r256193: build bot failure triggeredXinliang David Li2015-12-211-8/+0
| | | | llvm-svn: 256198
* [X86][SSE] Transform truncations between vectors of integers into ↵Cong Hou2015-12-212-154/+193
| | | | | | | | | | | | | | | | | | | X86ISD::PACKUS/PACKSS operations during DAG combine. This patch transforms truncation between vectors of integers into X86ISD::PACKUS/PACKSS operations during DAG combine. We don't do it in lowering phase because after type legalization, the original truncation will be turned into a BUILD_VECTOR with each element that is extracted from a vector and then truncated, and from them it is difficult to do this optimization. This greatly improves the performance of truncations on some specific types. Cost table is updated accordingly. Differential revision: http://reviews.llvm.org/D14588 llvm-svn: 256194
* [PGO] Fix profile var comdat generation problem with COFFXinliang David Li2015-12-211-0/+8
| | | | | | | | | | | When targeting COFF, it is required that a comdat section to have a global obj with the same name as the comdat (except for comdats with select kind to be associative). This fix makes sure that the comdat is keyed on the data variable for COFF. Also improved test coverage for this. llvm-svn: 256193
* [ValueTracking] Properly handle non-sized types in isAligned function.Michael Zolotukhin2015-12-211-0/+20
| | | | | | | | | | Reviewers: apilipenko, reames, sanjoy, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15597 llvm-svn: 256192
* Fix PR24563 (LiveDebugVariables unconditionally propagates all DBG_VALUEs)Adrian Prantl2015-12-212-2/+102
| | | | | | | | | | | | | | | | LiveDebugVariables unconditionally propagates all DBG_VALUE down the dominator tree, which happens to work fine if there already is another DBG_VALUE or the DBG_VALUE happends to describe a single-assignment vreg but is otherwise wrong if the DBG_VALUE is coming from only one of the predecessors. In r255759 we introduced a proper data flow analysis scheduled after LiveDebugVariables that correctly propagates DBG_VALUEs across basic block boundaries. With the new pass in place, the incorrect propagation in LiveDebugVariables can be retired witout loosing any of the benefits where LiveDebugVariables happened to do the right thing. llvm-svn: 256188
* Convert the CodeGen/ARM/sched-it-debug-nodes.ll testcase from IR -> MIR.Adrian Prantl2015-12-212-88/+160
| | | | | | | NFC PR24563 llvm-svn: 256187
* Teach ARMLoadStoreOptimizer to ignore DBG_VALUE instructions when mergingAdrian Prantl2015-12-211-0/+165
| | | | | | | | | instructions. As noted in PR24563. rdar://problem/23963293 llvm-svn: 256183
* AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VITom Stellard2015-12-211-9/+14
| | | | | | | | | | | | | | | Summary: These register has different encodings on CI and VI, so we add pseudo FLAT_SCRACTH registers to be used before MC, and subtarget specific registers to be used by the MC layer. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15661 llvm-svn: 256178
* [AArch64] Add additional extract-extend patterns for smovMatthew Simpson2015-12-211-9/+8
| | | | | | | | | | | | | This patch adds to the target description two additional patterns for matching extract-extend operations to SMOV. The patterns catch the v16i8-to-i64 and v8i16-to-i64 cases. The existing patterns miss these cases because the extracted elements must first be legalized to i32, resulting in any_extend nodes. This was originally implemented as a DAG combine (r255895), but was reverted due to failing out-of-tree tests. llvm-svn: 256176
* Add testcase for r256161 (PR25907)Teresa Johnson2015-12-211-0/+28
| | | | llvm-svn: 256174
* Revert "[AArch64] Promote loads from stores"Jun Bum Lim2015-12-213-671/+5
| | | | | | This reverts commit r256004 due to a failure in cortex-a53. llvm-svn: 256160
* [AArch64] Enable PostRAScheduler for AArch64 generic build.Chad Rosier2015-12-2121-29/+29
| | | | | | | | | Disable post-ra scheduler for perturbed tests to appease the bots and to preserve the history of the tests. http://reviews.llvm.org/D15652 llvm-svn: 256158
* AVX512BW: Enable AND/OR/XOR vector byte/word paked operation by promoting to ↵Igor Breger2015-12-211-28/+136
| | | | | | qword that natively suppored. llvm-svn: 256157
* Implemented Support of IA interrupt and exception handlers:Amjad Aboud2015-12-212-0/+165
| | | | | | | | http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html Differential Revision: http://reviews.llvm.org/D15567 llvm-svn: 256155
* [mips][microMIPS] Implement DERET and DI instructions and check size operand ↵Zlatko Buljan2015-12-219-9/+52
| | | | | | | | for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
* check-llvm: Tweak the feature "timestamps" for autoconf.NAKAMURA Takumi2015-12-212-1/+2
| | | | | | Note, ENABLE_TIMESTAMPS is either 1 or 0 in Makefile.config. llvm-svn: 256138
* [MC, COFF] Unbreak support for COFF timestampsDavid Majnemer2015-12-213-1/+8
| | | | | | | | | | | | | | | | | | | Support for COFF timestamps was unintentionally broken in r246905 when it was conditionally available depending on whether or not LLVM was configured with LLVM_ENABLE_TIMESTAMPS. However, Config/config.h was never included which essentially broke the feature. Due to lax testing, the breakage was never identified until we observed strange failures during incremental links of Chromium. This issue is resolved by simply including Config/config.h in WinCOFFObjectWriter and teaching lit that the MC/COFF/timestamp.s test is conditionally supported depending on LLVM_ENABLE_TIMESTAMPS. With this in place, we can strengthen the test to ensure that it will not accidentally get broken in the future. This fixes PR25891. llvm-svn: 256137
* [X86] Prevent constant hoisting for a couple compare immediates that the ↵Craig Topper2015-12-201-0/+25
| | | | | | | | | | selection DAG knows how to optimize into a shift. This allows "icmp ugt %a, 4294967295" and "icmp uge %a, 4294967296" to be optimized into right shifts by 32 which can fold the immediate into the shift instruction. These patterns show up with some regularity in real code. Unfortunately, since getImmCost can't see the icmp predicate we can't be tell if we're only catching these specific cases. llvm-svn: 256126
* Fix a bug in test case -- duplicate entriesXinliang David Li2015-12-201-21/+0
| | | | llvm-svn: 256117
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions for ↵Weiming Zhao2015-12-205-11/+18
| | | | | | | | | | | | | | | | | Thumb2 Summary: r250697 fixed the mapping for ARM mode. We have to do the same for Thumb2 otherwise the same llvm.arm.ssat() will generate different saturating amount for ARM and Thumb. r250697: http://reviews.llvm.org/rL250697 Reviewers: rmaprath Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15653 llvm-svn: 256115
* Revert r219171, "llvm/test/lit.cfg: Suppress dwarf stuff for targeting ↵NAKAMURA Takumi2015-12-201-2/+1
| | | | | | | | x86_64-mingw32 while investigating since r219108." It has been fixed since r219280 by David Majnemer. llvm-svn: 256112
* Nonnull elements in OperandBundleCallSites are not all InstructionsSanjoy Das2015-12-191-0/+36
| | | | | | | | | | `CloneAndPruneIntoFromInst` sometimes RAUW's dead instructions with `undef` before erasing them (to avoid deleting instructions that still have uses). This changes the `WeakVH` in `OperandBundleCallSites` to hold an `undef`, and we need to guard for this situation in eventuality in `llvm::InlineFunction`. llvm-svn: 256110
* [Deopt bundles] Fix a test caseSanjoy Das2015-12-191-1/+1
| | | | | | | The `CHECK-NOT` line was incorrect, and would not have caught a breakage. llvm-svn: 256109
* WebAssembly: add vtable testJF Bastien2015-12-191-0/+171
| | | | | | The test will mainly be useful to check that the .s file assembles and relocates properly because vtables reference functions in their data section. llvm-svn: 256102
* Remove double blanks. NFC.Manuel Jacob2015-12-191-7/+7
| | | | llvm-svn: 256100
* Hopefully fix debug-info-blocks.ll test on win32 botKeno Fischer2015-12-191-1/+1
| | | | | | | | llc_dwarf adds an mtriple, which forces this to use COFF, causing the test to fail. Hopefully using regular llc without the triple will work fine everywhere llvm-svn: 256084
* AMDGPU/SI: Fix implemenation of isSourceOfDivergence() for graphics shadersTom Stellard2015-12-192-0/+18
| | | | | | | | | | | | | | | Summary: The analysis of shader inputs was completely wrong. We were passing the wrong index to AttributeSet::hasAttribute() and the logic for which inputs where in SGPRs was wrong too. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15608 llvm-svn: 256082
* [RS4GC] Remove an overly strong assertionPhilip Reames2015-12-191-0/+35
| | | | | | As shown by the included test case, it's reasonable to end up with constant references during base pointer calculation. The code actually handled this case just fine, we only had the assert to help isolate problems under the belief that constant references shouldn't be present in IR generated by managed frontends. This turned out to be wrong on two fronts: 1) Manual Jacobs is working on a language with constant references, and b) we found a case where the optimizer does create them in practice. llvm-svn: 256079
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