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* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+40
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-0/+31
| | | | | | assembly. llvm-svn: 175036
* Finish obviously broken thought.Eric Christopher2013-02-131-1/+1
| | | | llvm-svn: 175035
* [tsan] disable load widening in ThreadSanitizer modeKostya Serebryany2013-02-131-0/+26
| | | | llvm-svn: 175034
* Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren2013-02-131-0/+173
| | | | | | | | | | | | | | RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs without emitting them at the end. We fix this by removing LDV from RegisterCoalescer. Also add an assertion to make sure we call emitDebugValues if DBG_VALUEs are removed at runOnMachineFunction. rdar://problem/13183203 Reviewed by Andy & Jakob llvm-svn: 175023
* Remove target-specific info from the testcase for DWARF/pubnames.Krzysztof Parzyszek2013-02-121-3/+0
| | | | llvm-svn: 174992
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-122-6/+20
| | | | | | | | | | | | | | This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 llvm-svn: 174983
* Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek2013-02-121-0/+127
| | | | | | option "generate-dwarf-pubnames" to control it, set to "false" by default. llvm-svn: 174981
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-121-0/+6
| | | | llvm-svn: 174979
* Fix the lit test added in r174972Paul Redmond2013-02-121-2/+2
| | | | | | Patch by: Kevin Schoedel llvm-svn: 174974
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-0/+19
| | | | | | instructions. llvm-svn: 174973
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-0/+15
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
* [NVPTX] Disable vector registersJustin Holewinski2013-02-121-0/+66
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. llvm-svn: 174968
* [asan] fix tests for the new ABIKostya Serebryany2013-02-122-4/+4
| | | | llvm-svn: 174959
* Test for string attributes and for attribute group output.Bill Wendling2013-02-121-0/+28
| | | | llvm-svn: 174954
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+40
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 llvm-svn: 174933
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-0/+27
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-0/+26
| | | | | | Part of rdar://12470373 llvm-svn: 174926
* Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> ↵Michael Ilseman2013-02-111-1/+7
| | | | | | bitcast X to ... llvm-svn: 174905
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-117-0/+1528
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* Remove trailing whitespaceMichael Ilseman2013-02-111-7/+8
| | | | llvm-svn: 174903
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-0/+13
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ↵Justin Holewinski2013-02-111-0/+21
| | | | | | is not valid in this case, and was causing incorrect optimizations. llvm-svn: 174896
* AArch64: generate dwarfdump test rather than include .o in subversionTim Northover2013-02-113-16/+33
| | | | llvm-svn: 174891
* AArch64: Add basic relocation processing for llvm-dwarfdump.Tim Northover2013-02-112-0/+16
| | | | | | | This allows llvm-dwarfdump to handle the relocations needed, at least for LLVM-produced code. llvm-svn: 174874
* AArch64: Undo change to how test was runTim Northover2013-02-111-1/+2
| | | | | | This broke on Windows, presumably due to interleaving of output streams. llvm-svn: 174873
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-111-501/+504
| | | | | | | | | This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. llvm-svn: 174871
* FileCheck-ize the tests.Bill Wendling2013-02-116-28/+44
| | | | llvm-svn: 174865
* [tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany2013-02-111-0/+10
| | | | llvm-svn: 174864
* LSR IVChain improvement.Andrew Trick2013-02-092-20/+94
| | | | | | | | | Handle chains in which the same offset is used for both loads and stores to the same array. Fixes rdar://11410078. llvm-svn: 174789
* Dwarf: do not use line_table_start in at_stmt_list since we do not always emit Manman Ren2013-02-091-1/+1
| | | | | | line table entries in assembly. llvm-svn: 174785
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-081-0/+30
| | | | | | | | | | same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. llvm-svn: 174747
* DAGCombiner: Constant folding around pre-increment loads/storesHal Finkel2013-02-081-0/+47
| | | | | | | | | | | Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. llvm-svn: 174746
* Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson2013-02-082-20/+1
| | | | | | | | | | | | Aside from the question of whether we report a warning or an error when we can't satisfy a requested stack object alignment, the current implementation of this is not good. We're not providing any source location in the diagnostics and the current warning is not connected to any warning group so you can't control it. We could improve the source location somewhat, but we can do a much better job if this check is implemented in the front-end, so let's do that instead. <rdar://problem/13127907> llvm-svn: 174741
* Refine fix to bug 15041.Bill Schmidt2013-02-081-0/+16
| | | | | | | | | Thanks to help from Nadav and Hal, I have a more reasonable (and even correct!) approach. This specifically penalizes the insertelement and extractelement operations for the performance hit that will occur on PowerPC processors. llvm-svn: 174725
* [SimplifyLibCalls] Library call simplification doen't work if the call site Chad Rosier2013-02-081-0/+48
| | | | | | | | isn't using the default calling convention. However, if the transformation is from a call to inline IR, then the calling convention doesn't matter. rdar://13157990 llvm-svn: 174724
* ARM cost model: Address computation in vector mem ops not freeArnold Schwaighofer2013-02-083-3/+86
| | | | | | | | | | | | | | | Adds a function to target transform info to query for the cost of address computation. The cost model analysis pass now also queries this interface. The code in LoopVectorize adds the cost of address computation as part of the memory instruction cost calculation. Only there, we know whether the instruction will be scalarized or not. Increase the penality for inserting in to D registers on swift. This becomes necessary because we now always assume that address computation has a cost and three is a closer value to the architecture. radar://13097204 llvm-svn: 174713
* Update tests for DWARF parser: store sources next to pre-built object files ↵Alexey Samsonov2013-02-0819-39/+132
| | | | | | and provide build instructions llvm-svn: 174711
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-0/+61
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* Revert "Have InstCombine call SipmlifyCall when handling calls. Test case ↵Andrew Trick2013-02-081-14/+2
| | | | | | | | | | included." This reverts commit 3854a5d90fee52af1065edbed34521fff6cdc18d. This causes a clang unit test to hang: vtable-available-externally.cpp. llvm-svn: 174692
* Have InstCombine call SipmlifyCall when handling calls. Test case included.Michael Ilseman2013-02-071-2/+14
| | | | llvm-svn: 174675
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-071-0/+8
| | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. llvm-svn: 174657
* Identify and simplify idempotent intrinsics. Test case included.Michael Ilseman2013-02-071-0/+51
| | | | llvm-svn: 174650
* [Object][ELF] Fix crash on no dynamic section.Michael J. Spencer2013-02-071-0/+2
| | | | llvm-svn: 174639
* ARM cost model: Add costs for vector selectsArnold Schwaighofer2013-02-071-0/+54
| | | | | | | | Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 llvm-svn: 174631
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-073-15/+150
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Add tests for unsupported condition codes.Tom Stellard2013-02-071-0/+83
| | | | | | All of the le and lt variants are unsupported. llvm-svn: 174608
* R600: Fix assembly name for SETGT_INTTom Stellard2013-02-071-1/+1
| | | | llvm-svn: 174607
* Remove this testcase until I can figure out how to properly conditionalize it.Owen Anderson2013-02-071-43/+0
| | | | llvm-svn: 174591
* Another attempt at getting the XFAIL line right for this test.Owen Anderson2013-02-071-1/+1
| | | | llvm-svn: 174588
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