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* MIR Serialization: Serialize the '.cfi_offset' CFI instruction.Alex Lorenz2015-07-233-0/+135
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243062
* WebAssembly: test that valid -mcpu flags are accepted.JF Bastien2015-07-231-0/+15
| | | | | | | | | | Summary: AArch64 has a similar test. Subscribers: sunfish, aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11479 llvm-svn: 243058
* fix crash in machine trace metrics due to processing dbg_value instructions ↵Sanjay Patel2015-07-231-0/+62
| | | | | | | | | | | | | | | | | | | (PR24199) The test in PR24199 ( https://llvm.org/bugs/show_bug.cgi?id=24199 ) crashes because machine trace metrics was not ignoring dbg_value instructions when calculating data dependencies. The machine-combiner pass asks machine trace metrics to calculate an instruction trace, does some reassociations, and calls MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() along with MachineTraceMetrics::invalidate(). The dbg_value instructions have their operands invalidated, but the instructions are not expected to be deleted. On a subsequent loop iteration of the machine-combiner pass, machine trace metrics would be called again and die while accessing the invalid debug instructions. Differential Revision: http://reviews.llvm.org/D11423 llvm-svn: 243057
* Moving tests in to X86 directory.Colin LeMahieu2015-07-232-0/+0
| | | | llvm-svn: 243049
* Using an input object file instead of trying to generate an object file.Colin LeMahieu2015-07-232-5/+2
| | | | llvm-svn: 243044
* Specifying a test triple.Colin LeMahieu2015-07-231-1/+2
| | | | llvm-svn: 243042
* [llvm-objdump] Add -D and --disassemble-all flags that attempt disassembly ↵Colin LeMahieu2015-07-231-0/+6
| | | | | | on all sections instead of just text sections. llvm-svn: 243041
* [Scalarizer] Fix potential for stale data in Scattered across invocationsMatt Wala2015-07-231-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Scalarizer has two data structures that hold information about changes to the function, Gathered and Scattered. These are cleared in finish() at the end of runOnFunction() if finish() detects any changes to the function. However, finish() was checking for changes by only checking if Gathered was non-empty. The function visitStore() only modifies Scattered without touching Gathered. As a result, Scattered could have ended up having stale data if Scalarizer only scalarized store instructions. Since the data in Scattered is used during the execution of the pass, this introduced dangling pointer errors. The fix is to check whether both Scattered and Gathered are empty before deciding what to do in finish(). This also fixes a problem where the Function can be modified although the pass returns false. Reviewers: rnk Subscribers: rnk, srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D10459 llvm-svn: 243040
* This patch eanble register coalescing to coalesce the following:Weiming Zhao2015-07-231-0/+18
| | | | | | | | | | %vreg2<def> = MOVi32imm 1; GPR32:%vreg2 %W1<def> = COPY %vreg2; GPR32:%vreg2 into: %W1<def> = MOVi32imm 1 Patched by Lawrence Hu (lawrence@codeaurora.org) llvm-svn: 243033
* NFC. Explicitly specify attributes in BasicAA/cs-cs.ll test.Igor Laevsky2015-07-231-1/+4
| | | | | | This will simplify verifying correctness for a changes which modify attributes. llvm-svn: 243016
* [X86] Allow load folding into PUSH instructionsMichael Kuperstein2015-07-231-0/+40
| | | | | | | | | | Adds pushes to the folding tables. This also required a fix to the TD definition, since the memory forms of the push instructions did not have the right mayLoad/mayStore flags. Differential Revision: http://reviews.llvm.org/D11340 llvm-svn: 243010
* [asan] Rename the ABI versioning symbol to '__asan_version_mismatch_check' ↵Kuba Brecka2015-07-231-1/+1
| | | | | | | | | | instead of abusing '__asan_init' We currently version `__asan_init` and when the ABI version doesn't match, the linker gives a `undefined reference to '__asan_init_v5'` message. From this, it might not be obvious that it's actually a version mismatch error. This patch makes the error message much clearer by changing the name of the undefined symbol to be `__asan_version_mismatch_check_xxx` (followed by the version string). We obviously don't want the initializer to be named like that, so it's a separate symbol that is used only for the purpose of version checking. Reviewed at http://reviews.llvm.org/D11004 llvm-svn: 243003
* [X86] Fix order of operands for ins and outs instructions when parsing intel ↵Michael Kuperstein2015-07-231-0/+14
| | | | | | | | | syntax Patch by: marina.yatsina@intel.com Differential Revision: http://reviews.llvm.org/D11337 llvm-svn: 243001
* Support printing relocations in files with no section table.Rafael Espindola2015-07-232-0/+12
| | | | llvm-svn: 242998
* X86: Fixed assertion failure in 32-bit modeElena Demikhovsky2015-07-231-0/+11
| | | | | | | | | | The DAG Node "SCALAR_TO_VECTOR" may be created if the type of the scalar element is legal. Added a check for the scalar type before creating this node. Added a test that fails with assertion on the current version. Differential Revision: http://reviews.llvm.org/D11413 llvm-svn: 242994
* Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."Chandler Carruth2015-07-2310-3576/+29
| | | | | | | | | | This commit broke the build. Numerous build bots broken, and it was blocking my progress so reverting. It should be trivial to reproduce -- enable the BPF backend and it should fail when running llvm-tblgen. llvm-svn: 242992
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer ↵Igor Breger2015-07-2310-29/+3576
| | | | | | | | | | Truncate with/without saturation Added tests for DAG lowering ,encoding and intrinsic Differential Revision: http://reviews.llvm.org/D11218 llvm-svn: 242990
* AVX : Fix ISA disabling in case AVX512VL , some instructions should be ↵Igor Breger2015-07-231-0/+1
| | | | | | | | | | disabled only if AVX512BW and AVX512VL present. Tests added. Differential Revision: http://reviews.llvm.org/D11414 llvm-svn: 242987
* Refactor duplicated code and check for invalid symbol table size.Rafael Espindola2015-07-232-0/+4
| | | | llvm-svn: 242981
* [dsymutil] Check archive members timestamps.Frederic Riss2015-07-222-0/+27
| | | | | | | | | The debug map contains the timestamp of the object files in references. We do not check these in the general case, but it's really useful if you have archives where different versions of an object file have been appended. This allows llvm-dsymutil to find the right one. llvm-svn: 242965
* [ConstantFolding] Support folding loads from a GlobalAliasDavid Majnemer2015-07-221-0/+11
| | | | | | | | | | | | | | The MSVC ABI requires that we generate an alias for the vtable which means looking through a GlobalAlias which cannot be overridden improves our ability to devirtualize. Found while investigating PR20801. Patch by Andrew Zhogin! Differential Revision: http://reviews.llvm.org/D11306 llvm-svn: 242955
* Force the gnu archive format to fix the test on darwin.Rafael Espindola2015-07-221-1/+1
| | | | llvm-svn: 242949
* WebAssembly: basic bitcode → assembly CodeGen testJF Bastien2015-07-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
* MIR Serialization: Serialize the machine instruction's debug location.Alex Lorenz2015-07-222-0/+126
| | | | llvm-svn: 242938
* Fix fetching the symbol table of a thin archive.Rafael Espindola2015-07-221-0/+11
| | | | | | We were trying to read it as an external file. llvm-svn: 242926
* Identify thin archives as archives.Rafael Espindola2015-07-221-0/+9
| | | | llvm-svn: 242921
* MIR Serialization: Serialize the metadata machine operands.Alex Lorenz2015-07-223-0/+186
| | | | llvm-svn: 242916
* [ARM] Make the frame lowering code ready for shrink-wrapping.Quentin Colombet2015-07-222-0/+1053
| | | | | | | | Shrink-wrapping can now be tested on ARM with -enable-shrink-wrap. Related to <rdar://problem/20821730> llvm-svn: 242908
* [X86][AVX512] add reduce/range/scalef/rndScaleAsaf Badouh2015-07-228-0/+1832
| | | | | | | | include encoding and intrinsics Differential Revision: http://reviews.llvm.org/D11222 llvm-svn: 242896
* Fix test from r242886 to use the right triple.Michael Kuperstein2015-07-221-0/+1
| | | | llvm-svn: 242889
* [X86] Add .intel_syntax noprefix directive to intel-syntax x86 asm outputMichael Kuperstein2015-07-221-0/+9
| | | | | | | Patch by: michael.zuckerman@intel.com Differential Revision: http://reviews.llvm.org/D11223 llvm-svn: 242886
* Fix mem2reg to correctly handle allocas only used in a single blockMichael Kuperstein2015-07-221-0/+44
| | | | | | | | | | | | | | | Currently, a load from an alloca that is used in as single block and is not preceded by a store is replaced by undef. This is not always correct if the single block is inside a loop. Fix the logic so that: 1) If there are no stores in the block, replace the load with an undef, as before. 2) If there is a store (regardless of where it is in the block w.r.t the load), bail out, and let the rest of mem2reg handle this alloca. Patch by: gil.rapaport@intel.com Differential Revision: http://reviews.llvm.org/D11355 llvm-svn: 242884
* [asan] Improve moving of non-instrumented allocasKuba Brecka2015-07-221-6/+19
| | | | | | | | In r242510, non-instrumented allocas are now moved into the first basic block. This patch limits that to only move allocas that are present *after* the first instrumented one (i.e. only move allocas up). A testcase was updated to show behavior in these two cases. Without the patch, an alloca could be moved down, and could cause an invalid IR. Differential Revision: http://reviews.llvm.org/D11339 llvm-svn: 242883
* AVX-512: Added intrinsics for VCVT* instructions.Elena Demikhovsky2015-07-226-40/+1330
| | | | | | | | All SKX forms. All VCVT instructions for float/double/int/long types. Differential Revision: http://reviews.llvm.org/D11343 llvm-svn: 242877
* [LoopUnswitch] Code refactoring to separate trivial loop unswitch and ↵Chen Li2015-07-221-0/+28
| | | | | | | | | | | | | | non-trivial loop unswitch in processCurrentLoop() Summary: The current code in LoopUnswtich::processCurrentLoop() mixes trivial loop unswitch and non-trivial loop unswitch together. It goes over all basic blocks in the loop and checks if a condition is trivial or non-trivial unswitch condition. However, trivial unswitch condition can only occur in the loop header basic block (where it controls whether or not the loop does something at all). This refactoring separate trivial loop unswitch and non-trivial loop unswitch. Before going over all basic blocks in the loop, it checks if the loop header contains a trivial unswitch condition. If so, unswitch it. Otherwise, go over all blocks like before but don't check trivial condition any more since they are not possible to be in the other blocks. This code has no functionality change. Reviewers: meheff, reames, broune Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11276 llvm-svn: 242873
* [BranchFolding] do not iterate the aliases of virtual registersJingyue Wu2015-07-221-0/+24
| | | | | | | | | | | | | | | | | Summary: MCRegAliasIterator only works for physical registers. So, do not run it on virtual registers. With this issue fixed, we can resurrect the BranchFolding pass in NVPTX backend. Reviewers: jholewinski, bkramer Subscribers: henryhu, meheff, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11174 llvm-svn: 242871
* [SROA] Fix a nasty pile of bugs to do with big-endian, different allocaChandler Carruth2015-07-223-12/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | types and loads, loads or stores widened past the size of an alloca, etc. This started off with a bug report about big-endian behavior with bitfields and loads and stores to a { i32, i24 } struct. An initial attempt to fix this was sent for review in D10357, but that didn't really get to the root of the problem. The core issue was that canConvertValue and convertValue in SROA were handling different bitwidth integers by doing a zext of the integer. It wouldn't do a trunc though, only a zext! This would in turn lead SROA to form an i24 load from an i24 alloca, zext it to i32, and then use it. This would at least produce the wrong value for big-endian systems. One of my many false starts here was to correct the computation for big-endian systems by shifting. But this doesn't actually work because the original code has a 64-bit store to the entire 8 bytes, and a 32-bit load of the last 4 bytes, and because the alloc size is 8 bytes, we can't lose that last (least significant if bigendian) byte! The real problem here is that we're forming an i24 load in SROA which is actually not sufficiently wide to load all of the necessary bits here. The source has an i32 load, and SROA needs to form that as well. The straightforward way to do this is to disable the zext logic in canConvertValue and convertValue, forcing us to actually load all 32-bits. This seems like a really good change, but it in turn breaks several other parts of SROA. First in the chain of knock-on failures, we had places where we were doing integer-widening promotion even though some of the integer loads or stores extended *past the end* of the alloca's memory! There was even a comment about preventing this, but it only prevented the case where the type had a different bit size from its store size. So I added checks to handle the cases where we actually have a widened load or store and to avoid trying to special integer widening promotion in those cases. Second, we actually rely on the ability to promote in the face of loads past the end of an alloca! This is important so that we can (for example) speculate loads around PHI nodes to do more promotion. The bits loaded are garbage, but as long as they aren't used and the alignment is suitable high (which it wasn't in the test case!) this is "fine". And we can't stop promoting here, lots of things stop working well if we do. So we need to add specific logic to handle the extension (and truncation) case, but *only* where that extension or truncation are over bytes that *are outside the alloca's allocated storage* and thus totally bogus to load or store. And of course, once we add back this correct handling of extension or truncation, we need to correctly handle bigendian systems to avoid re-introducing the exact bug that started us off on this chain of misery in the first place, but this time even more subtle as it only happens along speculated loads atop a PHI node. I've ported an existing test for PHI speculation to the big-endian test file and checked that we get that part correct, and I've added several more interesting big-endian test cases that should help check that we're getting this correct. Fun times. llvm-svn: 242869
* [dsymutil] Implement ODR uniquing for C++ code.Frederic Riss2015-07-2116-0/+1190
| | | | | | | | | | | | | | | | | This optimization allows the DWARF linker to reuse definition of types it has emitted in previous CUs rather than reemitting them in each CU that references them. The size and link time gains are huge. For example when linking the DWARF for a debug build of clang, this generates a ~150M dwarf file instead of a ~700M one (the numbers date back a bit and must not be totally accurate these days). As with all the other parts of the llvm-dsymutil codebase, the goal is to keep bit-for-bit compatibility with dsymutil-classic. The code is littered with a lot of FIXMEs that should be addressed once we can get rid of the compatibilty goal. llvm-svn: 242847
* MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset.Alex Lorenz2015-07-213-0/+89
| | | | | | | | This commit begins serialization of the CFI index machine operands by serializing one kind of CFI instruction - the .cfi_def_cfa_offset instruction. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242845
* [MDA] change BlockScanLimit into a command line option.Jingyue Wu2015-07-211-0/+15
| | | | | | | | | | | | | | | | | | | | Summary: In the benchmark (https://github.com/vetter/shoc) we are researching, the duplicated load is not eliminated because MemoryDependenceAnalysis hit the BlockScanLimit. This patch change it into a command line option instead of a hardcoded value. Patched by Xuetian Weng. Test Plan: test/Analysis/MemoryDependenceAnalysis/memdep-block-scan-limit.ll Reviewers: jingyue, reames Subscribers: reames, llvm-commits Differential Revision: http://reviews.llvm.org/D11366 llvm-svn: 242842
* [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-07-211-3/+9
| | | | | | | | | Check whether BaseCst is valid before extracting a GlobalValue. This fixes PR24163. Patch by David Majnemer. llvm-svn: 242840
* [Object][ELF] Handle files with no section header string table.Michael J. Spencer2015-07-212-0/+10
| | | | llvm-svn: 242839
* [PPC64LE] More vector swap optimization TLCBill Schmidt2015-07-211-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
* Re-land 242726 to use RAII to do cleanupReid Kleckner2015-07-211-0/+86
| | | | | | | The LooksLikeCodeInBug11395() codepath was returning without clearing the ProcessedAllocas cache. llvm-svn: 242809
* MergeFunc: Transfer the callee's attributes when replacing a direct callerArnold Schwaighofer2015-07-211-0/+40
| | | | | | | | | | We insert a bitcast which obfuscates the getCalledFunction for the utility function which looks up attributes from the called function. Loosing ABI changing parameter attributes is a bad thing. rdar://21516488 llvm-svn: 242807
* MIR Serialization: Serialize the external symbol machine operands.Alex Lorenz2015-07-211-0/+60
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242806
* Revert 242726, it broke ASan on OS X.Nico Weber2015-07-211-73/+0
| | | | llvm-svn: 242792
* Constfold trunc,rint,nearbyint,ceil and floor using APFloatKarthik Bhat2015-07-211-0/+65
| | | | | | | | A patch by Chakshu Grover! This patch allows constfolding of trunc,rint,nearbyint,ceil and floor intrinsics using APFloat class. Differential Revision: http://reviews.llvm.org/D11144 llvm-svn: 242763
* AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , Igor Breger2015-07-214-0/+460
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11351 llvm-svn: 242761
* [ARM] Define subtarget feature "reserve-r9", which is used to decideAkira Hatanaka2015-07-212-2/+2
| | | | | | | | | | | | | | | | | | | | whether register r9 should be reserved. This recommits r242737, which broke bots because the number of subtarget features went over the limit of 64. This change is needed because we cannot use a backend option to set cl::opt "arm-reserve-r9" when doing LTO. Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to reserve r9 should make changes to add subtarget feature "reserve-r9" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11320 llvm-svn: 242756
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