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* X86 cost model: Add cost for vectorized gather/scatherArnold Schwaighofer2013-07-121-0/+86
| | | | | | radar://14351991 llvm-svn: 186189
* ARM cost model: Add cost for gather/scatherArnold Schwaighofer2013-07-121-0/+88
| | | | | | | | | | Fixes a 35% degradation compared to unvectorized code in MiBench/automotive-susan and an equally serious regression on a private image processing benchmark. radar://14351991 llvm-svn: 186188
* Relax the test a bit more to handle different UIDs and GIDs.Rafael Espindola2013-07-121-1/+1
| | | | llvm-svn: 186186
* Relax test a bit to handle umask differences.Rafael Espindola2013-07-121-1/+1
| | | | llvm-svn: 186184
* Add a test for the 'o' option in llvm-ar.Rafael Espindola2013-07-121-0/+10
| | | | llvm-svn: 186183
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-0/+9
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-0/+79
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-0/+24
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-121-0/+13
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-121-0/+12
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-124-0/+60
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* X86: Shrink certain forms of movsx.Benjamin Kramer2013-07-124-6/+27
| | | | | | | | | | | | In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. llvm-svn: 186174
* X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when ↵Stephen Lin2013-07-122-0/+494
| | | | | | | | possible Patch by Andrea Di Biagio llvm-svn: 186165
* Start using CHECK-LABEL in some tests.Stephen Lin2013-07-1212-110/+111
| | | | llvm-svn: 186163
* Add new directive called CHECK-LABEL to FileCheck.Stephen Lin2013-07-121-0/+51
| | | | | | | | CHECK-LABEL is meant to be used in place on CHECK on lines containing identifiers or other unique labels (they need not actually be labels in the source or output language, though.) This is used to break up the input stream into separate blocks delineated by CHECK-LABEL lines, each of which is checked independently. This greatly improves the accuracy of errors and fix-it hints in many cases, and allows for FileCheck to recover from errors in one block by continuing to subsequent blocks. Some tests will be converted to use this new directive in forthcoming patches. llvm-svn: 186162
* Don't reject an empty archive.Rafael Espindola2013-07-122-0/+4
| | | | llvm-svn: 186159
* Revert "indvars: Improve LFTR by eliminating truncation when comparingChandler Carruth2013-07-121-25/+0
| | | | | | | | | | | | | | | | | | | against a constant." This reverts commit r186107. It didn't handle wrapping arithmetic in the loop correctly and thus caused the following C program to count from 0 to UINT64_MAX instead of from 0 to 255 as intended: #include <stdio.h> int main() { unsigned char first = 0, last = 255; do { printf("%d\n", first); } while (first++ != last); } Full test case and instructions to reproduce with just the -indvars pass sent to the original review thread rather than to r186107's commit. llvm-svn: 186152
* Add support for Mips break and syscall insructions. The corresponding test ↵Vladimir Medic2013-07-121-0/+10
| | | | | | cases are added. llvm-svn: 186151
* [SystemZ] Add test missing from r186148Richard Sandiford2013-07-121-0/+82
| | | | | | Sigh, twice in two days sorry. One day I'll remember... llvm-svn: 186150
* [SystemZ] Optimize sign-extends of vector setccsRichard Sandiford2013-07-121-0/+70
| | | | | | | | | | | | | Normal (sext (setcc ...)) sequences are optimised into (select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND. However, this is deliberately not done for vectors, and after vector type legalization we have (sext_inreg (setcc ...)) instead. I wondered about trying to extend DAGCombiner to handle this case too, but it seemed to be a loss on some other targets I tried, even those for which SETCC isn't "legal" and SELECT_CC is. llvm-svn: 186149
* [SystemZ] Improve spilling of LGDR and LDGRRichard Sandiford2013-07-121-0/+288
| | | | | | | If the source of these instructions is spilled we should load the destination. If the destination is spilled we should store the source. llvm-svn: 186147
* SLPVectorizer: Sink and enable CSE for ExtractElements.Nadav Rotem2013-07-123-4/+4
| | | | llvm-svn: 186145
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-122-0/+38
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* llvm/test/Object/archive-toc.test: Use env(1) to satisfy win32 hosts.NAKAMURA Takumi2013-07-121-8/+4
| | | | llvm-svn: 186143
* SLPVectorize: Replace the code that checks for vectorization candidates in ↵Nadav Rotem2013-07-121-0/+74
| | | | | | | | successor blocks with code that scans PHINodes. Before we could vectorize PHINodes scanning successors was a good way of finding candidates. Now we can vectorize the phinodes which is simpler. llvm-svn: 186139
* Add the ability to use guarded malloc when running llvm lit tests.David Dean2013-07-111-0/+20
| | | | llvm-svn: 186134
* In response to dblaikie's comment on r186035, replacing theAdrian Prantl2013-07-111-136/+163
| | | | | | | | (reduced LLVM IR) + (full source in comment) with the (full LLVM IR) + (reduced src in comment) llvm-svn: 186119
* Add tests for the before and after modifiers.Rafael Espindola2013-07-111-0/+20
| | | | llvm-svn: 186118
* Add a test for llvm-ar's m operation.Rafael Espindola2013-07-111-0/+30
| | | | llvm-svn: 186110
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-111-0/+18
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. llvm-svn: 186108
* indvars: Improve LFTR by eliminating truncation when comparing against a ↵Andrew Trick2013-07-111-0/+25
| | | | | | | | | | | | | | | | | constant. Patch by Michele Scandale! Adds a special handling of the case where, during the loop exit condition rewriting, the exit value is a constant of bitwidth lower than the type of the induction variable: instead of introducing a trunc operation in order to match correctly the operand types, it allows to convert the constant value to an equivalent constant, depending on the initial value of the induction variable and the trip count, in order have an equivalent comparison between the induction variable and the new constant. llvm-svn: 186107
* PPCDAGToDAGISel::isRunOfOnes should return false on zeroHal Finkel2013-07-111-0/+27
| | | | | | | | | | | | This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI with an out-of-range operand. Most uses of the isRunOfOnes function are guarded by a condition that the value is not zero. This was not true in two places, and in both places a zero input would result in an out-of-rage MB value (= 32). To fix this, isRunOfOnes returns false on a zero input (and I've remove one now-redundant guard). llvm-svn: 186101
* Fix a FIXME about the format and add a test.Rafael Espindola2013-07-111-8/+23
| | | | | | | While at it, use strftime on Unix too and use the thread safe versions of localtime. llvm-svn: 186090
* LoopVectorize: Vectorize all accesses in address space zero with unit strideArnold Schwaighofer2013-07-111-0/+61
| | | | | | | | | | | We can vectorize them because in the case where we wrap in the address space the unvectorized code would have had to access a pointer value of zero which is undefined behavior in address space zero according to the LLVM IR semantics. (Thank you Duncan, for pointing this out to me). Fixes PR16592. llvm-svn: 186088
* Merge these tests.Rafael Espindola2013-07-115-35/+16
| | | | llvm-svn: 186084
* Use a more unique name to avoid conflicting with directory.ll tests when runningRafael Espindola2013-07-111-19/+19
| | | | | | in parallel. llvm-svn: 186083
* Add a test for llvm-ar's 'd' operation.Rafael Espindola2013-07-111-0/+30
| | | | llvm-svn: 186082
* Add tests for the 'x' operation.Rafael Espindola2013-07-111-0/+20
| | | | llvm-svn: 186081
* [SystemZ] Add testcase missing from r186073Richard Sandiford2013-07-111-0/+266
| | | | llvm-svn: 186074
* [SystemZ] Use zeroing form of RISBG for shift-and-AND sequencesRichard Sandiford2013-07-111-2/+2
| | | | | | Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
* [SystemZ] Use zeroing form of RISBG for some AND sequencesRichard Sandiford2013-07-1126-262/+376
| | | | | | | | | | | | RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. llvm-svn: 186072
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-113-12/+12
| | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070
* TryToSimplifyUncondBranchFromEmptyBlock was checking that any commonDuncan Sands2013-07-111-1/+239
| | | | | | | | | | predecessors of the two blocks it is attempting to merge supply the same incoming values to any phi in the successor block. This change allows merging in the case where there is one or more incoming values that are undef. The undef values are rewritten to match the non-undef value that flows from the other edge. Patch by Mark Lacey. llvm-svn: 186069
* RegScavenger should not exclude undef usesHal Finkel2013-07-111-0/+48
| | | | | | | | | | | | | | When computing currently-live registers, the register scavenger excludes undef uses. As a result, undef uses are ignored when computing the restore points of registers spilled into the emergency slots. While the register scavenger normally excludes from consideration, when scavenging, registers used by the current instruction, we need to not exclude undef uses. Otherwise, we might end up requiring more emergency spill slots than we have (in the case where the undef use *is* the currently-spilled register). Another bug found by llvm-stress. llvm-svn: 186067
* Consolidate more lit tests.Nadav Rotem2013-07-113-62/+54
| | | | llvm-svn: 186063
* Consolidate some of the lit tests.Nadav Rotem2013-07-114-75/+57
| | | | llvm-svn: 186062
* Consolidate some of the lit tests.Nadav Rotem2013-07-115-61/+191
| | | | llvm-svn: 186060
* Teach TailRecursionElimination to handle certain cases of nocapture escaping ↵Michael Gottesman2013-07-112-25/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | allocas. Without the changes introduced into this patch, if TRE saw any allocas at all, TRE would not perform TRE *or* mark callsites with the tail marker. Because TRE runs after mem2reg, this inadequacy is not a death sentence. But given a callsite A without escaping alloca argument, A may not be able to have the tail marker placed on it due to a separate callsite B having a write-back parameter passed in via an argument with the nocapture attribute. Assume that B is the only other callsite besides A and B only has nocapture escaping alloca arguments (*NOTE* B may have other arguments that are not passed allocas). In this case not marking A with the tail marker is unnecessarily conservative since: 1. By assumption A has no escaping alloca arguments itself so it can not access the caller's stack via its arguments. 2. Since all of B's escaping alloca arguments are passed as parameters with the nocapture attribute, we know that B does not stash said escaping allocas in a manner that outlives B itself and thus could be accessed indirectly by A. With the changes introduced by this patch: 1. If we see any escaping allocas passed as a capturing argument, we do nothing and bail early. 2. If we do not see any escaping allocas passed as captured arguments but we do see escaping allocas passed as nocapture arguments: i. We do not perform TRE to avoid PR962 since the code generator produces significantly worse code for the dynamic allocas that would be created by the TRE algorithm. ii. If we do not return twice, mark call sites without escaping allocas with the tail marker. *NOTE* This excludes functions with escaping nocapture allocas. 3. If we do not see any escaping allocas at all (whether captured or not): i. If we do not have usage of setjmp, mark all callsites with the tail marker. ii. If there are no dynamic/variable sized allocas in the function, attempt to perform TRE on all callsites in the function. Based off of a patch by Nick Lewycky. rdar://14324281. llvm-svn: 186057
* Move r186044 tests into CodeGen/X86Hal Finkel2013-07-112-4/+2
| | | | | | | | I had thought that these tests could be target-neutral, but in practice this is not the case (on some targets, like Hexagon and Darwin), they trigger an assert (a different assert than the one that r186044 fixes). llvm-svn: 186051
* Set REQUIRES shell on the test cases for r186044Hal Finkel2013-07-102-0/+2
| | | | | | Trying to fix the i686-mingw32 build. llvm-svn: 186046
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