summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [InstSimplify] Teach InstSimplify how to simplify extractelementDavid Majnemer2015-07-131-0/+14
| | | | llvm-svn: 242008
* [InstSimplify] Teach InstSimplify how to simplify extractvalueDavid Majnemer2015-07-131-0/+9
| | | | llvm-svn: 242007
* [ARM] Add support for nest attribute using r12Renato Golin2015-07-121-0/+21
| | | | | | | | | | | | | | | | Register r12 ('ip') is used by GCC for this purpose and hence is used here. As discussed on the GCC mailing list, the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible. A similar patch has just gone in the AArch64 backend, so this is just the ARM counterpart, following the same discussion. Patch by Stephen Cross. llvm-svn: 241996
* [X86][SSE] Tidied up vector extend/truncation tests. NFCI.Simon Pilgrim2015-07-124-79/+81
| | | | llvm-svn: 241995
* [X86][SSE] Vectorized v4i32 non-uniform shifts.Simon Pilgrim2015-07-127-362/+262
| | | | | | | | | | While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
* [LICM] Don't try to sink values out of loops without any exitsDavid Majnemer2015-07-121-0/+19
| | | | | | | | | | | | | There is no suitable basic block to sink instructions in loops without exits. The only way an instruction in a loop without exits can be used is as an incoming value to a PHI. In such cases, the incoming block for the corresponding value is unreachable. This fixes PR24013. Differential Revision: http://reviews.llvm.org/D10903 llvm-svn: 241987
* [PowerPC] Make use of the TargetRecip systemHal Finkel2015-07-121-0/+15
| | | | | | | | | | r238842 added the TargetRecip system for controlling use of reciprocal estimates for sqrt and division using a set of parameters that can be set by the frontend. Clang now supports a sophisticated -mrecip option, and this will allow that option to effectively control the relevant code-generation functionality of the PPC backend. llvm-svn: 241985
* [PowerPC] Support the nest parameter attributeHal Finkel2015-07-122-0/+68
| | | | | | | | | | | | | This adds support for the 'nest' attribute, which allows the static chain register to be set for functions calls under non-Darwin PPC/PPC64 targets. r11 is the chain register (which the PPC64 ELF ABI calls the "environment pointer"). For indirect calls under PPC64 ELFv1, this would normally be loaded from the function descriptor, but providing an explicit 'nest' parameter will override that process and use the value provided. This allows __builtin_call_with_static_chain to work as expected on PowerPC. llvm-svn: 241984
* Revert "Revert r236894 "[BasicAA] Fix zext & sext handling""Hal Finkel2015-07-112-0/+197
| | | | | | | | | | | r236894 caused PR23626 (Clang miscompiles webkit's base64 decoder), and was reverted in r237984. This reapplies the patch with an additional test case for PR23626 and the associated fix (both scales and offsets in the BasicAliasAnalysis::constantOffsetHeuristic should initially be zero). Patch by Nick White, thanks! llvm-svn: 241981
* Add argmemonly attribute.Igor Laevsky2015-07-112-2/+54
| | | | | | | | This change adds new attribute called "argmemonly". Function marked with this attribute can only access memory through it's argument pointers. This attribute directly corresponds to the "OnlyAccessesArgumentPointees" ModRef behaviour in alias analysis. Differential Revision: http://reviews.llvm.org/D10398 llvm-svn: 241979
* Renamed some uses of unroll to interleave in the vectorizer.Tyler Nowicki2015-07-111-2/+2
| | | | llvm-svn: 241971
* MIR Serialization: Serialize the virtual register operands.Alex Lorenz2015-07-102-4/+102
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D11005 llvm-svn: 241959
* [InstCombine] Actually combine AA metadata when replacing one load with anotherBjorn Steinbrink2015-07-101-4/+2
| | | | | | Fixes PR24083 llvm-svn: 241955
* [SEH] Push reloads of the SEH code past phi nodesReid Kleckner2015-07-101-0/+91
| | | | | | | | | | | This in turn would sometimes introduce new cleanupblocks that didn't previously exist. The uses were being introduced by SSA value demotion. We actually want to *promote* uses of EH pointers and selectors, so I added some spcecial casing to avoid demoting such instructions. This is getting overly complicated, but hopefully we'll come along and delete it in the new representation. llvm-svn: 241950
* DAGCombiner: Assume invariant load cannot alias a storeMatt Arsenault2015-07-101-0/+35
| | | | | | | | | | The motivation is to allow GatherAllAliases / FindBetterChain to not give up on dependent loads of a pointer from constant memory. This is important for AMDGPU, because most loads are pointers derived from a load of a kernel argument from constant memory. llvm-svn: 241948
* [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.Quentin Colombet2015-07-102-0/+78
| | | | | | | Although this is not incorrect to insert such code, it is useless and it hurts the binary size. llvm-svn: 241946
* Fix AArch64 prologue for empty frame with dynamic allocas.Evgeniy Stepanov2015-07-101-0/+50
| | | | | | | | Fixes PR23804: assertion failure in emitPrologue in the case of a function with an empty frame and a dynamic alloca that needs stack realignment. This is a typical case for AddressSanitizer. llvm-svn: 241943
* [Object][ELF] Handle the dynamic string table in files without a section table.Michael J. Spencer2015-07-101-1/+29
| | | | llvm-svn: 241937
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-101-4/+52
| | | | | | | | | | | | This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 241928
* ComputeKnownBits: be a bit smarter about ADDsFiona Glaser2015-07-102-7/+8
| | | | | | | | If our two inputs have known top-zero bit counts M and N, we trivially know that the output cannot have any bits set in the top (min(M, N)-1) bits, since nothing could carry past that point. llvm-svn: 241927
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-106-16/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926
* MIR Serialization: Initial serialization of stack objects.Alex Lorenz2015-07-101-0/+39
| | | | | | | | | | | | | | This commit implements the initial serialization of stack objects from the MachineFrameInfo class. It can only serialize the ordinary stack objects (including ordinary spill slots), but it doesn't serialize variable sized or fixed stack objects yet. The stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset and alignment. The stack objects are a part of machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 241922
* ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun2015-07-101-2/+2
| | | | | | | | | | | | | | | | | | | | | This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920
* Actually support volatile memcpys in NVPTX loweringEli Bendersky2015-07-101-0/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D11091 llvm-svn: 241914
* [InstSimplify] Fold away ord/uno fcmps when nnan is present.Benjamin Kramer2015-07-101-0/+15
| | | | | | | This is important to fold away the slow case of complex multiplies emitted by clang. llvm-svn: 241911
* Add support for fast-math flags to the FCmp instruction.James Molloy2015-07-101-0/+23
| | | | | | | | | | | | | | FCmp behaves a lot like a floating-point binary operator in many ways, and can benefit from fast-math information. Flags such as nsz and nnan can affect if this fcmp (in combination with a select) can be treated as a fminnum/fmaxnum operation. This adds backwards-compatible bitcode support, IR parsing and writing, LangRef changes and IRBuilder changes. I'll need to audit InstSimplify and InstCombine in a followup to find places where flags should be copied. llvm-svn: 241901
* Disable loop re-rotation for -Oz (patch by Andrey Turetsky)Alexey Bataev2015-07-101-0/+30
| | | | | | | After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too. Differential Revision: http://reviews.llvm.org/D10961 llvm-svn: 241897
* Revert the new EH instructionsDavid Majnemer2015-07-102-71/+2
| | | | | | This reverts commits r241888-r241891, I didn't mean to commit them. llvm-svn: 241893
* Tighten the verifier check for catchblock.David Majnemer2015-07-101-6/+6
| | | | llvm-svn: 241891
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-102-2/+71
| | | | | | | | | | | | | | | Summary: This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11041 llvm-svn: 241888
* [InstCombine] Employ AliasAnalysis in FindAvailableLoadedValueBjorn Steinbrink2015-07-101-0/+15
| | | | llvm-svn: 241887
* [InstCombine] Properly combine metadata when replacing a load with anotherBjorn Steinbrink2015-07-101-0/+31
| | | | | | | | Not doing this can lead to misoptimizations down the line, e.g. because of range metadata on the replacing load excluding values that are valid for the load that is being replaced. llvm-svn: 241886
* [NVPTX] declare no vector registersJingyue Wu2015-07-101-0/+39
| | | | | | | | | | | | | | | | | Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
* [WinEH] Make sure LSDA tables are 4 byte alignedReid Kleckner2015-07-105-0/+6
| | | | | | | | | | Apparently this is important, otherwise _except_handler3 assumes that the registration node is corrupted and ignores it. Also fix a bug in WinEHPrepare where we would insert code after a terminator instruction. llvm-svn: 241877
* [x86] enable machine combiner reassociations for scalar double-precision ↵Sanjay Patel2015-07-091-0/+23
| | | | | | multiplies llvm-svn: 241873
* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-091-1/+23
| | | | llvm-svn: 241871
* [Object][ELF] Support dumping hash-tables from files with no section table.Michael J. Spencer2015-07-092-0/+8
| | | | | | This time without breaking the bots. llvm-svn: 241869
* MIR Serialization: Serialize the virtual register definitions.Alex Lorenz2015-07-092-0/+61
| | | | | | | | | | | | The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
* [WinEH] Give up on using CSRs across 32-bit invokes for nowReid Kleckner2015-07-092-23/+37
| | | | | | | | | | | The runtime does not restore CSRs when transferring control back to the function handling the exception. According to the experts on IRC, LLVM's register allocator has no way to model register clobbers that only happen on one edge of the CFG. For now, don't worry about trying to use the meager three CSRs available on 32-bit X86 and just say that such invokes preserve nothing. llvm-svn: 241865
* MIR Parser: Report an error when parsing machine function with an empty body.Alex Lorenz2015-07-097-0/+39
| | | | | | | | | | This commit adds a new error which is reported when the MIR Parser encounters a machine function without any machine basic blocks. The machine verifier expects that the machine functions have at least one MBB, and this error will prevent machine functions without MBBs from reaching the machine verifier and crashing with an assertion. llvm-svn: 241862
* [ImplicitNullChecks] Be smarter in picking the memory op.Sanjoy Das2015-07-092-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change ImplicitNullChecks would only pick loads of the form: ``` test Reg, Reg jz elsewhere fallthrough: movl 32(Reg), Reg2 ``` but not (say) ``` test Reg, Reg jz elsewhere fallthrough: inc Reg3 movl 32(Reg), Reg2 ``` This change teaches ImplicitNullChecks to look through "unrelated" instructions like `inc Reg3` when searching for a load instruction to convert to a trapping load. Reviewers: atrick, JosephTremoulet, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11044 llvm-svn: 241850
* Create BSD archives by default on OS X.Rafael Espindola2015-07-091-1/+1
| | | | | | | | | They should probably be created on anything that is not windows or linux, but I will test on freebsd before changing that. With this it is possible to bootstrap with llvm-ar instead of ar+ranlib on OS X. llvm-svn: 241849
* MIR Serialization: Serialize the simple MachineFrameInfo attributes.Alex Lorenz2015-07-091-0/+91
| | | | | | | | | | | | This commit serializes the 13 scalar boolean and integer attributes from the MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap, HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack, HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and HasMustTailInVarArgFunc. These attributes are serialized as part of the frameInfo YAML mapping, which itself is a part of the machine function's YAML mapping. llvm-svn: 241844
* llvm-ar: Pad the symbol table to 4 bytes.Rafael Espindola2015-07-091-0/+8
| | | | | | | It looks like ld64 requires it. With this we seem to be able to bootstrap using llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2). llvm-svn: 241842
* [IndVars] Try to use existing values in RewriteLoopExitValues.Sanjoy Das2015-07-091-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RewriteLoopExitValues, before expanding out an SCEV expression using SCEVExpander, try to see if an existing LLVM IR expression already computes the value we're interested in. If so use that existing expression. Apart from reducing IndVars' reliance on the rest of the compilation pipeline, this also prevents IndVars from concluding some expressions as "high cost" when they're not. For instance, `InductiveRangeCheckElimination` often emits code of the following form: ``` len = umin(len_A, len_B) loop: ... if (i++ < len) goto loop outside_loop: use(i) ``` `SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`, since it thinks the value of `i` on loop exit, `len`, is a high cost expansion since it contains an `umax` in it. With this change, `IndVars` can see that it can re-use `len` instead of creating a new expression to compute `umin(len_A, len_B)`. I considered putting this cleverness in `SCEVExpander`, but I was worried that it may then have a deterimental effect on other passes that use it. So I decided it was better to just do this in the one place where it seems like an obviously good idea, with the intent of generalizing later if needed. Reviewers: atrick, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10782 llvm-svn: 241838
* [llvm-readobj] Print MIPS PLT tableSimon Atanasyan2015-07-092-0/+34
| | | | | | Now the -mips-plt-got prints both MIPS GOT and PLT tables. llvm-svn: 241836
* [yaml2obj] Initialize sh_addralign field for the .symtab sectionSimon Atanasyan2015-07-091-0/+3
| | | | llvm-svn: 241835
* [ELF] Explicitly configure sections alignment in the tests. NFCSimon Atanasyan2015-07-092-0/+2
| | | | llvm-svn: 241834
* [llvm-objdump] Require that jump targets shown in -d are functionsDavid Majnemer2015-07-091-0/+4
| | | | | | | Don't let the disassembler pick call <.text> if a function happens to live at the start of the section by only using function symbols. llvm-svn: 241830
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-092-0/+42
| | | | | | | | | | This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
OpenPOWER on IntegriCloud